Flip-chip Devices Research Articles

60‐5: Late‐News Paper: External Quantum Efficiency of All InGaN Polychromic MicroLEDs

This paper reports on the performance results including radiance, dominant wavelength, and forward voltage of monolithic MicroLEDs that can emit red, green, and blue light simultaneously and are thus described as polychromic. Further, flip chip devices have been fabricated to facilitate absolute EQE external quantum efficiency (EQE) measurements. The peak EQE for a 20 × 17 µm device are 2.0 % in red, 14.2% in green, and 17.5% in blue.

Pixel detector hybridisation and integration with anisotropic conductive adhesives

A reliable and cost-effective interconnect technology is required for the development of hybrid pixel detectors. The interconnect technology needs to be adapted for the pitch and die sizes of the respective applications. This contribution presents recent results of a newly developed in-house single-die interconnection process based on Anisotropic Conductive Adhesives (ACA). The ACA interconnect technology replaces solder bumps with conductive micro-particles embedded in an epoxy layer applied as either film or paste. The electro-mechanical connection between the sensor and ASIC is achieved via thermocompression of the ACA using a flip-chip device bonder. The ACA technology can also be used for ASIC-PCB/FPC integration, replacing wire bonding or large-pitch solder bumping techniques. A specific pixel-pad topology is required to enable the connection via micro-particles and create cavities into which excess epoxy can flow. This pixel-pad topology is achieved with an in-house Electroless Nickel Immersion Gold (ENIG) process. The ENIG and ACA processes are qualified with a variety of different ASICs, sensors, and dedicated interconnect test structures, with pad diameters ranging from 12 μm to 140 μm and pitches between 20 μm and 1.3 mm. The produced assemblies are characterized electrically, with radioactive-source exposures, and in tests with high-momentum particle beams. This contribution introduces the developed interconnect and plating processes and showcases different hybrid assemblies produced and tested with the above-mentioned methods. A focus is placed on recent optimization of the plating and interconnect processes, resulting in an improved plating uniformity and interconnect yield.

Development of novel single-die hybridisation processes for small-pitch pixel detectors

Hybrid pixel detectors require a reliable and cost-effective interconnect technology adapted to the pitch and die sizes of the respective applications. During the ASIC and sensor R&D phase, especially for small-scale applications, such interconnect technologies need to be suitable for the assembly of single dies, typically available from Multi-Project-Wafer submissions. Within the CERN EP R&D programme and the AIDAinnova collaboration, innovative hybridisation concepts targeting vertex-detector applications at future colliders are under development. Recent results of two novel interconnect methods for pixel pitches of 25 µm and 55 µm are presented in this contribution — an industrial fine-pitch SnAg solder bump-bonding process adapted to single-die processing using support wafers, as well as a newly developed in-house single-die interconnection process based on Anisotropic Conductive Film (ACF). The fine-pitch bump-bonding process is qualified with hybrid assemblies from a recent bonding campaign at Frauenhofer IZM. Individual CLICpix2 ASICs with 25 µm pixel pitch were bump-bonded to active-edge silicon sensors with thicknesses ranging from 50 µm to 130 µm. The device characterisation was conducted in the laboratory as well as during a beam test campaign at the CERN SPS beam-line, demonstrating an interconnect yield of about 99.7%. The ACF interconnect technology replaces the solder bumps by conductive micro-particles embedded in an epoxy film. The electro-mechanical connection between the sensor and ASIC is achieved via thermocompression of the ACF using a flip-chip device bonder. The required pixel pad topology is achieved with an in-house Electroless Nickel Immersion Gold (ENIG) plating process. This newly developed ACF hybridisation process is first qualified with the Timepix3 ASICs and sensors with 55 µm pixel pitch. The technology can be also used for ASIC-PCB/FPC integration, replacing wire bonding or large-pitch solder bumping techniques. This contribution introduces the two interconnect processes and presents preliminary hybridisation results with CLICpix2 and Timepix3 sensors and ASICs.

Pixel detector hybridisation with anisotropic conductive films

Hybrid pixel detectors require a reliable and cost-effective interconnect technology adapted to the pitch and die sizes of the respective applications. During the ASIC and sensor R&D phase, and in general for small-scale applications, such interconnect technologies need to be suitable for the assembly of single-dies, typically available from Multi-Project-Wafer submissions. Within the CERN EP R&D programme and the AIDAinnova collaboration, innovative hybridisation concepts targeting vertex-detector applications at future colliders are under development. This contribution presents recent results of a newly developed in-house single-die interconnection process based on Anisotropic Conductive Film (ACF). The ACF interconnect technology replaces the solder bumps with conductive particles embedded in an adhesive film. The electro-mechanical connection between the sensor and the read-out chip is achieved via thermo-compression of the ACF using a flip-chip device bonder. A specific pad topology is required to enable the connection via conductive particles and create cavities into which excess epoxy can flow. This pixel-pad topology is achieved with an in-house Electroless Nickel Immersion Gold (ENIG) plating process that is also under development within the project. The ENIG and ACF processes are qualified with the Timepix3 ASIC and sensors, with 55 µm pixel pitch and 14 µm pad diameter. The ACF technology can also be used for ASIC-PCB/FPC integration, replacing wire bonding or large-pitch solder bumping techniques. This contribution introduces the ENIG plating and ACF processes and presents recent results on Timepix3 hybrid assemblies.

Comprehensive Investigation of Electrical and Optical Characteristics of InGaN-Based Flip-Chip Micro-Light-Emitting Diodes.

Micro-light-emitting diodes (micro-LEDs) have been regarded as the important next-generation display technology, and a comprehensive and reliable modeling method for the design and optimization of characteristics of the micro-LED is of great use. In this work, by integrating the electrical simulation with the optical simulation, we conduct comprehensive simulation studies on electrical and optical/emission properties of real InGaN-based flip-chip micro-LED devices. The integrated simulation adopting the output of the electrical simulation (e.g., the non-uniform spontaneous emission distribution) as the input of the optical simulation (e.g., the emission source distribution) can provide more comprehensive and detailed characteristics and mechanisms of the micro-LED operation than the simulation by simply assuming a simple uniform emission source distribution. The simulated electrical and emission properties of the micro-LED were well corroborated by the measured properties, validating the effectiveness of the simulation. The reliable and practical modeling/simulation methodology reported here shall be useful to thoroughly investigate the physical mechanisms and operation of micro-LED devices.

Extraction efficiency simulation in deep ultraviolet AlGaN light emitting diodes

A ray tracing model is developed to study the light extraction efficiency (LEE) of the nitride wide band gap semiconductor deep ultraviolet light emitting diodes (DUV-LEDs). The basic device structure is flip-chip LED device with dome shape encapsulation. Various device parameters such as reflecting p-metal, absorption coefficient of the AlN layer, sapphire surface roughness etc have been examined. We have found that the transparency of the AlGaN/AlN epitaxial layers as well as the encapsulation material play key roles in improving the LEE and spatial intensity distribution. To verify the transparency of the epi-layers, highly doped n-type Al\(_{0.61}\)Ga\(_{0.39}\)N on AlN template are grown on sapphire substrate by high-temperature metalorganic chemical vapor deposition (HT-MOCVD), then the crystal and optical properties are measured and analyzed. The calculated the absorption coefficient of the AlN is below 10\(^{3}\)cm\(^{-1}\), which paves the way to achieve high extraction efficiency DUV LEDs.

On-Chip Integration of III-Nitride Flip-Chip Light-Emitting Diodes With Photodetectors

The fabrication of GaN light-emitting diodes (LEDs) with on-chip photodetectors (PDs) based on flip-chip configuration is reported. The exposed sapphire plays a key role not only in light extraction but also light guiding in the lateral direction. The same InGaN/GaN quantum well structure responsible for light emission in the LED and photodetection in the PD is characterized. The light-detecting mechanism of on-chip PDs at varying positions are also studied and verified by simulation. Compared with the design of PD adjacent to the LED, the PD formed in the center of the LED has less influence on the uniformity of the LED emission, and exhibits one-third increase in photocurrent. The flip-chip packaging device also enables a yellow phosphor film to be directly integrated onto the sapphire surface to generate white light emission. The on-chip PD is capable of detecting the variation of LED intensity without blocking the light output emission, which makes it highly valuable for real-time detection of the intensity of LED sources in various lighting applications.

Superlattice hole injection layers for UV LEDs grown on SiC

AlGaN-based germicidal UV LEDs show promise in fighting the COVID-19 pandemic through disinfection of air, water, and surfaces. We report UV LEDs grown by MOCVD on SiC substrates, fabricated into thin-film flip chip devices. Replacing the uniform p-Al x Ga1-xN layer (x = 0.2) with a short-period-superlattice of alternating (x = 0.1 and 0.8) Al-composition improved EQE from 1.3% to 2.7% (3.2% with encapsulation) at 20 A/cm2. Peak EQE and WPE values of 4.8% and 2.8% (287 nm) were measured at current densities below 2 A/cm2, and maximum output power of 7.4 mW (76 mW/mm2) was achieved at 284 nm. Further WPE improvements are expected with both superlattice and uniform layer optimization, improved p-contact metallization, and active region optimization.

Function reconsideration of indium bump in InSb IRFPAs

Indium bumps are generally accepted to possess functions of electrical connection, mechanical support and heat transfer in flip-chip devices. After comparing the distribution of stress components along different paths in InSb infrared focal plane arrays (IRFPAs), we ascertain that local enhancement effects of the stress components are remarkable in regions where the indium bumps are. More specifically, the local enhanced tensile stress in InSb chip connected with the indium bumps can lead to the local fracture of the InSb chip, and the locally enhanced shear and peeling stresses may give rise to the local interfacial delamination between the InSb chip and the indium bumps. These inferences are confirmed by the observed local failure characteristics, such as the distribution of the local delamination, the distribution of the crack widths, and the distribution of the cracks. In addition, the simulated Z-component strain distribution in InSb IRFPAs is also consistent with the backside surface profile of the InAs/GaSb IRFPAs fabricated in America with the identical structure, that is, the InSb chip glued with the indium bumps is concave downward, and the InSb chip glued with the underfill is convex upward. Judging from all these confirmed simulation results, we are confident that the indium bumps play a pivotal role in inducing the local failure of InSb IRFPAs. So the role of the indium bumps in causing the local failure of InSb IRFPAs needs to be supplemented and emphasized to comprehensively evaluate the structural reliability of InSb IRFPAs.

Effects of modulation doped n-AlGaN epilayers on the optoelectronic properties of 278-nm AlGaN-based flip-chip light-emitting devices

AlGaN-based deep ultraviolet flip-chip light-emitting diodes (DUV-FCLEDs), have been fabricated by different doping processes in n-AlGaN epilayers, respectively. That is, the silicon uniformly doped (Si-UD) processes and the modulation doped (MD) growth methods. Compared with the UD sample of about 278-nm emission wavelength, the electrical structures, optical properties and output performance of the MD sample, have been effectively enhanced. The MD sample is a more intense UV emitter than the UD sample by a factor of about 30% in the electroluminescence intensities, the photoluminescence spectra also demonstrate that the MD methods can effectively enhance the light emissions. The measured peak capacitance of internal capacitance–voltage characteristics in the UD sample is only 175 pF at room temperature, while the MD sample is about 390 pF, which is mostly attributed to the series capacitors effects within the periodic n-AlGaN super-lattices structures. Both the forward bias voltage and reverse leakage current of the MD sample are directly reduced than those of the UD sample, and the calculated conductance is significantly increased. We demonstrate that there are higher current spreading efficiency and better devices’ reliability in the MD sample with the Si-MD processes. Our investigations may be useful for the enhancements of structure and optoelectronic performance in DUV-FCLEDs succeeding the MD methods in n-AlGaN epi-layers.

Flip-chip gate-tunable acoustoelectric effect in graphene

We demonstrate a flip-chip device for performing low-temperature acoustoelectric measurements on exfoliated two-dimensional materials. With this device, we study gate-tunable acoustoelectric transport in an exfoliated monolayer graphene device, measuring the voltage created as high-frequency surface acoustic waves dynamically drive the graphene charge carriers, the density of which we simultaneously control with a silicon back-gate. We demonstrate ambipolar dependence of the acoustoelectric signal, as expected from the sign of the graphene charge carriers. We observe a marked reduction in the magnitude of the acoustoelectric signal over a well-defined range of density in the vicinity of charge neutrality, which we attribute to a spatially heterogeneous charge-disorder landscape not directly revealed by conventional transport measurements.

Rapid Solder Interconnect Fatigue Life Test Methodology for Predicting Thermomechanical Reliability

A rapid reliability test methodology was devised for simulating mechanical stresses induced from thermal expansion induced shear in temperature cycling of flip-chip devices in order to de-convolute shear stress from thermal effects in typical environmental tests. Using controlled force application according to spring deflection, a test stand was created to mechanically apply shear stress to solder interconnects in flip chip devices at isothermal conditions. The shear stress was applied cyclically using a tribometer to simulate the mechanical stresses induced in the interconnects of a device during a thermal cycle while in operation or accelerated testing. In the mechanical application of shear, the control of loading and cyclic rate can be precisely controlled while monitoring key factors for observing crack propagation and damage. In doing so, this novel approach introduces the ability to directly correlate shear stress and plastic work accumulation (damage) to fatigue life in a generic device, utilizing help from finite element models alongside data acquisition. Using the obtained correlations, lifetime predictions through early stage design analysis are possible, paving the way for a-priori optimized design for thermomechanical reliability in flip-chip devices. The methodology presented herein creates the opportunity to eliminate costly lifetime testing on multiple electronic device designs/configurations, while also expediting any data collection needed for new materials or process related impacts to reliability.

Probing Molecular Structures of Buried Interfaces in Thick Multilayered Microelectronic Packages

The fast development of flip-chip (FC) devices has helped to keep ICs on pace for Moore's law. FC devices have many buried interfaces, the structures of which all need to be investigated in order to optimize them. It is extremely difficult to examine molecular structures of buried interfaces in samples with multiple layers due to the lack of appropriate analytical tools. In this paper, real FC-on-leadframe devices, manufactured by Texas Instruments Incorporated, were investigated using the intrinsically interface-sensitive technique and sum-frequency generation (SFG) vibrational spectroscopy. By milling down the Si wafer, we can probe the polyimide (PI)/mold compound (MC) interface. By milling down further, we can examine the air/MC and the MC/leadframe (LF) interfaces. Methylene and methyl groups were detected from each of the three interfaces, and the orientation of methyl groups was determined at each interface. It was calculated that at the PI/MC interface, the methyl group tilt angle was 20° (from the surface normal). For the air/MC interface, the tilt angle was 43.5°, and for the LF/MC interface, the tilt angle was measured to be 45°. The deduced different methyl orientations at the two buried solid/solid interfaces can be interpreted by the interfacial interactions. The PI surface is more hydrophobic than the LF surface; therefore, it has more favorable interactions with the hydrophobic methyl groups, leading to a more “standing up” (smaller tilt angle) position for the methyl groups at the PI/MC interface. In this paper, SFG was successfully applied to study the buried interfaces in real devices. The SFG method used in this paper is general and can be applied to other real-world, complicated thick systems.

Evaluation of the thermal conductance of flip-chip bonding structure utilizing the measurement based on Fourier’s law of heat conduction at steady-state

Fourier’s law of heat conduction at steady-state was adopted to establish a measurement method utilizing platinum (Pt) thin-film electrodes as the heater and the temperature sensor. The thermal conductivities (κ’s) of Pyrex glass, an epoxy resin and a commercial underfill for flip-chip devices were measured and a good agreement with previously reported values was obtained. The thermal boundary resistances (RTBR’s) of Pt/sample interfaces were also extracted for discussing their influence on the thermal conduction of samples. Afterward, the flip-chip samples with 2×2 solder joint array utilizing Si wafers as the die and the substrate, without and with the underfills, were prepared and their thermal conductance were measured. For the sample without underfill, the air presenting in the gap of die and the substrate led to the poor thermal conductance of sample. With the insertion of underfills, the thermal conductance of flip-chip samples improved. The resistance to heat transfer across Si/underfill interfaces was also suppressed and to promote the thermal conductance of samples. The thermal properties of underfill and RTBR at Si/underfill interface were further implanted in the calculation of thermal conductance of flip-chip samples containing various solder joint arrays. The increasing number of solder joints diminished the influence of thermal conduction of underfill and RTBR of Si/underfill interface on the thermal conductance of samples. The insertion of underfill with high-κ value might promote the heat conductance of samples containing low-density solder joint arrays; however, it became insignificant in improving the heat conductance of samples containing high-density solder joint arrays.

Improved coupling of nanowire-based high-Tc SQUID magnetometers—simulations and experiments

Superconducting quantum interference devices (SQUIDs) based on high critical-temperature superconducting nanowire junctions were designed, fabricated, and characterized in terms of their potential as magnetometers for magnetoencephalography (MEG). In these devices, the high kinetic inductance of junctions and the thin film thickness (50 nm) pose special challenges in optimizing the field coupling. The high kinetic inductance also brings difficulties in reaching a low SQUID noise. To explore the technique for achieving a high field sensitivity, single-layer devices with a directly connected pickup loop and flip-chip devices with an inductively coupled flux transformer using a two-level coupling approach were fabricated and tested. Two-level coupling is an approach designed for flip-chip nanowire-based SQUIDs, in which a washer type SQUID pickup loop is introduced as an intermediate coupling level between the SQUID loop and the flux transformer input coil. The inductances and effective areas of all these devices were simulated. We found that at T = 77 K, flip-chip devices with the two-level coupling approach (coupling coefficient of 0.37) provided the best effective area of 0.46 mm2 among all the tested devices. With a flux noise level of 55 0 , the field sensitivity level was 240 fT . This sensitivity is not yet adequate for MEG applications but it is the best level ever reached for nanowire-based high-Tc SQUID magnetometers.

Investigation of Package Effects on the Edge Termination E-Field for HV WBG Power Semiconductors

Abstract The edge termination of a power semiconductor is defined as the spatial junction terminations around the edges of the power devices. Guard rings are used to contour the internal depletion regions and E-fields as they terminate at the edge termination, i.e. the intersection of the depletion regions and the wafer saw line where the crystal damage is located. Since there is no specific package for WBG power devices, wire bonds are still widely used to interconnect to the topside metal pads of the power devices. From previous research it is shown that wire bonding will not affect the E-field around the guard rings on a WBG device. However, planar power package, such as double-sided and power flip-chip device packaging could be a problem where the close distance between the topside of the power device and conducting plane may negatively affect the E-field distribution of the guard rings, which in turn lowers the reverse blocking capability of the WBG power device and increases leakage current creating greater on-state power loss, or even early break down. Few works have shown the Electric field distribution in embedded power modules. Therefore, a more detailed investigation and possible solution is needed for the proliferation of double-sided power packages. To investigate this packaging problem simulations were performed in Sentaurus TCAD and COMSOL based on the device physics and package geometries. Guard ring structures in 1.2kV and 10kV SiC Schottky Barrier Diode (SBD) were built and simulated in various double-sided package geometries, together with the thermal and mechanical evaluation of the package, to observe the influence on the E-field distribution in and out the WBG device. Different double-sided package structures were evaluated and a guideline (spacing/pad size/etc.) summarized for double-sided design. Moreover, a new bevel edge termination method was evaluated for double-sided WBG power semiconductor devices. Experimental reverse blocking test results will be reported in various temperature (from 25°C to 175°C) to verify the function of the package. The tests are on 1200V/50A SiC SBD (Schottky Barrier Diode) from Global Power Technology, which has double-sided Ag on both sides.

Silver free III-nitride flip chip light-emitting-diode with wall plug efficiency over 70% utilizing a GaN tunnel junction

A molecular beam epitaxy regrowth technique was demonstrated on standard industrial patterned sapphire substrate light-emitting diode (LED) epitaxial wafers emitting at 455 nm to form a GaN tunnel junction. By using an HF pretreatment on the wafers before regrowth, a voltage of 3.08 V at 20 A/cm2 was achieved on small area devices. A high extraction package was developed for comparison with flip chip devices which utilize an LED floating in silicone over a BaSO4 coated header and produced a peak external quantum efficiency (EQE) of 78%. A high reflectivity mirror was designed using a seven-layer dielectric coating backed by aluminum which has a calculated angular averaged reflectivity over 98% between 400 and 500 nm. This was utilized to fabricate a flip chip LED which had a peak EQE and wall plug efficiency of 76% and 73%, respectively. This flip chip could increase light extraction over a traditional flip chip LED due to the increased reflectivity of the dielectric based mirror.

Investigation of the Direct Plating Copper (DPC) on Al2O3, BeO or AlN Ceramic Substrates for High Power Density Applications

Abstract In the high power module applications, the power increasing and the size shrinking becomes one of the major topics for the power module design. Due to both the power increasing and the size decreasing, the power density of the device will be much increased. Therefore, not only the thermal conductivity and stability of the substrate material but the long-term material reliability of the substrate have to be seriously considered. For these reasons, the ceramic PCB becomes one of the best solutions. The ceramic substrates now used are normally based on Ag-printed or direct bonding copper (DBC) technology. In the case of the Ag-printed ceramic substrate, the pattern resolution and metallization thickness are limited by the Ag-printed process. Also the combination strength of the silver and ceramic substrate by glass (which is normally mixed in the silver paste) is normally not good enough. A thermal dissipation barrier will then be formed between silver and ceramic substrate due to the poor thermal conductivity of the glass material. For the DBC ceramic substrate, DBC substrates are manufactured at 1065°C by the diffusion between ceramic and Cu/CuO layer. A thicker Cu layer thickness of normally more than 300 um is required in the thermal compressing bonding process. The Cu pattern resolution will then be limited by the thickness of the Cu layer. However, the about 5~10% of the voids exist randomly between ceramic and Cu layer is the other major issue. The resolution issues of the Ag-printed and DBC ceramic substrates make the limitation for the device density design (fine line/width and flip-chip device design become very difficult). The glass material in the Ag printed ceramic substrate and the 5~10% voids existence in DBC ceramic substrate may cause the reliability issue operating at a high power density applications. For high power density module applications, we introduce the DPC technology on the ceramic substrate. In DPC ceramic substrate system, the sputtered Ti is used as the combination material between Cu and ceramic substrate. And the first copper is then sputtered on the top of Ti layer as seed-layer for the following Cu electrode plating (second cupper layer). By the material and the sputtering process control, several ceramic substrate raw materials can be used, such as Al2O3, AlN, BeO, Si3N4 and so on. The Ti combined/buffer layer provides good adhesion strength and material stability. The second copper layer is plated by electrode casting plating to 3 to 5 oz. (100~150um) in thickness. The key technology of the metal trace plating is the material control of the sputter layers and the second copper layer stress release during plating. In the DPC system, the double layers design is available. The laser drilled via holes on the various ceramic substrates is introduced. The conducting of the front and back side is connected by the following plating process. The key technology of this process is the stability of the via-holes. We have to make sure the via-holes cleaning, impurity removing and material stability during high temperature laser drilled is well controlled. DPC ceramic substrates provide a better metal/ceramic interface uniformity and material reliability due to the stable Ti combination material and much less voids in the metal/ceramic interface. Also, the DPC ceramic substrates provide a gold pattern resolution of 50 um line space with tight tolerance of 20 um min. We believe the material characteristic make DPC a very suitable substrate material for high power module applications.

Application of laser deprocessing technique in PFA on chemical over-etched on bond-pad issue

With technology scaling of semiconductor devices and further growth of the integrated circuit (IC)11Integrated Circuit (IC). design and function complexity, the package size has shrank down proportionally too. Hence, flip-chip solder bump mounting is the current semiconductor devices trend to replace the wire bonding technology.When come to PFA22Physical Failure Analysis (PFA). on the flip-chip devices with solder bump, wet etch for solder bump removal is an essential method. Upon using wet etch methodology; it is very dependent on etching timing and the chemical aggressiveness to get a good removal result for the solder bump. If there is an excessive period in etching or chemical reacts too aggressively, chemical over-etched on bond pad will occur. It is very unfavorable for FA33Failure Analysis (FA). engineer to perform subsequent reverse engineering on the bond pad over-etched device.In this paper, the application of laser deprocessing technique is proposed to solve the bond pad over-etched issue. This proposed technique is a quick and reversal way in deprocessing technique for defect identification in PFA.

The Direct plating copper (DPC) ceramic material on Al2O3/AlN or LTCC (Low-temperature co-fired ceramic) substrates

RESEARCH BACKGROUND: The now used ceramic substrate or sub-mounted are normally based on Ag-printed, direct bonding copper (DBC) ceramic or LTCC (Low temperature co-fired ceramic)/HTCC (High temperature co-fired ceramic) technology.Due to the limit of the screen-printed process, the resolution and conducting material thickness the Ag-printed, LTCC and HTCC substrate are poor. The poor resolutions make these materials difficult to use in high density and flip-chip device design. And the related thinner conducting material (normally <20um) limits the power rating of the design.DBC is now widely applied in power circuit design, however, duo to the copper lamination process requirement, more than 300um in thickness of copper layer is needed. Any lower copper thickness design should have an extra costly grind to reach. Also, the DBC material is difficult to provide to the multilayer trace design. OUR GOAL: We want to provide a solution with multilayer ceramic substrate for high power and high device density applications. Besides, the material properties, the adhesion of the metal/ceramic also be considered. Following are the material characteristics required for the development:A low electrical resistance material: Copper.A thick trace material thickness of more than 3 oz.A high thermal conductivity and stability ceramics with via-holes for TSV plating (Drilled Al2O3/AlN substrate ) or non- shrinking LTCC materialHigh metal trace resolution whose line width and space could be only 50 umWell metal/ceramic adhesion uniformity and strength is required: The voids between metal/ceramic < 1%; The adhesion strength> 2 kg/2*2mm2. METHODS & RESULTS: Metal trace plating: For high resolution and lower material electrical resistance request of the trace metal, we introduce electrical casting direct-plating copper (DPC) technology. The first copper is sputtered on the ceramic substrate using Ti as combined/buffer layer between copper and ceramic to provide good adhesion strength and stability. The second copper is made by electrical casting process to increase its thickness to 3 to 5 oz. (100~150um). The key technology of the metal trace plating is the material control of the sputter layers and the second copper layer stress release during plating. Multilayer Ceramic substrates: For double layers design, we use sintered Al2O3 or AlN substrates with electrical conducting via-holes design. The via-holes are made by laser drilling. And the conducting of the front and back side is connected by the following plating process. The key technology of this process is the stability of the via-holes. We have to make sure the via-holes cleaning, impurity removing and material variation during high temperature laser drilled is well controlled. For the more than three layers design, the non-shrinking LTCC is used. The dimension mismatch of the non-shrinking LTCC can controlled less than 100um., much better than that of normal LTCC/HTCC. By the correction of the following DPC process, the tolerance of the metal trace can be controlled < 30 um. The key technology of this process is the non-shrinking LTCC technology and the adhesion of the DPC metal on LTCC material.