Flip Chip Applications Research Articles

Electromigration in flip chip solder joints having a thick Cu column bump and a shallow solder interconnect

In advanced electronic products, current crowding induced electromigration failure is one of the serious problems in fine pitch flip chip solder joints. To explore a strong resistance against current crowding induced electromigration failure, a very thick Cu column bump combined with a shallow solder interconnect at 100μm pitch for flip chip applications has been studied in this paper. Results revealed that these interconnects do not fail after 720h of current stressing at 100°C with a current density of 1×104A∕cm2 based on the area of interface between Cu column bump and solder. The reduction of current crowding in the solder region by using thick Cu column bumps increased the reliability against electromigration induced failure. The current distribution in a flip chip joint of a Cu column bump combined with a shallow solder has been confirmed by simulation. However, Kirkendall void formation was found to be much serious and enhanced by electromigration at the Cu∕Cu3Sn interface due to the large Cu∕Sn ratio. Since this is a system of a limited amount of Sn and an infinite supply of Cu, the Cu6Sn5 transforms to the Cu3Sn after all the Sn content in the solder bump is consumed and the Cu3Sn can grow very thick; the vacancy flux that opposes the Cu flux will condense to form Kirkendall voids. The mechanism of electromigration induced Kirkendall void formation in the Cu column with the shallow solder joint is discussed. Furthermore, a very large temperature gradient exists across the shallow solder interconnects, leading to thermomigration. Electromigration accompanied by thermomigration could replace current crowding as a serious reliability issue in using Cu column based interconnects.

Optoelectronic and Microwave Transmission Characteristics of Indium Solder Bumps for Low-Temperature Flip-Chip Applications

This paper describes low-temperature flip-chip bonding for both optical interconnect and microwave applications. Vertical-cavity surface-emitting laser (VCSEL) arrays were flip-chip bonded onto a fused silica substrate to investigate the optoelectronic characteristics. To achieve low-temperature flip-chip bonding, indium solder bumps were used, which had a low melting temperature of 156.7degC. The current-voltage (I-V) and light-current (L-I) characteristics of the flip-chip bonded VCSEL arrays were improved by Ag coating on the indium bump. The I-V and L-I curves indicate that optical and electrical performances of Ag-coated indium bumps are superior to those of uncoated indium solder bumps. The microwave characteristics of the solder bumps were investigated by using a flip-chip-bonded coplanar waveguide (CPW) structure and by measuring the scattering parameter with an on-wafer probe station for the frequency range up to 40 GHz. The indium solder bumps, either with or without the Ag coating, provided good microwave characteristics and retained the original characteristic of the CPW signal lines without degradation of the insertion and return losses by the solder bumps

Study and characterization on the nanocomposite underfill for flip chip applications

The nanosilica filled composite is a promising material for the no-flow underfill in flip-chip application. However, as the filler size decreases into the nano length scale, the rheological, mechanical, and thermal mechanical properties of the composite change significantly. The filler-filler and filler-polymer interactions have a profound impact on the material properties. The purpose of this paper is to achieve an in-depth understanding of the effect of the filler size and surface treatment on material properties and therefore to design a nanocomposite formulation with desirable material properties for no-flow underfill applications. Mono-dispersed nanosilica filler of 100nm in size were used in this study. An epoxy/anhydride mixture was used as the base resin formulation. The nanosilica fillers were incorporated into the resin mixture to different filler loadings from 5wt% to 40wt% with or without silane coupling agents as the surface treatment. UV-Visible spectroscopy showed that the underfills with nano-size filler were transparent in the visible region even at high filler loading. The curing behavior and the Tg of the nanocomposite were studied using a modulated differential scanning calorimerter. It was found that the presence of the nanosilica could hinder the curing reaction, especially at the late stage of cure. The Tgs of the nanocomposites with untreated silica were found to decrease with the increasing filler loading. The measurement of the dynamic moduli from dynamic mechanical analyzer indicated that there was a secondary relaxation related to the filler-polymer interface. The coefficient of thermal expansion of the nanocomposite was measured using a thermal mechanical analyzer. The rheology of the nanocomposite was studied using a stress rheometer. It was found that the filler treatment could significantly reduce the viscosity of the nanocomposite and improve the processing capability of the underfill. Density measurements and moisture absorption experiments both indicated that the addition of nanosilica could increase the free volume of materials. The dispersion of the nanosilica in the cured composite materials was observed using scanning electron microscopy. Control samples with micron-size silica fillers were formulated and characterized for comparison.

Metallurgy and Kinetics of Liquid–Solid Interfacial Reaction during Lead-Free Soldering

The wetting of a molten solder on metallic surfaces is a rather complex phenomenon. In addition to physical spreading due to surface tension reduction, there are interfacial metallurgical and flux chemical reactions with the metallic substrate surface. Substrate dissolution and intermetallic formation take place rapidly during soldering. Since lead-free soldering requires substantially higher soldering temperatures (around 250 � C), the rates of intermetallic growth and substrate dissolution for lead-free solders are expected to be significantly greater than those for the current Sn–Pb eutectic solder. This study systematically investigates the metallurgy of the solid–liquid interface reactions and intermetallic growth kinetics for three lead-free solders: Sn–Ag eutectic (96.5%Sn–3.5%Ag), Sn–Cu eutectic (99.3%Sn–0.7%Cu) and Sn–Ag– Cu eutectic (Sn–3.8Ag–0.7Cu, SAC 387) with three metallic substrates: Cu, Ni, and Alloy 42 (42%Ni–52%Fe) over temperatures ranging from 225 to 280 � C for reaction time from 10 s to 16 h. Wetting behavior of these three alloys on PCBs with OSP, immersion Sn, and Ni/Au finishes, was also examined from 220 � C up to 260 � C. A thorough understanding of lead-free solder/substrate interfacial reactions should give guidance to the optimum lead-free soldering processes and to the optimum lead-free coating thicknesses for component and PCB terminal finishes, as well as for under-chip metallurgical coatings for flip-chip and BGA applications.

Thermomechanical and viscoelastic behavior of a no-flow underfill material for flip-chip applications

No-flow underfill is an alternative material technology for packaging high-speed flip-chip assemblies in microelectronics industry. In this study, the thermal expansion behavior of a cured no-flow underfill material was examined by thermomechanical analysis (TMA), and the dynamic mechanical behavior was investigated by dynamic mechanical analysis (DMA) at a fixed frequency of 1 Hz. In addition, because the no-flow underfill material is polymer-based and its mechanical properties are influenced by both temperature and time, it is important to consider its viscoelastic behavior. This was accomplished by conducting the time–temperature superposition (TTS) experiments using DMA. From the TTS results, master curves were constructed for both the storage ( E′) and the loss moduli ( E″) as a function of frequency at a pre-selected reference temperature. The shift factors along the frequency axis were also determined as a function of temperature, and they can be fitted using the Williams–Landel–Ferry (WLF) equation. Based on the master curves for E′ and E″, one can obtain the relaxation modulus, E( t, T), as a function of time and temperature. The measured thermomechanical and viscoelastic properties of the no-flow underfill material provided crucial material properties for accurately modeling the package stress.

Evaluation of lead-free SnAg solder ball deposition and reflow processes for flip chip applications

For flip chip technology solder balls, SnAg and SnAgCu are the most promising materials to replace standard SnPb solder, which will be restricted in the future because of environmental reasons [ Directive 2002/95/EC of the European Parliament and of the Council of 27 January 2003 on the restriction of the use of certain hazardous substances in electrical and electronic equipment, Official Journal of the European Union, 13.2.2003, pp. L37/19–23]. Electrochemical processes are commonly used for the solder deposition, but it is difficult to adjust the composition ratio in the deposited binary and ternary metal compounds with this method. In this paper, we report the evaluation of different metallization schemes with Ni- or Cu-studs beneath the solder material. Special efforts were put on the investigation and optimization of selected unit processes and hardware setups required for the whole bump formation process, like resist patterning, electroplating, resist stripping, under bump metallization (UBM) etching and the reflow process.

Evaluation of displacement rate effect in shear test of Sn–3Ag–0.5Cu solder bump for flip chip application

An experimental investigation was combined with a non-linear finite element analysis using an elastic–viscoplastic constitutive model to study the effect of ball shear speed on the shear forces of flip chip solder bumps. A solder composition used in this study was Sn–3mass%Ag–0.5mass%Cu. A low cost bumping process has been employed using electroless Ni and immersion Au followed by solder paste stencil printing. A thin layer of intermetallic compound, (Ni 1− x Cu x ) 3Sn 4, was formed by the reaction between the solder and electroless Ni with a thickness of about 1.4 μm, while some discontinuous (Cu 1− y Ni y ) 6Sn 5 particles were also formed at the interface. The compositions of the resulting compounds were identified using energy dispersive spectrometer (EDS) and electron microprobe analysis (EPMA). Shear tests were carried out over a shear speed range from 20 to 400 μm/s at a shear ram height of 20 μm. The shear force was observed to linearly increase with shear speed and reach the maximum value at the fastest shear speed in both experimental and computational results. The optimum shear speeds for the shear test of solder bumped flip chip were recommended to be not exceeding 200 μm/s. The failure mechanisms were discussed in terms of von Mises stresses and plastic strain energy density distributions.

Anisotropic conductive adhesives with enhanced thermal conductivity for flip chip applications

In this paper, we present the development work of anisotropic conductive adhesives (ACA) with particular emphasis on the enhanced thermal conductivity of ACAs for flip chip applications. To ensure good thermal conductivity, we incorporated silicon carbide (SiC) fillers in the ACA formulation. For the characterization of modified ACAs with enhanced thermal conductivity by loading different content of SiC fillers, measurements of thermal conductivity and thermomechanical analyses such as dynamic scanning calorimetry (DSC), dynamic mechanical analysis (DMA), and thermomechanical analysis (TMA) were performed. The current carrying capability and reliability of flip chip joints using conventional ACA and novel ACA with enhanced thermal conductivity were compared to investigate the role of ACA as a new thermal transfer medium in the flip chip assembly. We developed a new ACA with high thermal conductivity which can improve reliability under high current stressing. This paper is part of a broad study of thermally conductive ACAs for flip chip packaging and other electronic packaging technologies.

Recent advances on anisotropic conductive adhesives (ACAs) for flat panel displays and semiconductor packaging applications

Anisotropic conductive films (ACFs) consist of conducting particles and adhesive polymer resins in a film type and have been widely used for the flat panel display module to be high-resolution, light weight, thin profile and low power consumption in forms of out lead bonding (OLB), flex to printed circuit board bonding (PCB), chip-on-glass (COG) and chip-on-film (COF) in last decades. As the interconnection pitch between driver IC and flex is decreasing, ACF materials have been evolved to meet the fine pitch capability, low-temperature curing and strong adhesion requirements. Multi-layered ACF structures such as double and triple-layered ACFs were developed for the same reason. Flip chip technology has been well-known as one of the solutions to meet today's semiconductor packaging needs of miniaturization of package size as well as reduction in interconnection distance, resulting in high electrical performance. Especially, flip chip assembly using anisotropic conductive adhesives (ACAs) has been gaining much attention for its simple and lead-free processing as well as cost-effective packaging method. High mechanical reliability, good electrical performance at high-frequency range and effective thermal conductivity for high current density are the required properties for the ACF material for wide use in the flip chip application. In this paper, an overview on the principles, recent development and applications of ACF materials for flat panel displays and semiconductor packaging applications, with focus on the fine pitch capability, low-temperature bonding process, electrical/mechanical/thermal performance and wafer level package using ACFs are described.

Flow time measurements for underfills in flip-chip packaging

Flow time is a key material property for underfill materials in flip-chip applications. In this paper, we will discuss how to use flow time testing for underfill flow evaluation and material screening. The flow time of several underfills was measured at elevated temperatures using test pieces made from glass microscope slides. The material properties impacting underfill flow, such as viscosity, contact angle, and surface tension, were also experimentally measured and used to calculate estimated flow times using the Washburn equation. Empirical and calculated flow times were compared. The effects of channel width and flow distance on flow time were also studied. Additionally, the effect of a tilted stage on flow time, epoxy tongue, and void formation was evaluated.

Experiment and Numerical Analysis of the Residual Stresses in Underfill Resins for Flip Chip Package Applications

Polymeric encapsulant is widely used to protect the integrated circuit chips and thus to enhance the reliability of electronic packages. Residual stresses are introduced in the plastic package when the polymer is cooled from the curing temperature to ambient, from which many reliability issues arise, including warpage of the package, premature interfacial failure, and degraded interconnections. Bimaterial strip bending experiment has been employed successfully to monitor the evolution of the residual stresses in underfrill resins for flip chip applications. A numerical analysis is developed to predict the residual stresses, which agree well with the experimental measurements. The changes of material properties, such as flexural modulus and coefficient of thermal expansion, of the resins with temperature are taken into account in the finite element analysis.

Solid state interfacial reaction and joint strength of Sn–37Pb solder with Ni–P under bump metallization in flip chip application

The interfacial microstructure of Sn–37Pb solder with immersion Au/electroless Ni–P under bump metallization (UBM) was studied using scanning electron microscopy (SEM) and transmission electron microscopy (TEM). A Ni 3Sn 4 intermetallic compound (IMC) layer was formed at the interface between the solder and Ni–P UBM upon reflow. However, after isothermal aging, AuSn 4 containing a certain amount of Ni dissolved in it, i.e. (Au,Ni)Sn 4, appeared above the Ni 3Sn 4 layer. Two distinctive layers, P-rich and Ni–Sn–P, were additionally found from the TEM observation. Analytical studies using energy dispersive spectrometer (EDS) equipped in TEM revealed that the averaged composition of the P-rich layer is more close to that of a mixture of Ni 3P and Ni, while that of the Ni–Sn–P layer is analogous to the P-rich layer but containing a small amount of Sn in it. The growth of the Ni 3Sn 4 IMC layer thickness obeyed a parabolic growth law which implies that the interfacial IMC growth is mainly controlled by volume diffusion of the elements to the reaction layer. The shear force of the joints decreased during isothermal aging at 373 K. The decrease of the shear force could be mainly due to the coarsening effect of the microstructure within the solder. The failure behavior could be well explained with the results of finite element modeling (FEM) analyses.

Characterizing metallurgical reaction of Sn–Pb solder with Ni/Cu under-bump metallization by electron microscopy

Ni/Cu under-bump metallization (UBM) for flip-chip application is widely used in electronics packaging. The intermetallic compounds (IMCs) formed at the interface between Sn–Pb solder and Ni/Cu UBM during reflowing are mainly (Ni, Cu) 3Sn 4 and (Cu, Ni) 6Sn 5. Field-emission scanning electron microscopy (FE-SEM) and transmission electron microscopy (TEM) analyses were employed to analyze the morphology and structure in intermetallic compounds. The elemental distribution near the interfacial region was evaluated by an electron probe microanalyzer (EPMA). From the morphology of IMCs observed by SEM and cross-sectional EM images of Sn–Pb solder joint, it is revealed that the growth of (Cu 1− y , Ni y ) 6Sn 5 IMC is accompanied by a decreasing thickness of (Ni 1− x , Cu x ) 3Sn 4 IMC between (Cu 1− y , Ni y ) 6Sn 5 and Ni/Cu layer. This phenomenon was further evidenced by the cross-sectional SEM images of Sn–Pb solder/Ni layer interface after multiple reflow cycles. Based on the observation and characterization by FE-SEM, TEM, and EPMA, the evolution of the phase transformation between (Cu 1− y , Ni y ) 6Sn 5 and (Ni 1− x , Cu x ) 3Sn 4 IMCs is proposed.

Effects of Silica Filler and Diluent on Material Properties and Reliability of Nonconductive Pastes (NCPs) for Flip-Chip Applications

In this paper, thermomechanical and rheological properties of nonconductive pastes (NCPs) depending on silica filler contents and diluent contents were investigated. And then, thermal cycling (T/C) reliability of flip chip assembly using selected NCPs was verified. As the silica filler content increased, thermomechanical properties of NCPs were changed. The higher the silica filler content was added, glass transition temperature (T/sub g/) and storage modulus at room temperature became higher while coefficient of thermal expansion (CTE) decreased. On the other hand, rheological properties of NCPs were significantly affected by diluent content. As the diluent content increased, viscosity of NCP decreased and thixotropic index increased. However, the addition of diluent deteriorated thermomechanical properties such as modulus, CTE, and T/sub g/. Based on these results, three candidates of NCPs with various silica filler and diluent contents were selected and used as adhesives for reliability test of flip chip assemblies. T/C reliability test was performed by measuring changes of NCP bump connection resistance. Results showed that flip chip assembly using NCP with lower CTE and higher modulus exhibited better T/C reliability behavior because of reduced shear strain in NCP adhesive layer.

Novel Reworkable Fluxing Underfill for Board-Level Assembly

Underfills are traditionally applied for flip-chip applications. Recently, there has been increasing use of underfill for board-level assembly including ball grid arrays (BGAs) and chip scale packages (CSPs) to enhance reliability in harsh environments and impact resistance to mechanical shocks. The no-flow underfill process eliminates the need for capillary flow and combines fluxing and underfilling into one process step, which simplifies the assembly of underfilled BGAs and CSPs for SMT applications. However, the lack of reworkability decreases the final yield of assembled systems. In this paper, no-flow underfill formulations are developed to provide fluxing capability, reworkability, high impact resistance, and good reliability for the board-level components. The designed underfill materials are characterized with the differential scanning calorimeter (DSC), the thermal mechanical analyzer (TMA), and the dynamic mechanical analyzer (DMA). The potential reworkability of the underfills is evaluated using the die shear test at elevated temperatures. The 3-point bending test and the DMA frequency sweep indicate that the developed materials have high fracture toughness and good damping properties. CSP components are assembled on the board using developed underfill. High interconnect yield is achieved. Reworkability of the underfills is demonstrated. The reliability of the components is evaluated in air-to-air thermal shock (AATS). The developed formulations have potentially high reliability for board-level components.

Development and reliability of non-conductive adhesive flip-chip packages

Driven by miniaturization, cost and environmental friendliness, non-conductive adhesive (NCA) is emerging as one of the potential alternatives for solder-less flip-chip interconnections. It offers inherent characteristics such as finer pitch interconnect, green process, good electrical performance, lower cost and low processing temperature compatible with organic substrates. A reliability evaluation of NCA for flip chip application was carried out to investigate the degradation of the NCA joint in environmental tests. Finite element analysis was also performed to understand the observed phenomenon. In order to obtain accurate material properties for precise finite element simulation, NCA pastes are characterized, as close as possible to reliability test condition, in terms of their thermo-mechanical, moisture diffusion, and viscoelastic properties. The results showed that failures occurring in NCA joints are caused by moisture induced hygroscopic swelling and stress relaxation. All these factors affect the degradation of the compressive force that maintains the mechanical contact in NCA flip chip. The common failure modes observed were interfacial delamination, bump/pad opening as well as cracking.

Intermetallic compound formation between Sn–3.5Ag solder and Ni-based metallization during liquid state reaction

Ni and its alloys possess a lower reaction rate with Sn than Cu and Cu alloys. Ni-based under bump metallization (UBM) therefore receives considerable attention from the microelectronic packaging industry for the popular flipchip applications. In this work, we study the interfacial reaction of electroless Ni–P (EN) alloy and Ni UBMs with Sn–3.5Ag solder. Morphology and growth kinetics of the formed Ni 3Sn 4 intermetallic compound (IMC) in both systems are investigated under different reflow durations. With the Ni–P alloy as the UBM, needle-type, boomerang-type and chunk-type IMC grains coexist at short reflow time, but only chunk-type grains remain after prolonged reflow. With pure Ni as UBM, only scallop grains with faceted surfaces are found under both short and long reflow durations. The thickness of the intermetallic compound in both UBM systems is measured under different reflow conditions, from which the growth kinetics parameters are obtained. It is found that the IMC growth rate is higher with the Ni–P UBM than with pure Ni UBM. Another difference between the two UBMs is the existence of Kirkendall voids at the interface: the voids are found inside the Ni 3P layer in the Ni–P UBM system after long-time reflow. However, such voids are not observed in the pure Ni UBM system.

Optoelectronic and microwave characteristics of silver coated indium bumps for low temperature flip-chip applications

The effect of silver coating on pure indium bumps for low temperature and high speed flip-chip applications is presented with respect to optoelectronic and microwave characteristics. The current-voltage and light power-current characteristics of flip-chip bonded vertical-cavity surface-emitting laser (VCSEL) arrays are improved by coating a thin silver layer of 0.2 µm. The flip-chip assembled coplanar waveguide packages using silver coated bumps show the insertion loss is about 3.3 dB/cm at 20 GHz and the return loss is under 13 dB.

Improvement of Adhesion and Microwave Transmission Characteristics of Indium Bump by Silver Coating for Low Temperature Flip-Chip Applications

ABSTRACTWe have conducted low-temperature flip-chip bonding for both optical interconnect and microwave applications. Flip-chip bonding of vertical-cavity surface-emitting laser (VCSEL) arrays was performed on a fused silica substrate that provides propagation paths of laser beams and also supports a polymeric waveguide. To avoid thermal damage of the polymeric waveguide during the flip-chip bonding, indium bumps were used and the bonding condition of the flip-chip was determined as a heating temperature of 150 °C and a pressure of 500 gf. Experimentally, a thin silver (Ag) layer coated on the indium bump was very effective to enhance the adhesion strength between the indium bump and the VCSEL chip pads. In addition, the microwave characteristic of coplanar waveguide (CPW) package was slightly improved by the Ag coating.

Interface reactions and phase equilibrium between Ni/Cu under-bump metallization and eutectic SnPb flip-chip solder bumps

Ni-based under-bump metallization (UBM) for flip-chip application is widely used in today's electronics packaging. In this study, electroplated Ni UBM with different thickness was used to evaluate the interfacial reaction during multiple reflow between Ni/Cu UBM and eutectic Sn–Pb solders in the 63Sn–37Pb/Ni/Cu/Ti/Si3N4/Si multilayer structure. During the first cycle of reflow, Cu atoms diffused through electroplated Ni and formed the intermetallic compound (IMC) (Ni1−x, Cux)3Sn4. After more than three times of reflow, Cu atoms further diffused through the boundaries of (Ni1−x, Cux)3Sn4 IMC and reacted with Ni and Sn to form another IMC of (Cu1-y, Niy)6Sn5. After detailed quantitative analysis by electron probe microanalysis, the values of y were evaluated to remain around 0.4; however, the values of x varied from 0.02 to 0.35. The elemental distribution of IMC in the interface of the joint assembly could be correlated to the Ni–Cu–Sn ternary equilibrium. In addition, the mechanism of (Cu1−y, Niy)6Sn5 formation was also probed.