Flicker Noise Upconversion Research Articles

Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion

Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion

A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f 3 Noise Over Wide Tuning Range

We introduce a new mode of oscillation in an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tank: an inverse class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">23</sub> . In contrast to the conventional class-F oscillators, in which a high value of the real impedance (i.e., resistance) is presented to the third (in class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) or/and to the second (in class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">23</sub> ) oscillator harmonics via an auxiliary resonance, here low resistive impedances (resembling a non-ideal short) are presented at both the second and third harmonics. This is made possible by tight magnetic coupling in the differential and common modes, respectively, afforded by a new compact 2:3 transformer. Being largely free from the harmonics in the voltage waveform and their possible deleterious phase shift effects on the flicker noise up-conversion, the phase noise performance in the flicker and thermal regions is further improved by narrowing the conduction angle. The 2:3 step-up transformer also provides a high passive gain to help with the startup in face of low supply. The switched-capacitor banks and cross-coupled transistor pair are carefully integrated under the transformer with a special arrangement of native (high-resistivity) substrate layer to mitigate their effect on the oscillation while reducing the area by 30%. The proposed digitally controlled oscillator (DCO) is implemented in 28-nm CMOS and achieves −95 dBc/Hz and −118 dBc/Hz at 100 kHz and 1 MHz offsets, respectively, while operating at a 0.3 V supply. The measured <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1/f^{3}$ </tex-math></inline-formula> corner stays within 60 to 100 kHz over the 35% tuning range (TR) (from 2.02 to 2.87 GHz). This results in a figure-of-merit (FoM) with normalized TR (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of −196 and −199 dB at 100 kHz and 1 MHz offsets, respectively, is a record in the space of ≤0.5 V and ≤1 mW.

A Low Phase Noise and High FoM Distributed-Swing-Boosting Multi-Core Oscillator Using Harmonic-Impedance-Expanding Technique

In this article, a distributed-swing-boosting and harmonic-impedance-expanding multi-core oscillator is proposed to achieve low phase noise and high figure-of-merit (FoM), simultaneously. First, a distributed-coupling multi-core topology is introduced to reduce the chip area with no mode ambiguity. Then, the distributed-swing-boosting and harmonic-impedance-expanding structure is developed to boost the gate swing and square-like waveform of <inline-formula> <tex-math notation="LaTeX">$V_{\text {DS}}$ </tex-math></inline-formula>. The common-mode (CM) resonances around the second harmonic and the differential-mode (DM) resonances around the third harmonic are utilized to suppress the flicker noise up-conversion and achieve harmonic shaping. Meanwhile, the dual-resonance response expands the high-impedance frequency ranges around the harmonics, and thus, the effect of harmonic shaping can be obtained over a wide frequency range. Fabricated in a 40-nm CMOS process, the oscillator measured exhibits low phase noise and high FoM simultaneously with a compact chip size. The minimum phase noise is &#x2212;138.9 dBc/Hz at the 1-MHz offset, corresponding to an FoM of 195.1 dBc/Hz. The 1/<inline-formula> <tex-math notation="LaTeX">$f^{3}$ </tex-math></inline-formula> phase noise corner is 100&#x2013;130 kHz over the 26.6&#x0025; tuning range.

A Generalization of the Groszkowski’s Result in Differential Oscillator Topologies

The paper presents a generalization of the Groszkowski's result in differential oscillators, providing novel equations to describe the oscillation frequency dependence on the harmonic content. The effect of the common-mode oscillation is rigorously included. Moreover, an additional term, arising from the dependence of the transistor current on the drain voltage, which is dominant any time ohmic operation occurs, is disclosed here for the first time. This framework is applied to Van der Pol oscillators, both nMOS and CMOS, designed in a 28-nm bulk CMOS technology. The results correctly match the oscillation frequency dependence derived from detailed circuit simulations. The analysis shows that, when even harmonics are relevant, the classical Groszkowski's result is not able to account for close-in phase noise performance. The novel theoretical framework fully justifies, instead, the simulation results and sheds new light on the flicker noise up-conversion mechanisms in the considered oscillator structures.

A Distributed Stubs Technique to Mitigate Flicker Noise Upconversion in a mm-Wave Rotary Traveling-Wave Oscillator

A rotary traveling-wave oscillator (RTWO) has an ability to generate multiple phases at millimeter-wave (mmW) frequencies while achieving low phase noise (PN). Unfortunately, due to the practically unavoidable transmission line (TL) dispersion, which causes the higher-order harmonics to travel faster than the fundamental, RTWOs suffer from flicker noise upconversion. In this article, we propose a “distributed stubs” technique to mitigate this mechanism in which tuning capacitors placed on the TL stubs away from the maintaining amplifiers will slow down the travel speed of higher-order harmonics relative to the fundamental, thus lowering the phase shifts due to the TL dispersion. We further provide a comprehensive analysis of the flicker noise upconversion mechanism due to the TL dispersion. The proposed 26.2-30-GHz RTWO is implemented in 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS with eight differential phases. At 30 GHz, it achieves PN of -107.6 and -128.9 dBc/Hz at 1- and 10-MHz offsets, respectively. This translates into figures-of-merit (FoMs) of 184.2 and 185.4 dB, respectively, for a single phase. The proposed architecture consumes 20 mW from 0.8-V supply. It achieves a flicker PN corner of 180 kHz, which is an order-of-magnitude better than currently achievable by state-of-the-art mmW RTWOs.

Oscillator Flicker Phase Noise: A Tutorial

A deep understanding of how to reduce flicker phase noise (PN) in oscillators is critical in supporting ultra-low PN frequency generation for the advanced communications and other emerging high-speed applications. Unfortunately, the current literature is either full of conflicting theories and ambiguities or too complex in mathematics, hiding the physical insights. In this brief, we comprehensively review the evolution of flicker noise upconversion theories and clarify their controversial and confusing parts. Two classes of such upconversion mechanisms in voltage-biased LC-tank oscillators (nMOS-only and complementary) are specifically compared and numerically verified using a commercial simulation model of 28-nm CMOS. We identify that non-resistive terminations of both 2nd and 3rd harmonic currents contribute to oscillation waveform asymmetries that lead to the flicker noise upconversion. Further, we discuss three 1/f <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> PN reduction mechanisms: waveform shaping, narrowing of conduction angle, and gate-drain phase shift.

A 2-D Mode-Switching Quad-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting

This article proposes a quad-core millimeter-wave (mm-wave) oscillator using E-M mixed-coupling resonance boosting. The mixed-coupling resonator is introduced to generate four reconfigurable resonances. The magnetic coupling and electric coupling are achieved by the symmetrically coupled transformer and coupling capacitor, respectively. A 2-D mode switch array is introduced to couple the quad-core and achieve the quad-mode switching without degrading the performance of the selected mode. Therefore, the reduction of phase noise and the extension of tuning range are achieved simultaneously. Meanwhile, the digitally controlled tail-resistor array is used to optimize the flicker noise up-conversion in wideband. Prototyped in 40-nm CMOS, the proposed oscillator exhibits a 73.2% tuning range from 18.6 to 40.1 GHz. The best phase noise at 1-MHz offset is -108.5 dBc/Hz, corresponding to an figure-of-merit (FoM) of 184.4 dBc/Hz and FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 201.7 dBc/Hz. The variation range of FoM over the whole frequency range is 3 dB. The 1/ f <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> phase noise corner is 220-620 kHz.

Low 1/f3 Noise Corner LC-VCO Design Using Flicker Noise Filtering Technique in 22nm FD-SOI

This paper presents a K/Ka-band voltage biased differential LC-VCO in 22nm FD-SOI achieving a 1/f 3 corner below 18 kHz and a figure-of-merit (FOM) at 1 MHz offset frequency of 188~190 dBc/Hz over the tuning range. Thanks to the flicker noise filtering technique, flicker noise upconversion can be suppressed significantly without degrading the phase noise (PN) in the 1/f 2 region. The difference in connection of the switched-capacitor bank (SCB) over the VCO tuning range is taken into account in our analysis of flicker noise filtering. The VCO uses differential source degeneration with a self-coupled inductor that is used for layout compactness and common-mode (CM) resonance manipulation. To obtain a low 1/f 3 corner over the tuning range, a common centroid layout technique is used for the SCB. The post-layout simulation shows that the 1/f 3 corner is well below 50 kHz over the tuning range in different process corners. The PN@1 MHz and PN@100 kHz are -110.2 dBc/Hz and -89.9 dBc/Hz, respectively, at the center of the tuning range with a power consumption of 8.8 mW.

Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators

This brief aims to intuitively explain and numerically verify the observed phenomenon of flicker noise reduction in oscillators of reduced conduction angle (i.e., in class-C), which has been presented in literature but never properly explained. The flicker phase noise in a voltage-biased oscillator capable of operating in class-B and class-C is compared and numerically verified using a commercial simulation model of TSMC 28-nm CMOS. We illustrate how narrowing the conduction angle can suppress the $1/{f}$ noise up-conversion by decreasing $1/{f}$ noise exposure to the asymmetric rising and falling edges of oscillation waveform. The effects of implicit common-mode tank in the class-C operation is also discussed. We further clarify ambiguities among several simulation methods of impulse sensitivity function (ISF) based on periodic small-signal analysis [periodic AC or periodic transfer function (PXF)], which is a key tool in understanding the flicker noise up-conversion. A clearer ISF simulation method based on positive sidebands of PXF is proposed.

A Low-Noise Fractional-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${N}$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

In this paper, we propose a 60-GHz fractional- ${N}$ digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker ( $1/\!f^{3}$ ) and thermal ( $1/\!f^{2}$ ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with $\Sigma \Delta $ dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to $1/\!f^{3}$ PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213–277-fs rms jitter in the 57.5–67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300–400 kHz.

A Low-Voltage Low-Phase-Noise 25-GHz Two-Tank Transformer-Feedback VCO

This paper presents a low-voltage low-phase-noise LC voltage-controlled-oscillator (VCO) with a novel two-tank transformer-feedback topology. The flicker noise up-conversion is suppressed by making the drain impedance of the cross-coupled transistors to be a real number at the second harmonic of the oscillation. The loaded quality factor is boosted and the noise contribution from the transconductor of the VCO is reduced by introducing a negative source impedance. A prototype VCO based on this topology is demonstrated in a 65 nm digital CMOS process. The VCO is operated from 23.9 to 26.9 GHz at a low supply voltage of 0.6 V, while achieving an ultra-low 1/ $f^{3}$ phase noise corner from 170 to 240 kHz across the tuning range. The phase noise is −110 dBc/Hz at 1 MHz frequency offset. The power consumption is 4.8 mW. The measurement results demonstrate that the VCO achieves a state-of-the-art phase noise performance in both the 1/ $f^{2}$ region and the 1/ $f^{3}$ region.

A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path

This paper presents a millimeter-wave (mmW) frequency generation stage aimed at minimizing phase noise (PN) via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A 2nd-harmonic resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for explicit common-mode current return path. Class-F operation with 3rd-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10-GHz tank at the 30-GHz frequency generation. We further propose a comprehensive quantitative analysis method of flicker noise upconversion mechanism exploiting latest insights into the flicker noise mechanisms in nanoscale short-channel transistors, and it is numerically verified against foundry models. The proposed 27.3- to 31.2-GHz oscillator is implemented in TSMC 28-nm CMOS. It achieves PN of −106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of −184 dBc/Hz at 27.3 GHz. Its flicker phase-noise ( $1/f^{3}$ ) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.

Low &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$1/f^{3}$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Phase Noise Quadrature LC VCOs

Series-coupled quadrature LC voltage-controlled oscillators(SQVCOs) perform robustly over a wide tuning range, but have a higher $1/f^{3}$ phase noise than their single-phase counterparts. Switching transistors inject noise into the tank only once per cycle leading to an asymmetric impulse sensitivity function(ISF) and large flicker noise upconversion. Circuit topologies with additional capacitive paths from the drains of the switching transistors are proposed to make the switching transistors inject noise twice in a cycle and reduce the average ISF to nearly zero. The proposed SQVCOs have a phase noise figure of merit(FoM) close to that of a single-phase VCO for a given tank. They also eliminate mode ambiguity usually present in the coupled VCOs. The 2.4 GHz prototypes of two of the proposed SQVCOs in a 0.13 $\mu \text{m}$ CMOS process have $1/f^{3}$ phase noise corners of 400 and 150 kHz compared to 3 MHz in the conventional SQVCO. At 1 MHz/3 MHz offset, the proposed SQVCOs have measured phase noise(FoM) of −133.5/−145.1 dBc/Hz (188.2/190.2 dB) and −130/−140.2 dBc/Hz (192.5/193.2 dB) whereas the conventional SQVCO has −125.5/−137.6 dBc/Hz (180.3/183 dB). The average measured phase error over five chips is 0.9°.

A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators

In this paper, we propose a method to reduce a flicker (1/f) noise upconversion in voltage-biased RF oscillators. Excited by a harmonically rich tank current, a typical oscillation voltage waveform is observed to have asymmetric rise and fall times due to even-order current harmonics flowing into the capacitive part, as it presents the lowest impedance path. The asymmetric oscillation waveform results in an effective impulse sensitivity function of a nonzero dc value, which facilitates the 1/f noise upconversion into the oscillator’s 1/f3 phase noise. We demonstrate that if the $\omega _{0}$ tank exhibits an auxiliary resonance at 2 $\omega _{0}$ , thereby forcing this current harmonic to flow into the equivalent resistance of the 2 $\omega _{0}$ resonance, then the oscillation waveform would be symmetric and the flicker noise upconversion would be largely suppressed. The auxiliary resonance is realized at no extra silicon area in both inductor- and transformer-based tanks by exploiting different behaviors of inductors and transformers in differential- and common-mode excitations. These tanks are ultimately employed in designing modified class-D and class-F oscillators in 40 nm CMOS technology. They exhibit an average flicker noise corner of less than 100 kHz.

Design and Analysis of Chopper Stabilized Injection-Locked Oscillator Sensors Employing Near-Field Modulation

This paper presents the design and the analysis of chopper stabilization circuit techniques in oscillator-based RF sensors with injection locking for dielectric spectroscopy bio-sensing applications. As the conventional phase modulation chopping scheme inevitably up-converts the 1/f phase noise intrinsically to the oscillator, we propose a near-field modulation technique that periodically shields the sensing electrical fields from fringing into the material-under-test (MUT), to achieve the desired chopping operation while avoiding the modulation of the sensor 1/f phase noise. Detailed design considerations to remedy the residual flicker noise up-conversion are discussed. The sensor prototype, implemented in 65 nm CMOS technology and operated at 16 GHz, shows a reduction in the flicker-noise corner from 10 to 0.25 kHz with field-modulation enabled, yielding a noise floor of 1 ppm in frequency shift at 10 Hz filtering bandwidth. Thermal-cycled bovine serum albumin (BSA) solutions are measured with the proposed sensor-on-CMOS. The results prove the potential for the permittivity measurements at microwave frequencies in detecting protein conformation change.

A Low-Power Low-Phase-Noise VCO With Self-Adjusted Active Resistor

This letter presents a low-power low-phase-noise VCO with self-adjusted active resistor (SAAR). A pair of PMOS transistors is introduced between cross-coupled pairs and LC-tank, serving as the SAAR. When cross-coupled transistor resides in the saturation region, SAAR exhibits small resistance, enabling fast switching and suppressing flicker noise up-conversion to 1/f <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> phase noise. Moreover, as cross-coupled transistor enters triode region, SAAR will adjust to larger resistance and prevent the small conducting resistance of the cross-coupled transistor degrading the quality factor of LC tank. Fabricated in a 65 nm CMOS technology, the proposed VCO demonstrates a tuning range of 5.07-6.35 GHz (22.4%) with only 0.42 mW power consumption at 0.6 V supply. The phase noise in the worst case is -40.8 dBc/Hz at 1 kHz and -111 dBc/Hz at 1 MHz, respectively.

Relation Between Delay Line Phase Noise and Ring Oscillator Phase Noise

The phase noise of a ring oscillator can be obtained by multiplying its open-loop phase noise by a simple shaping function. The shaping function is computed using first principles and is applicable to both flicker-noise-induced and white-noise-induced phase noise, leading to compact equations for ring oscillators. It is also shown that flicker noise upconversion in ring oscillators is primarily a function of the total gate capacitance and inevitable regardless of the risetime and falltime symmetry. Two oscillator prototypes fabricated in 65-nm CMOS technology verify the validity of the results.

Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band

Flicker noise up-conversion in voltage-biased oscillators can be effectively suppressed by inserting resistances in series to the drain of the transconductor MOSFETs. This solution avoids the degradation of the start-up margin and the adoption of area-demanding resonant filters with proper tuning. This paper presents a detailed theoretical analysis of 1/f noise up-conversion and quantitatively addresses the impact of two major contributions, namely the Groszkowski effect and the loop delay caused by stray capacitances at the drain node of the transistors. A simple flow for the design of an oscillator with suppressed flicker noise up-conversion is presented which is based on first-order closed-form formulas. Finally , theoretical estimates are compared to experimental results on a 65-nm CMOS VCO covering the 3.0–3.6 GHz band.

Analysis and Minimization of Flicker Noise Up-Conversion in Voltage-Biased Oscillators

Traditional design of voltage-controlled oscillators (VCOs) can lead to unacceptable degradation of the 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> phase-noise component when a broad tuning range is required. In this paper, the flicker noise up-conversion mechanisms in a voltage-biased topology are deeply investigated, providing general design guidelines for its mitigation. An improved VCO architecture is then introduced, where a segmented transconductor tailors the excess gain depending on the operating range to ensure that 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> noise up-conversion remains minimal over the tuning range. The solution covers both fourth-generation and WiMAX 2.5-GHz bands and leads to a 10-dB reduction of the 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> phase noise with respect to a traditional design without impairing the 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> phase-noise performance.

Complementary BAW oscillator for ultra-low power consumption and low phase noise

A complementary cross coupled BAW parallel resonance oscillator offering ultra-low power consumption and a good phase noise performance is presented. The power consumption in this structure is 50 % less than the classical NMOS based structure without any penalty in the phase noise performance. Rather, this structure serves to reduce the noise contribution of the biasing transistors at the output leading to a marginal improvement in thermal noise performance as compared to the NMOS based structure. Furthermore, the flicker noise upconversion of this complementary structure can be minimized by proper design considerations. The power consumption in case of such a complementary structure based oscillator (designed in 180nm CMOS process) employing a 2.497 GHz BAW resonator is around 675 μW for an amplitude of 300 mV with a phase noise of −140 dBc/Hz at 1 MHz offset.