Flexible Hardware Implementation Research Articles

Lightweight and flexible hardware implementation of authenticated encryption algorithm SIMON‐Galois/Counter Mode

SummaryThis brief proposes a new lightweight authenticated encryption algorithm SIMON‐GCM for Internet of Things (IoT) security, which realizes the combination of SIMON block cipher and Galois/Counter Mode (GCM). The designed SIMON circuit supports 128/192/256‐bit key size, which improves the flexibility and enlarges the range of applications. Moreover, the scheme of 32‐cycle Galois field (GF) multiplier in GF(2128) is adopted to effectively reduce the hardware cost of the Galois Hash (GHASH) function in GCM. At the same time, a finite state machine (FSM) is used to run the SIMON and GHASH modules in parallel, thus shortening the authenticated encryption time. The whole circuit is designed and implemented in field programmable gate array (FPGA) platforms. It is measured to yield a throughput of 32.4 Gbps when consuming 331 slices in Artix‐7. Compared with the existing authenticated encryption algorithms, the proposed algorithm achieves lower resource consumption and better flexibility.

AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography

As the computation bottleneck in lattice-based cryptography (LBC), the polynomial multiplication based on number theoretic transform (NTT) has been continuously studied for flexible hardware implementations with high area-efficiency. This paper presents an area-efficient and configurable NTT-based polynomial multiplier (AC-PM) incorporating algorithmic and architectural level optimization techniques. For the core operation of polynomial multiplication, two low-complexity and fast modular multiplication algorithms are introduced with loose constraints of LBC-friendly primes. Based on the proposed algorithms, a reconfigurable processing element (RPE) is dedicatedly designed to execute all the operations in an NTT-based polynomial multiplication: NTT, inverse NTT (INTT), and coefficient-wise multiplication (CWM). The proposed AC-PM can be configured with different numbers of RPEs and supports various polynomial degrees without recompilation. Additionally, the dataflow complexity is greatly simplified. More importantly, to the best of our knowledge, the twiddle factors are reused, for the first time, to support both NTT and INTT with multiple polynomial degrees, which leads to increased flexibility of AC-PM with small overhead on hardware resource. FPGA implementation results demonstrate that the proposed AC-PM significantly outperforms the prior arts in both flexibility and area efficiency.

The Surprising Benefits of Hysteresis in Unlimited Sampling: Theory, Algorithms and Experiments

The Unlimited Sensing Framework (USF) was recently introduced to overcome the sensor saturation bottleneck in conventional digital acquisition systems. At its core, the USF converts a continuous-time high-dynamic-range (HDR) signal into folded, low-dynamic-range, modulo samples and allows the recovery of the HDR signal via algorithmic unfolding. In hardware, however, implementing ideal modulo folding requires careful calibration, analog design and high precision. At the interface of theory and practice, this paper explores a computational sampling strategy that relaxes strict hardware requirements via a novel, mathematically guaranteed reconstruction. We start with a generalized model for USF with two new parameters modeling <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">hysteresis</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">folding transients</i> in addition to the modulo threshold. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Hysteresis</i> accounts for mismatches between the reset threshold and the amplitude displacement at the folding time and the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">folding transient</i> is a continuous transition period in the implementation of a reset. Both these effects are motivated by our hardware experiments and also occur in previous, domain-specific applications. We show that hysteresis is beneficial for USF and leverage it to derive the first recovery guarantees in the context of our generalized USF model for a certain sampling rate regime. Additionally, we show how the sampling rate requirement can be greatly reduced via a direct generalization of the proposed recovery. Our theoretical work is corroborated by hardware experiments with a hysteresis enabled, modulo ADC testbed comprising off-the-shelf electronic components. Thus, by capitalizing on a collaboration between hardware and algorithms, our paper enables an end-to-end pipeline for HDR sampling allowing more flexible hardware implementations.

Flexible and high‐throughput structures of Camellia block cipher for security of the Internet of Things

The advancements in wireless communication have created exponential growth in the Internet of Things (IoT) systems. Security and privacy of the IoT systems are critical challenges in many data-sensitive applications. Herein, high-throughput and flexible hardware implementations of the Camellia block cipher for IoT applications are presented. In the proposed structures, sub-blocks of the ciphers are implemented based on optimised circuits. The proposed structures for Camellia are designed and shared for implementing the encryption process and generating some intermediate key values in the two separate times. The most complex block in these ciphers is the substitution box (S-box). The S-boxes are implemented based on area-optimised logic circuits. The Camellia S-boxes consist of a field inversion over F 2 8 and two affine transformations over F 2 . The inversion operation is implemented over the composite field F ( 2 4 ) 2 instead of an inversion over F 2 8 which is an important factor to reduce area consumption. A large number of gates, in the structure, have been implemented by 2-input NAND and 2-input NOR gates to reduce delay and area. Also, the flexible structure for Camellia that can do various configurations of this cipher to support variable key sizes 128, 192 and 256 bits was proposed. Implementation results of the proposed architectures in 180 nm CMOS technology for different key sizes are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared to the other related works.

Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher

In this study, high-throughput and flexible hardware implementations of the CLEFIA lightweight block cipher are presented. A unified processing element is designed and shared for implementing of generalised Feistel network that computes round keys and encryption process in the two separate times. The most complex blocks in the CLEFIA algorithm are substitution boxes ( and ). The S-box is implemented based on area-optimised combinational logic circuits. In the proposed S-box structure, the number of logic gates and critical path delay are reduced by using the simplification of computation terms. The S-box consists of three steps: a field inversion over and two affine transformations over . The inversion operation is implemented over the composite field instead of inversion over which is an important factor for the reduction of area consumption. In addition, we proposed a flexible structure that can perform various configurations of CLEFIA to support variable key sizes: 128, 192 and 256 bit. Implementation results of the proposed architectures in 180 nm complementary metal–oxide–semiconductor technology for different key sizes are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared with other related works.

Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography

Considering code-based cryptography, quasi-cyclic low-density parity-check (QC-LDPC) codes are foreseen as one of the few solutions to design post-quantum cryptosystems. The bit-flipping algorithm is at the core of the decoding procedure of such codes when used to design cryptosystems. An effective design must account for the computational complexity of the decoding and the code size required to ensure the security margin against attacks led by quantum computers. To this end, it is of paramount importance to deliver efficient and flexible hardware implementations to support quantum-resistant public-key cryptosystems, since available software solutions cannot cope with the required performance. This manuscript proposes an efficient and scalable architecture for the implementation of the bit-flipping procedure targeting large QC-LDPC codes for post-quantum cryptography. To demonstrate the effectiveness of our solution, we employed the nine configurations of the LEDAcrypt cryptosystem as representative use cases for QC-LDPC codes suitable for post-quantum cryptography. For each configuration, our template architecture can deliver a performance-optimized decoder implementation for all the FPGAs of the Xilinx Artix-7 mid-range family. The experimental results demonstrate that our optimized architecture allows the implementation of large QC-LDPC codes even on the smallest FPGA of the Xilinx Artix-7 family. Considering the implementation of our decoder on the Xilinx Artix-7 200 FPGA, the experimental results show an average performance speedup of 5 times across all the LEDAcrypt configurations, compared to the official optimized software implementation of the decoder that employs the Intel AVX2 extension.

High‐throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers

SummaryIn this paper, high‐throughput and flexible hardware implementations of the SIMON and SPECK lightweight block ciphers are presented. The most complex block in the SPECK algorithm is addition modulo 2n, where n is word size (half of the input data). In the proposed structure of modular adder, we used the Sklansky adder, which is an efficient parallel prefix adder with low critical path delay and suitable hardware resources. In the SIMON block cipher, to reduce critical path delay, we use a tree structure for implementation of XOR operations. In addition, we proposed flexible structures that can perform various configurations of the SIMON and SPECK ciphers to support variable key sizes (128, 144, 192, and 256 bits) and block sizes (64, 96, and 128 bits). Therefore, the flexible architectures provide versatile implementations with adaptive security level and the ability of encryption of longer messages based on variable key size and variable block size. Implementation results of the proposed structures in 180 nm CMOS technology for different key and block sizes are achieved. The results show that the proposed structures have better critical path delay compared with other's related works.

Flexible Architectures for Cryptographic Algorithms — A Systematic Literature Review

Symmetric and asymmetric cryptographic algorithms are used for a secure transmission of data over an unsecured public channel. In order to use these algorithms in real-time applications, many flexible hardware architectures have been proposed and implemented with multiple design constraints. Therefore, a systematic study is required to analyze various implementation approaches. This paper has focused on the identification and classification of recent research practices pertaining to the flexible hardware implementation of cryptographic algorithms. We have used Systematic Literature Review (SLR) process to identify 51 research articles, published during 2008–2017. The identified researches have been classified according to three design approaches: (1) crypto processor, (2) crypto coprocessor and (3) multicore crypto processor. Consequently, a comparative analysis of various cryptographic algorithms in terms of flexibility, throughput, area, power and implementation technology has been presented. A comprehensive investigation of flexible architectures for implementing cryptographic algorithms facilitates researchers and designers of the domain to select an appropriate design approach for a particular algorithm and/or application according to their needs.

Novel dynamic partial reconfiguration implementations of the support vector machine classifier on FPGA

The support vector machine (SVM) is one of the highly powerful classifiers that have been shown to be capable of dealing with high-dimensional data. However, its complexity increases requirements of computational power. Recent technologies including the postgenome data of high-dimensional nature add further complexity to the construction of SVM classifiers. In order to overcome this problem, hardware implementations of the SVM classifier have been proposed to benefit from parallelism to accelerate the SVM. On the other hand, those implementations offer limited flexibility in terms of changing parameters and require the reconfiguration of the whole device. The latter interrupts the operation of other tasks placed on the hardware device. In this work, two flexible hardware implementations of the SVM classifier are proposed, namely A1 and A2 classifiers with successful applications in a microarray dataset. In addition, two dynamically and partially reconfigurable (DPR) architectures of the SVM classifier are presented. The A1 and A2 architectures have achieved up to 61× and 49× speed-up, respectively, over the equivalent general purpose processor. Furthermore, the DPR implementations achieved at least ∼8× reduction in reconfiguration time compared to non-DPR implementation. This is a significant achievement that can be easily adapted in other application domains of a similar nature.

FPGA-Based Flexible Hardware Architecture for Image Interest Point Detection

An important challenge in computer vision is the implementation of fast and accurate feature detectors, as they are the basis for high-level image processing analysis and understanding. However, image feature detectors cannot be easily applied in embedded scenarios, mainly due to the fact that they are time consuming and require a significant amount of processing power. Although some feature detectors have been implemented in hardware, most implementations target a single detector under very specific constraints. This paper proposes a flexible hardware implementation approach for computing interest point extraction from grey-level images based on two different detectors, Harris and SUSAN, suitable for robotic applications. The design is based on parallel and configurable processing elements for window operators and a buffering strategy to support a coarse-grain pipeline scheme for operator sequencing. When targeted to a Virtex-6 FPGA, a throughput of 49.45 Mpixel/s (processing rate of 161 frames per second of VGA image resolution) is achieved at a clock frequency of 50 MHz.

Efficient smart-camera accelerator: A configurable motion estimator dedicated to video codec

Smart cameras are used in a large range of applications. Usually the smart cameras transmit the video or/and extracted information from the video scene, frequently on compressed format to fit with the application requirements. An efficient hardware accelerator that can be adapted and provide the required coding performances according to the events detected in the video, the available network bandwidth or user requirements, is therefore a key element for smart camera solutions. We propose in this paper to focus on a key part of the compression system: motion estimation. We have developed a flexible hardware implementation of the motion estimator based on FPGA component, fully compatible with H.264, which enables the integer motion search, the fractional search and variable block size to be selected and adjusted. The main contributions of this paper are the definition of an architecture allowing flexibility and some new hardware optimizations of the architecture of the motion estimation allowing the improvement of the performances (computing time or hardware resources) compared to the state of the art. The paper describes the design and proposes a comparison with state-of-art architectures. The obtained FPGA based architecture can process integer motion estimation on 720x576 video streams at 67fps using full search strategy, and sub-pel refinement up to 650KMacroblocks/s.

An efficient low-cost FPGA implementation of a configurable motion estimation for H.264 video coding

Despite the diversity of video compression standard, the motion estimation still remains a key process which is used in most of them. Moreover, the required coding performances (bit-rate, PSNR, image spatial resolution,etc.) depend obviously of the application, the environment and the network communication. The motion estimation can therefore be adapted to fit with these performances. Meanwhile, the real time encoding is required in many applications. To reach this goal, we propose in this paper a flexible hardware implementation of the motion estimator which enables the integer motion search algorithms to be modified and the fractional search as well as variable block size to be selected and adjusted. Hence, this novel architecture, especially designed for FPGA targets, proposes high-speed processing for a configuration which supports the variable size blocks and quarter-pel refinement, as described in H.264. The proposed low-cost architecture based on Virtex 6 FPGA can process integer motion estimation on 1080 HD video streams, respectively, at 13 fps using full search strategy (108k Macroblocks/s) and up to 223 fps using diamond search (1.8M Macroblocks/s). Moreover subpel refinement in quarter-pel mode is performed at 232k Macroblocks/s.

FPNA: interaction between FPGA and neural computation.

Neural networks are usually considered as naturally parallel computing models. But the number of operators and the complex connection graph of standard neural models can not be directly handled by digital hardware devices. More particularly, several works show that programmable digital hardware is a real opportunity for flexible hardware implementations of neural networks. And yet many area and topology problems arise when standard neural models are implemented onto programmable circuits such as FPGAs, so that the fast FPGA technology improvements can not be fully exploited. Therefore neural network hardware implementations need to reconcile simple hardware topologies with complex neural architectures. The theoretical and practical framework developed, allows this combination thanks to some principles of configurable hardware that are applied to neural computation: Field Programmable Neural Arrays (FPNA) lead to powerful neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme. This paper shows how FPGAs have led to the definition of the FPNA computation paradigm. Then it shows how FPNAs contribute to current and future FPGA-based neural implementations by solving the general problems that are raised by the implementation of complex neural networks onto FPGAs.

FPNA Interaction Between FPGA and Neural Computation

Neural networks are usually considered as naturally parallel computing models. But the number of operators and the complex connection graph of standard neural models can not be directly handled by digital hardware devices. More particularly, several works show that programmable digital hardware is a real opportunity for flexible hardware implementations of neural networks. And yet many area and topology problems arise when standard neural models are implemented onto programmable circuits such as FPGAs, so that the fast FPGA technology improvements can not be fully exploited. Therefore neural network hardware implementations need to reconcile simple hardware topologies with complex neural architectures. The theoretical and practical framework developed in ref. 1 allows this combination thanks to some principles of configurable hardware that are applied to neural computation: Field Programmable Neural Arrays (FPNA) lead to powerful neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme. This paper shows how FPGAs have led to the definition of the FPNA computation paradigm. Then it shows how FPNAs contribute to current and future FPGA-based neural implementations by solving the general problems that are raised by the implementation of complex neural networks onto FPGAs.

On fast running max-min filtering

The problem of fast running max/min filters for arbitrary size windows is addressed. The size of the filter window is increased to the least power of two greater than the given size and, the input sequence is expanded. The running max/min computation uses a fast algorithm for power of two window sizes. The computational complexity (comparisons per sample) of the proposed algorithm is very close to log/sub 2/ n, where n is the size of the given window. A flexible hardware implementation for n ranging between two consecutive powers of two is discussed.

A 24-b 50-ns digital image signal processor

A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0- mu m CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-speed single-board flexible hardware implementation of a wave digital filter

The hardware implementation of a sixth-order wave digital filter on a single printed-circuit board has been described in the literature. In the present paper, a greatly improved hardware design is discussed. By including more parallelism into the architecture, sampling rates of over 500 kHz can be achieved for a fifthorder filter. With the aid of a microprocessor development system, the filter can be programmed for any order up to 15. Once programmed, the filter runs independently. An example is given, which illustrates the hardware performance with various coefficient wordlengths. Attention is also paid to the question of in-band noise.