Flexible Chip Research Articles

Electrowetting-on-Dielectric Based Economical Digital Microfluidic Chip on Flexible Substrate by Inkjet Printing.

In order to get rid of the dependence on expensive photolithography technology and related facilities, an economic and simple design and fabrication technology for digital microfluidics (DMF) is proposed. The electrodes pattern was generated by inkjet printing nanosilver conductive ink on the flexible Polyethylene terephthalate (PET) substrate with a 3D circuit board printer, food wrap film was attached to the electrode array to act as the dielectric layer and Teflon® AF was sprayed to form a hydrophobic layer. The PET substrate and food wrap film are low cost and accessible to general users. The proposed flexible DMF chips can be reused for a long time by replacing the dielectric film coated with hydrophobic layer. The resolution and conductivity of silver traces and the contact angle and velocity of the droplets were evaluated to demonstrate that the proposed technology is comparable to the traditional DMF fabrication process. As far as the rapid prototyping of DMF is concerned, this technology has shown very attractive advantages in many aspects, such as fabrication cost, fabrication time, material selection and mass production capacity, without sacrificing the performance of DMF. The flexible DMF chips have successfully implemented basic droplet operations on a square and hexagon electrode array.

Directly Visualized Mechanical Strain Distribution in Package Interconnect Using Digital Image Correlation

For advanced package interconnects, analyzing strain distribution within the complex three-dimensional structure is important in order to design a mechanically reliable system. Electronic packages frequently undergo various types of deformation including tension, compression, bending, and thermal treatments. Failures under these loading modes can be prevented with accurate information of distribution and degree of the mechanical strains. This information, however, is difficult to obtain using conventional methods due to the small-sized packages with complex internal structures. It is also uncertain to rely on predictive results from analytical solutions because it is hard to theoretically calculate the complex strain mechanics, especially for the heterogeneously integrated structures. Therefore, experimental methods have been recently demanded for direct evaluation of mechanical deformation in the package interconnects.In this study, a novel method that visualizes and accurately measures the internal strain distribution in package interconnects is developed. This method is based on digital image correlation (DIC), which utilizes microscopic images of the internal structure. The DIC method is adopted by taking advantage of non-contact and full-field analysis capability. Images from both optical microscopy and scanning electron microscopy are utilized for the non-contact strain evaluation method for the micro-scale deformation analysis. In order to obtain clear image of the internal structure, mechanical polish is conducted to form cross-section. For image pattern tracking, micro/ nano sized particles are deposited onto the cross-section to serve as speckle pattern of the DIC analysis. After the specimen preparation, the digital images are obtained before and after a mechanical loading at a same position. The consecutive images are then compared to execute image tracking analysis to result in the microscopic deformation contour. The results can be fully adopted in prediction of failure site or failure modes by providing essential data such as weak spot or intensity of deformation. Using the quantitative strain information, predicting the failure cycle could be also possible based on mechanics of fatigue fracture.We demonstrate that this method is effectively utilized for various package interconnects including printed circuit boards (PCBs), flexible chip packages, and through-hole stress analysis in a 3-D stacked structure. Bending strain analysis of flexible packages and composite substrates, thermal strain analysis of the PCB interconnects are shown as applications of the thermo-mechanical reliability evaluation method. We believe that this experimental method will enable to fully understand the internal stress-strain behavior of the advanced package interconnects and flexible devices that require high mechanical reliability for commercialization.

Flexible Surface-Enhanced Raman Scattering Chip: A Universal Platform for Real-Time Interfacial Molecular Analysis with Femtomolar Sensitivity.

We propose and demonstrate a flexible surface-enhanced Raman scattering (SERS) chip as a versatile platform for femtomolar detection and real-time interfacial molecule analysis. The flexible SERS chip is composed of a flexible and transparent membrane and embedded plasmonic dimers with ultrahigh particle density and ultrasmall dimer gap. The chip enables rapid identification for residuals on solid substrates with irregular surfaces or dissolved analytes in aqueous solution. The sensitivity for liquid-state measurement is down to 0.06 molecule per dimers for 10-14 mol·L-1 Rhodamine 6G molecule without molecule enrichment. Strong signal fluctuation and blinking are observed at this concentration, indicating that the detection limit is close to the single-molecule level. Meanwhile, the homogeneous liquid environment facilities accurate SERS quantification of analytes with a wide dynamic range. The synergy of flexibility and liquid-state measurement opens up avenues for the real-time study of chemical reactions. The reduction from p-nitrothiophenol (PNTP) to p-aminothiophenol (PATP) in the absence of the chemical reducing agents is observed at liquid interfaces by in situ SERS measurements, and the plasmon-induced hot electron is demonstrated to drive the catalytic reaction. We believe this robust and feasible approach is promising in extending the SERS technique as a general method for identifying interfacial molecular traces, tracking the evolution of heterogeneous reactions, elucidating the reaction mechanisms, and evaluating the environmental effects such as pH value and salty ions in SERS.

Flexible CMOS chip converted by a novel chip transformation process

In this Letter, the authors report a flexible CMOS chip converted by a novel chip transformation process. To realise a truly flexible CMOS chip, a two-step etching process was employed in the transformation process: (i) vapour etching to remove inter-dielectric layers followed by polymer encapsulation and (ii) plasma etching to remove the substrate of the chip. The I–V results measured after the chip transformation process show a voltage variance of <0.8% compared to the rigid chip. The bending test also revealed very small changes (0.6%) under strain conditions. Their results offer a viable route to use the foundry-fabricated CMOS chip for flexible chips; thus, a high-performance flexible chip can be realised. This technology will enable us to utilise various foundry-processed chips for future flexible applications such as health and environment monitoring, advanced mobile communication systems, and wearable electronics via a simple post-transformation process.

Highly Efficient Photothermal Conversion of Ti3C2Tx/Ionic Liquid Gel Pen Ink for Smoothly Writing Ultrasensitive, Wide-Range Detecting, and Flexible Thermal Sensors.

Photothermal conversion behavior has a vital application to disease therapy, water purification, or uncontacted heaters. The fabrication of high-performance photothermal conversion materials especially for near-infrared (NIR) light and microstructures has attracted a great deal of attention. Among numerous substances, MXene as a new type of 2D material with semi-metallic and unique electromagnetic properties presents a broader absorption of light and even a typical plasmonic absorption near the NIR-I area (808 nm), which has made it suitable for photothermal conversion. Here, we propose a facile approach for preparing a Ti3C2Tx/ionic liquid ink with a high photothermal conversion efficiency. The as-prepared ink has showed good wettability of various substrates as well as the high sensitivity of 808 nm NIR light irradiation and a wide range of thermal variation. After packing the ink into a gel pen refill, the flexible thermal chips could be easily obtained just by pen writing on the soft surface with the designed size, which also have become an optimal candidate for the thermal alarm system.

PEDOT:PSS-based micromuscles and microsensors fully integrated in flexible chips

The demand for polymer-based soft micro-electro-mechanical systems (MEMS) is growing due to the substantial increase of flexible and wearable electronic devices. In this context, electronically conducting polymers (ECPs) fulfil the requirements for soft MEMS by offering the possibility of actuation and sensing, however, their miniaturization, their integration attempts and their resulting performances are still limiting their use in real applications. In this work, elaboration, integration and operation of soft and efficient microtransducers based on commercially available poly(3,4-ethyledioxythiophene):poly(styrene sulfonate) conductive ink into flexible chips is demonstrated. This original process overcomes existing hurdles to the fabrication of fully integrated ECP-based devices with gold remote contacts directly in contact with ECPs and further embedding in flexible support. These batch-fabricated chips are actuated at low voltage (±3.0 V) in open-air with individual accessible electrical connections. More importantly, the mechanical strain sensing is evidenced for the first time on such small ECP-based devices after full integration and demonstrating low impact of the microfabrication process. This work opens the way for further development of soft ECP-MEMS and integration into more complex systems with possible applications in microrobotics, microfluidics, optoelectronics, biology, medicine or space.

Flexible and tailorable quasi‐solid‐state rechargeable Ag/Zn microbatteries with high performance

AbstractThe recent boom in flexible and wearable electronics requires their power sources not only to be adequately compact but also could undergo extreme deformation without significant degradation in performance. Here, flexible and tailorable quasi‐solid‐state microsized Ag/Zn batteries (micro‐AZBs) were designed by combining mask‐assisted spray printing and electrochemical deposition strategies. The micro‐AZBs display ultrastable output voltage, excellent energy, and power densities, as well as stable cycling performance. Furthermore, the micro‐AZBs with desired shapes can be designed in series or in parallel on a flexible chip to output improved voltage or current with the internal connection. More importantly, the microelectrodes could be sprayed on various substrates. Flexible micro‐AZBs could be achieved on flexible substrates and tailorable micro‐AZBs are obtained when they are fabricated on clothes. They exhibit stable electrochemical performance even under bending or cutting states. The novel design of such quasi‐solid‐state micro‐AZBs would pave a way for the miniaturization and integration of energy storage devices.

A flexible chip with embedded intelligence

A flexible processing engine that is hardwired for machine learning can be used to create a smart electronic nose for odour classification.

Finite element analysis (FEA) modelling and experimental verification to optimise flexible electronic packaging for e-textiles

In this paper a three-dimensional model of a novel electronic package has been developed using Finite element analysis to evaluate the shear load, tensile, bending and thermal stresses. Simulations of a complete flexible flip chip electronic packaging method are performed to minimize stresses on the packaged electronic device to improve robustness and reliability. Three component under-fill adhesives (Loctite 4860, Loctite 480 and Loctite 4902) and three circuit substrate materials (Kapton, Mylar and PEEK) are compared and the optimal thickness of each is found by shear load, tensile load, bending test and thermal expansion simulations. A fixed die size of 3.5 mm × 8 mm × 0.53 mm has been simulated and evaluated experimentally under shear and bending load. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. The Kapton substrate together with the Loctite 4902 adhesive were identified as the optimum in the simulation. The simulation of under-fill adhesive and substrate thickness identified an optimum configuration of a 0.045–0.052 mm thick substrate layer and a 0.042–0.045 mm thickness of the Loctite 4902 adhesive. The bending simulation has also been used to determine the neutral axis of the encapsulated electronic package in this paper, thus identifying the optimal material and thickness for the encapsulation layer of the package.

Redesign high-performance flexible thermoelectrics: From mathematical algorithm to artificial cracks

This work presents a high-performance flexible thermoelectric device (f-TED) by rationally introducing the mathematical algorithm cyclotomic rule into flat-to-flexible inorganic/organic hybrid device design. Artificial cracks and selected substrate-cutting are integrated to realize full flexibility with 0–360° bending angle and low contact resistance. Experimental measurements and numerical simulations as well as contact resistance models indicate and verify the high energy efficiency and power output of the f-TED under various temperature differences and artificial cracks. Noticeably, 19.6 mW/cm2 power density and ∼3% power conversion efficiency are achieved at near room temperature (53 K temperature difference) for the bismuth telluride f-TED with a 360° bending angle. These results offer feasibility to use the f-TED for energy generation and thermal management of heat source/sink with different surface curvature, especially in self-powered wearable mechatronics and flexible chip cooling in the Internet of Things.

Security on Plastics: Fake or Real?

Electronic devices on plastic foil, also referred to as flexible electronics, are making their way into mainstream applications. In the near future, flexible electronic labels can be embedded in smart blisters, but also used as mainstream technology for flexible medical patches. A key technology for flexible electronics is based on thin-film transistors, which have the potential to be manufactured at low cost, making them an ideal candidate for these applications. Yet, up to now, no-one is taking digital security into account in the design of flexible electronics.In this paper, we present, to our knowledge, the first cryptographic core on plastic foil. Two main research challenges arise. The first challenge is related to the reliability of the circuit, which typically decreases when the circuit area increases. By integrating cryptographic modules, we explore the limits of the technology, since the smallest lightweight block ciphers feature a larger area than the largest digital circuit on flex foil reported up to now. The second challenge is related to key hiding. The relatively large features on the chip and the fact that electronic chips on plastics are used as bare dies, i.e. they are not packaged, make it easy to read out the value of the stored secret key. Because there is no dedicated non-volatile memory technology yet, existing methods for writing data to the flexible chip after fabrication are based on wire cutting with a laser or inkjet printing. With these techniques, however, it is extremely easy to “see” the value of the secret key under a microscope. We propose a novel solution that allows us to invisibly program the key after fabrication.

Stable, Flexible, and High-Performance SERS Chip Enabled by a Ternary Film-Packaged Plasmonic Nanoparticle Array.

The high sensitivity and long-term storage stability of a plasmonic substrate are vital for practical applications of the surface-enhanced Raman scattering (SERS) technique in real-world analysis. In this study, a rationally designed, ternary film-packaged, silver-coated gold-nanoparticle (Au@Ag NP) plasmonic array was fabricated and applied as a stable and high-performance SERS chip for highly sensitive sensing of thiabendazole (TBZ) residues in fruit juices. The ternary films played different roles in the plasmonic chip: a newborn poly(methyl methacrylate) (PMMA) film serving as a template for fixing the self-assembled closely packed monolayer Au@Ag NP array that provided an intensive hot spot, a fluorescent quantitative polymerase chain reaction adhesive film (qPCR film) acting as a carrier to retrieve the Au@Ag/PMMA film that was used to improve the robustness of the plasmonic array, and a polyethylene terephthalate (PET) film covered over the Au@Ag/PMMA/qPCR film performing as a barrier to improve the stability of the chip. The Au@Ag/PMMA/qPCR-PET film chip showed high sensitivity with an enhancement factor of 3.14 × 106, long-term storage stability without changing SERS signals for more than 2 months at room temperatures, and a low limit of detection for sensing TBZ in pear juice (21 ppb), orange juice (43 ppb), and grape juice (69 ppb). In addition, the procedure for fabricating the Au@Ag/PMMA/qPCR-PET film SERS chip was easy to handle, offering a new strategy to develop flexible and wearable sensors for on-site monitoring of chemical contaminants with a portable Raman spectrometer in the future.

A novel low cost roll-to-roll manufacturing compatible ultra-thin chip integration and direct metal interconnection process for flexible hybrid electronics

Abstract The emerging Internet-of-Everything (IoE) framework aims to revolutionise human-machine interaction where billions of sensors and actuators placed on almost every physical object will be tasked to communicate with each other. A substantial fraction of these devices will be placed on locations that would undergo repeated bending deformation (such as sensors for prosthetics, human body and robots) or on curved surfaces (like interior as well as exterior of automobiles, buildings and industrial equipment). Therefore, flexible sensors and actuators delivering high performance at low power requirements and manufactured at low cost will be the key for successful implementation of IoE. Though massive developments achieved in printed and organic electronics have enabled them to fulfil the required flexibility and low cost demands of IoE applications, printed and organic electronics often fall short of the high performance and low power requirements demonstrated by silicon ICs. Flexible chip foil packages fabricated by integrating ultra-thin bare silicon ICs fulfil the aforementioned demands posed by IoE applications and therefore, they are often considered as potential enablers of IoE. Here, we present an innovative roll-to-roll manufacturing compatible low cost approach for direct metal interconnection and integration of ultra-thin silicon ICs. The thickness of the fabricated flexible packages with the integrated and interconnected ultra-thin ICs were as thin as 100 μm. Electrical measurements conducted on the 60 fabricated samples with interconnected flexible ultra-thin ICs revealed a very promising yield of 94%.

Controllable spatial engineering of flexible all-in-one graphene-based supercapacitors with various architectures

The recent boom in portable electronic devices requires their power sources to be sufficiently compact and potentially integrated on a flexible chip with other electronic components. However, there is still a challenge to realize 3D spatial engineering of supercapacitor devices in one chip. Herein, a metal selective reduction strategy was developed to achieve the 3D spatial engineering of all-in-one supercapacitors with various architectures and interconnections in one GO film, where rGO structures serve as electrode as well as connection wire, and GO structures act as separator. In such all-carbon integrated supercapacitors, the area, shapes and connection circuits of rGO electrodes can be well controlled via tuning the reduction time, size and pattern of Zn stamp even these rGO electrodes are not in a planar surface, realizing the spatial connection of supercapacitors in series or/and parallel circuits without external connections. 3D spatial engineering of supercapacitors in the GO film can also reduce overall chip design complexity and improve the integration of several supercapacitors per unit area. More importantly, these all-in-one supercapacitors can remain their electrochemical properties under different bending states. Therefore, the universality and ease of this strategy could make it a promising route to design high performance graphene-based energy storage devices.

Theoretical and Experimental Study of Reversible and Stable Wetting States of a Hierarchically Wrinkled Surface Tuned by Mechanical Strain.

The wetting behavior of hierarchically wrinkled surfaces has attracted great interest because of its broad application in flexible electronic, microfluidic chip, and biomedicine. However, theoretical studies concerning the relationship between the apparent contact angle and mechanical strain applied on the soft and flexible surface with a hierarchically wrinkled structure are still limited. We established a theoretical framework to describe and understand how prestrain and applied dynamic strain reversibly tune the wettability of the hierarchically wrinkled surface. More specifically, a direct relationship between the mechanical strain and contact angle was built through reversible tuning of the amplitude and the wavelength of the wrinkled structures caused by mechanical strain, which allowed for more precise adjustment of surface wettability. To verify the accuracy of the theoretical relationship between the contact angle and mechanical strain, a soft surface with a hierarchically wrinkled structure was prepared by combining wrinkled microstructures and strip ones. The results showed that the experimental contact angles were in agreement with the theoretical ones within a limited error range. This will be helpful for further investigation on the wettability of hierarchically wrinkled surfaces.

Fully packaged paper heater systems with remote and selective ignition capabilities for nanoscale energetic materials

Development of low-voltage driven multifunctional thermal igniters for nanoscale energetic materials (nEMs) is important for extending the application of nEMs to various thermal engineering fields. In this study, highly flexible heater chips capable of generating a sufficient amount of heat to ignite nEMs at a low voltage are demonstrated by incorporating a patterned aluminum-doped paper (AP) with polymeric substrates. A combination of automatic paper cutting and single-step ultraviolet polymer curing techniques helps in the fabrication of various designs of flexible AP heater chips in a simple and low-cost manner. Based on the AP heater chips, three models of flexible thermal igniters are designed to develop new functions such as selective ignition and sequential ignition in a single chip and successfully operated at low voltages. Two types of compact ignition systems are fabricated by fully integrating the arrayed AP igniters, circuit modules, and portable batteries in a three-dimensional printed single package and on a flexible circuit board. The systems are successfully demonstrated to ignite nEMs wirelessly and selectively with a smartphone.

Thermal Analysis of Ultimately-Thinned-and-Transfer-Bonded CMOS on Mechanically Flexible Foils

Thinned CMOS chips transfer-bonded onto a compliant host substrate remain to date the technology of choice for applications requiring both mechanical flexibility and high frequency operation. However, the use of poorly thermally conductive host substrates raises the problem of thermal management of flexible electronics, a topic poorly addressed in literature. In this letter, we report the analysis of flexible SOI-CMOS chips ultimately-thinned-and-transfer-bonded (UTTB) onto polyimide and copper substrates. While the temperature remains limited to ~68°C on the native silicon substrate or after transfer onto a copper host substrate, infrared thermography reveals temperature peaks of up to 118°C on polyimide. The impact of self-heating in flexible SOI-CMOS is correlated with electrical performance for the three types of substrates. Beyond the property of mechanical flexibility it provides, a copper substrate is shown to slightly strengthen electrostatic integrity while maintaining a thermal landscape close to that of silicon.

Paper-Based Versatile Surface-Enhanced Raman Spectroscopy Chip with Smartphone-Based Raman Analyzer for Point-of-Care Application.

With the advanced development of miniaturized Raman spectroscopy, surface-enhanced Raman spectroscopy (SERS) has extended its applications into the field of point-of-care testing (POCT) and demonstrated its great significance by virtue of its noninvasive property and capability of fingerprint identification. In the SERS-based analysis and/or sensing system, the preparation of a low-cost, high-performance SERS substrate is critically important. In this manuscript, vacuum filtration is utilized to fabricate the silver nanoparticles (AgNPs)-embedded nylon filter membrane (ANFM) as flexible paper-based SERS chips. By characterizing the typical analytes with a miniaturized smartphone-based Raman analyzer, the proposed SERS chips have successfully demonstrated good sensitivity, repeatability, and stability. The lowest concentration as detected can approach 1 pmol for rhodamine 6G (RH6G) and 10 pmol for both crystal violet (CV) and malachite green (MG), respectively. With the help of the microporous structure of the membrane, the ANFM-based SERS chips can implement the separation of small molecules from a complex mixture and can achieve "purified" SERS signals of targeted molecules. Besides, with the function of antifriction resistance and flexibility, the ANFM can serve as SERS papers to preconcentrate the contaminates by multiple swapping and further enhance the SERS signals for point-of-care analysis. Therefore, we demonstrate multifunctions of the flexible ANFM-based SERS chips, which provide a promising solution for the POCT analysis with the SERS technique on account of their flexibility and low fabrication cost.

Wafer-scale fabrication of microelectrode arrays on optically transparent polymer foils for the integration of flexible nanoscale devices

The integration of high-performance polymer substrates with added functionalities such as optical transparency and compatibility with micro-/nanolithography processes underpins future developments in flexible electronics and offers a myriad of applications such as displays, sensors, energy conversion etc. Recently, polyimide substrates such as Kapton® have emerged as an ideal choice for realizing high-performance, low-dimensional nanoelectronic platforms due to their high glass transition temperatures and chemical inertness. Flexible devices based on Kapton® polyimides, however, encounter fundamental challenges regarding the integration of optoelectronic platforms, due to their partly opaque optical characteristics. In this work, we realize a new photolithography process for wafer-scale patterning of metal microelectrode arrays (MEAs) on an optically transparent polyimide called Neopulim®. The newly established lithography protocol enabled the high throughput fabrication of flexible microchips with differently configured microelectrode arrays with uniform surface characteristics. The application potential of such optically transparent and flexible MEA chips is demonstrated by the realization of nanoscale devices based on two-dimensional graphene-based materials (GBMs) and one-dimensional zinc oxide nanowires (ZnO NWs). It is further shown that the use of Neopulim® with a high glass transition temperature (303 °C) characteristic withstands demanding device preparation steps such as use of thermal annealing and the self-assembly growth of NWs in a hot precursor solution, etc., opening a new chapter in the assembly and use of nanoscale optoelectronic platforms. The lithography procedure used to realize MEA chips and the fabrication of GBM and ZnO NW based optically transparent devices was characterized using state-of-the-art surface and electrical characterization tools. The devices were deployed as ion-sensitive field-effect transistors and as shown in this work, our devices provide an ideal platform for simultaneous optical and electrical readouts owing to high optical transparency. Scalable realization of optically transparent flexible devices at the nanoscale as presented in this work will open up new opportunities for next-generation platforms for optoelectronics, energy, sensors and biomedical applications.

Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements

In this paper, we propose a flexible and reconfigurable changeable-radix fast Fourier transform (FFT) hardware architecture. It aims to support 48 different FFT sizes and up to 4096 FFT points, which are defined in current 3GPP-LTE communication system. The built-up design structure is primarily constructed on a radix-52 basis of single-path delay feedback FFT and up to 18 various changeable radixes of FFT processing. A design technique of switchable FIFO usage approach is developed to efficiently manage FIFO arrangement for 48 FFT modes. In addition, a design technique of coarse and fine rotating is designed to effectively reduce twiddle-factor circuit area. By using TSMC 40-nm CMOS technology, an FFT ASIC implementation only has a core area occupation of 0.414 mm2 and consumes 49.8 mW in average at maximal working frequency of 526.32 MHz. This innovative design work is competitive as compared to current state-of-the-art works, especially in terms of circuit area cost and power/energy performance evaluation.