Flat-band Voltage Fluctuation Research Articles

Optimization of channel structure and bias condition for signal-to-noise ratio improvement in Si-based FET-type gas sensor with horizontal floating-gate

Sensing performances of the Si-based field-effect transistor (FET)-type gas sensor are not only affected by sensing material characteristics but also by electrical properties of a transducer. Therefore, the optimization of transducer properties, including subthreshold swing, transconductance, and low-frequency noise (LFN) characteristics, is necessary for improving the sensing performances. In this paper, NO2 gas sensing properties, LFN characteristics, and signal-to-noise ratio (SNR) of the FET-type gas sensor having different channel structures (surface and buried channel FETs) are investigated. An n-type indium-gallium-zinc oxide (IGZO) thin-film is used as a sensing layer. The LFN characteristics of both sensors are explained using a carrier number fluctuation model with correlated mobility fluctuation. The flat-band voltage fluctuation (SVfb) value of the buried channel (4.54×10−10 V2/Hz) is smaller than that of the surface channel (2.73×10−9 V2/Hz). Thus, the SNR of the sensor with a buried channel shows ~10 times larger SNR than that with a surface channel. Also, the optimal bias conditions for both sensors are suggested. The sensor with buried channel FET has a limit of detection (LOD) of 44.2 ppt to NO2 gas.

Origin of Low-Frequency Noise in Triple-Gate Junctionless n-MOSFETs

The low-frequency noise in triple-gate junctionless n-MOSFETs, with channel lengths varying from 95 to 25 nm and operating in the bulk and accumulation modes, is investigated by measurements in the frequency and time domains. The experimental drain current noise spectra present $1/{f}$ and Lorentzian-type behavior components. The noise spectra in the time domain reveal that the Lorentzian-type behavior components are due to the capture and emission processes of carriers at discrete gate insulator traps, resulting in random telegraph noise (RTN). The $1/{f}$ behavior can be described by the carrier number with the correlated mobility fluctuations model. In the below-threshold region, the conducting channel is isolated from the interface by depletion region. In the above-threshold region (bulk conduction mode), the histograms of the time-domain data show multilevel switching events, from which one or more individual traps can be distinguished. The extracted time constants of two-level RTN signals indicate the interaction of a single trap either with the channel or with both channel and gate. The relative RTN amplitude is described with the carrier number with the mobility correlated fluctuations physics-based model or with the “hole in the inversion layer” stochastic simulation-based model, enabling estimation of the flat-band voltage fluctuation caused by the RTN.

Low-Frequency Noise in Field-Effect Devices Functionalized With Dendrimer/Carbon- Nanotube Multilayers

Low-frequency noise in an electrolyte-insulator-semiconductor (EIS) structure functionalized with multilayers of polyamidoamine (PAMAM) dendrimer and single-walled carbon nanotubes (SWNT) is studied. The noise spectral density exhibits dependence with the power factor of and for the bare and functionalized EIS sensor, respectively. The gate-voltage noise spectral density is practically independent of the pH value of the solution and increases with increasing gate voltage or gate-leakage current. It has been revealed that functionalization of an EIS structure with a PAMAM/SWNTs multilayer leads to an essential reduction of the noise. To interpret the noise behavior in bare and functionalized EIS devices, a gate-current noise model for capacitive EIS structures based on an equivalent flatband-voltage fluctuation concept has been developed.

Impact of strained-channel n-MOSFETs with a SiGe virtual substrate on dielectric interface quality evaluated by low frequency noise measurements

We have investigated gate and drain current noise on strained-channel n-MOSFETs with a SiGe virtual substrate and a 12 Å thermally nitrided gate oxide using low frequency noise measurements. The power spectral densities (PSD) of the flat-band voltage fluctuations are extracted from both gate and drain current noise. We show that the same oxide trap density profile is involved in drain and gate low frequency noise. A comparison with standard n-MOSFET transistors with the same gate stack process is presented. The flat-band voltage PSD concept is also used to compare both technologies to show that bulk and dielectric quality of strained devices are not degraded with regard to standard n-MOSFETs.

Improved analysis of low frequency noise in polycrystalline silicon thin-film transistors

An improved analysis of the low frequency noise in polycrystalline silicon thin-film transistors (polysilicon TFTs) is presented. The analysis takes into account an exponential energy distribution for the density of states and the flat-band voltage fluctuations for the origin of the drain current noise. Analysis of the drain current spectral density enables the characterization of the gate oxide/polysilicon interface and the active polysilicon layer quality.

Low frequency noise in thin gate oxide MOSFETs

Low frequency, 1/ f, noise of the drain current, I D, fluctuations was measured on a series of Si MOSFETs with the gate oxide thickness, t ox, varied from 25 to 40 Å by steps of 5 Å. The salient point of this work is a demonstration that, at sufficiently low I D intensities, a mean low noise level in the MOSFETs is reduced as the gate oxide becomes thinner. This is explained assuming that the noise originates from the electron capture/release on Si/SiO 2 interface/border traps. The flat band voltage fluctuations, observable as noise, are linked then to the oxide charge fluctuations by a factor, that is inversely proportional to the gate capacitance, C ox, and thus proportional to t ox. At higher I D, the results are more complicated, as the access resistance noise is also involved. We provide an interpretation of the ensemble of the data and show that the noise analysis can furnish quantitative estimates of several device characteristics. Device degradation and its consequences for the low frequency noise at higher current levels are also discussed.

Model for drain current RTS amplitude in small-area MOS transistors

An analysis of the drain current RTS amplitude in small-area Si MOS transistors is conducted. A simple model for explaining the variations of the drain current random telegraph signals (RTS) amplitudes as a function of gate and drain voltages is also worked out. This model which is based on the concept of flatband voltage fluctuation predicts that the drain current RTS amplitude dependencies with biases can be strongly correlated to those of the transconductance-to-drain current ratio. RTS measurements performed on small-area MOS transistors partly support the validity of this model.