Flash Storage Systems Research Articles

TCSE: A Target Cell States Elimination Coding Strategy for Highly Reliable Data Storage Based on 3-D nand Flash Memory

With the wide application of NAND flash storage systems in read-intensive memory, the corresponding reliability enhancement strategies for mitigating read disturb become the focus of investigations in recent years. The prior investigations have reported the strategies based on data modulation and verified their effectiveness in mitigating retention loss. The most significant advantage of these strategies is that they can often achieve significant reliability enhancement effect with great read performance, since they are usually based on asymmetric coding. This feature means that they have the potential to be ideal reliability enhancement strategies for read-intensive memory applications. To propose a universal and highly reliable data storage strategy, this article first observes the error modes at the cell-state level under the reliability stresses of retention loss and read disturb with floating-gate (FG) 3-D triple-level (TLC) NAND flash, and then proposes a target cell states elimination (TCSE) coding strategy for further restraining bit errors. In addition, this article for the first time reports the extra bit errors generated in the decoding process of the storage strategies based on data modulation, and defines the concept of transfer factor (TF) for evaluation. By using the proposed TCSE, the experimental results show that the overall bit error rate (BER) can be reduced by 80%–90% on average, compared with the raw random data pattern.

A Low-Latency BF Decoding of LDPC Codes With Dynamic Thresholds

This letter proposes a high throughput bit-flipping (BF) algorithm for regular LDPC codes with dynamic thresholds. In the iterative decoding, the flipping threshold is dynamically updated according to the previous flipping results. Compared to the exiting hard-information-based BF algorithms, the proposed algorithm can get better decoding performance. At the same time, in order to accelerate the convergence speed, we limit the number of occurrences of high thresholds which effectively reduces the invalid decoding iterations. The proposed algorithm has better decoding performance and lower average number of iterations which is suitable for the flash storage systems with low latency and high throughput requirements.

RealWear

NAND flash memory has revolutionized how we manage data in modern digital systems, significant improvements are needed in flash-based storage systems to meet the requirements of emerging data-intensive applications. In this paper, we address the problem of NAND aging markers that represent the wearing degree of NAND cells. Since all flash operations are affected by the wearing status of NAND cells, an accurate NAND aging marker is critical to develop flash optimization techniques. From our evaluation study, we first show that the existing P/E cyclebased aging marker (PeWear) is inadequate to estimate the actual aging status of NAND blocks, thus losing opportunities for further optimizations. To overcome the limitations of PeWear, we propose a new NAND aging marker, RealWear, based on extensive characterization studies using real 3D TLC flash chips. By considering multiple variables that can affect the NAND cell wear, RealWear can accurately indicate the actual wear status of NAND blocks during run time. Using three case studies, we demonstrate that RealWear is effective in enhancing the lifetime and performance of a flash storage system. Our experimental results showed that RealWear can extend the lifetime of individual NAND blocks by 63% and can reduce the GC overhead by 21%. Furthermore, RealWear significantly mitigates read latency fluctuations, guaranteeing that the read latency can be bounded with at most 2 read retry operations.

Internal Task-Aware Command Scheduling to Improve Read Performance of Embedded Flash Storage Systems

Many NAND flash storage systems access flash memories by generating flash commands to process input/output (I/O) requests from a host system. Because the order in which flash commands are processed affects the I/O performance, command scheduling has been performed in previous studies to prioritize flash read commands for improving the read performance. However, in addition to the flash commands for accessing user data requested by the host, flash commands for internal tasks that improve the I/O performance and operation efficiency of the flash storage are issued. Particularly in embedded flash storage, the flash commands by the map cache management have a significant influence on the latency of I/O requests. The processing time of the I/O request depends on the execution time of the flash commands for mapping information and the flash commands for user data. In this paper, we propose command scheduling to improve read performance to address the occurrence of map flash commands. Priority is given to the flash read and program command from the read request, and among these commands, the flash command originating from the read request, which has a shorter processing time, is executed first. Consequently, the waiting time of the flash command is reduced, thereby improving the read latency. Experiments conducted with real workloads show that the proposed scheduling scheme reduces the average read latency by up to 51% compared with the existing scheduling scheme and demonstrates an effective performance improvement in a small map cache.

RealWear: Improving performance and lifetime of SSDs using a NAND aging marker

Although NAND flash memory has revolutionized how we manage data in modern digital systems, significant improvements are needed in flash-based storage systems to meet the requirements of emerging data-intensive applications. In this paper, we address the problem of NAND aging markers that represent the wearing degree of NAND cells. Since all flash operations are affected by the wearing status of NAND cells, an accurate NAND aging marker is critical to develop flash optimization techniques. From our evaluation study, we first show that the existing P/E cycle-based aging marker (PeWear) is inadequate to estimate the actual aging status of NAND blocks, thus losing opportunities for further optimizations. To overcome the limitations of PeWear, we propose a new NAND aging marker, RealWear, based on extensive characterization studies using real 3D TLC flash chips. By considering multiple variables that can affect the NAND cell wear, RealWear can accurately indicate the actual wear status of NAND blocks during run time. Using three case studies, we demonstrate that RealWear is effective in enhancing the lifetime and performance of a flash storage system. Our experimental results showed that RealWear can extend the lifetime of individual NAND blocks by 63% and can reduce the GC overhead by 21%. Furthermore, RealWear significantly mitigates read latency fluctuations, guaranteeing that the read latency can be bounded with at most 2 read retry operations.

Interleaved Write Scheme for Improving Sequential Write Throughput of Multi-Chip MLC NAND Flash Memory Systems

Mass-storage systems made of multi-level cell (MLC) NAND flash memory are cost effective but suffer from limited sequential write throughput. Although conventional interleaved write scheme helps, the unique characteristic of the MLC that the write time of a least significant bit (LSB) is much shorter than that of a most significant bit (MSB) leaves performance improvement headroom. This article presents an interleaved write scheme for improving the sequential write throughput of the multi-chip MLC NAND flash memory system. It leverages the longer write time of the upper pages to transmit more data by reordering the interleaved write sequence of the MLC chips. The proposed scheme can be directly implemented in the firmware of the flash memory controller without conflicting with existing flash translation layer (FTL) routines. No hardware modification is needed. The design criteria and performance improvements of general MLC NAND flash storage systems are derived for optimizing the system’s performance. Experimental results of an example single-channel 4-chip solid-state drives (SSD) system showed the sequential write throughput was improved by over 11.4%. The proposed interleaved write scheme can be applied to multi-channel storage systems to improve their sequential write throughput as well.

SmartHeating: On the Performance and Lifetime Improvement of Self-Healing SSDs

In NAND flash memory-based solid-state drives (SSDs), during the idle time between the consecutive program/erase cycles (dwell time), the dielectric damage of flash cell can be partially repaired, also known as the self-recovery effect. As the effectiveness of the self-recovery effect can be improved under high temperature, self-healing SSDs are proven feasible to extend the flash endurance significantly. However, current self-healing SSDs perform the heating operations on all the worn-out blocks without considering the data retention requirement, and measures the lifetime of flash memory based on the worst-case self-recovery effect, leading to some unnecessary heating operations and the degraded performance. We propose SmartHeating, a smart heating scheme that exploits the dwell time variation and the write hotness variation to improve the I/O performance and the lifetime of self-healing SSDs. SmartHeating tracks the dwell time of all worn-out flash blocks, predicts their self-recovery effect and reliability, and avoids performing heating operations on the worn-out flash blocks that still have strong flash reliability. In addition, by exploiting the data hotness variation, SmartHeating only heats the worn-out flash blocks that store write-cold data, while allocating write-hot data to a small portion of worn-out flash blocks with negligible refresh overhead. The experimental results show that SmartHeating reduces the number of heating operations by 12.5% on average, boosts I/O performance of flash storage systems by 21.0%, and improves the lifetime of flash memory by $1.20\times $ compared with conventional heating scheme.

$Q$ -Value Prediction for Reinforcement Learning Assisted Garbage Collection to Reduce Long Tail Latency in SSD

Garbage collection (GC), an essential operation for flash storage systems, causes long tail latency which is one of the key problems in real-time and quality-critical systems. In this article, we take advantage of reinforcement learning (RL) to reduce long tail latency. Especially, we propose two novel techniques which are: 1) $Q$ -table cache (QTC) and 2) $Q$ -value prediction. The QTC allows us to utilize appropriate and frequently recurring key states at a small memory cost. We propose a neural network called $Q$ -value prediction network (QP Net) that predicts the initial $Q$ -value of a new state in the QTC. The integrated solution of QTC and QP Net enables us to benefit from both short-term (by QTC) and long-term (by QP Net) history of system behavior to reduce the long tail latency. The experimental results demonstrate that the proposed scheme offers significant (by 25%–37%) reductions in the long tail latency of storage-intensive workloads compared with the state-of-the-art solution that adopts an RL-assisted GC scheduler.

GALRU: A Group-Aware Buffer Management Scheme for Flash Storage Systems

Many flash storage systems divide input/output (I/O) requests that require large amounts of data into sub-requests to exploit their internal parallelism. In this case, an I/O request can be completed only after all sub-requests have been completed. Thus, non-critical sub-requests that are completed quickly do not affect I/O latency. To efficiently reduce I/O latency, we propose a buffer management scheme that allocates buffer space by considering the relationship between the processing time of the sub-request and I/O latency. The proposed scheme prevents non-critical sub-requests from wasting ready-to-use buffer space by avoiding the situation in which buffer spaces that are and are not ready to use are allocated to an I/O request. To allocate the same type of buffer space to an I/O request, the proposed scheme first groups sub-requests derived from the same I/O request and then applies a policy for allocating buffer space in units of sub-request groups. When the ready-to-use buffer space is insufficient to be allocated to the sub-request group being processed at a given time, the proposed scheme does not allocate it to the sub-request group but it instead sets it aside for future I/O requests. The results of the experiments to test the proposed scheme show that it can reduce I/O latency by up to 24% compared with prevalent buffer management schemes.

Extending the lifetime of NAND flash-based SSD through compacted write

In the traditional file system, the partial page write will result in internal fragmentation and write amplification of NAND flash-based SSDs due to the page-alignment of write. Although large page sizes are useful for increasing the flash capacity and throughput, they may decrease the performance and lifetime of flash storage systems for the frequent partial page writes. After analysing the various realistic workload traces, we observe that the partial page writes are common for those heads and tails of large write requests. This observation makes compacted write possible, which compresses two partial page writes from the same large write request into one page before data are written into flash. Therefore, we propose a compacted write for page-level FTL scheme, called CWFTL, to extend the lifetime of SSD. The experiment results show that CWFTL really reduces the times of data written to flash and the average read/write response time.

DCR: Deterministic Crash Recovery for NAND Flash Storage Systems

NAND flash memory has been widely adopted as the storage medium. As power failure may occur at any time and result in data loss, crash recovery becomes vitally important in NAND flash memory storage systems. Since flash translation layers (FTLs) are used to manage flash memory, the crash recovery problem in NAND flash is how to efficiently and effectively recover FTL metadata with consistency after system crash. In this paper, we present deterministic crash recovery (DCR) that adopts a deterministic approach for crash recovery in NAND flash storage systems. The basic idea is to exploit the determinism of FTLs and reproduce events that happened between the last checkpoint and the crash point during crash recovery. Different from existing approaches that need to scan the whole flash memory chip, DCR can recover the system more efficiently by only checking a limited number of blocks based on deterministic FTL operations. We have implemented DCR in an FTL and compared it with the representative version-based and power loss recovery schemes based on an ARM-based embedded system. Experimental results show that DCR can greatly reduce the recovery time and guarantee the consistency of FTL metadata after recovery.

플래시 저장 시스템의 Full Stripe Parity를 위한 메타데이터 로그 관리 방법

플래시 저장 시스템의 Full Stripe Parity를 위한 메타데이터 로그 관리 방법

Efficient VLSI architecture for the parallel dictionary LZW data compression algorithm

The Lempel–Ziv–Welch (LZW) algorithm is an important dictionary-based data compression approach that is used in many communication and storage systems. The parallel dictionary LZW (PDLZW) algorithm speeds up the LZW encoding by using multiple dictionaries. This simplifies the parallel search in the dictionaries. However, the compression gain of the PDLZW depends on the partitioning of the address space, i.e. on the sizes of the parallel dictionaries. This work proposes an address space partitioning technique that optimises the compression rate of the PDLZW. Numerical results for address spaces with 512, 1024, and 2048 entries demonstrate that the proposed address partitioning improves the performance of the PDLZW compared with the original proposal. These address space sizes are suitable for flash storage systems. Moreover, the PDLZW has relative high memory requirements which dominate the costs of a hardware implementation. This work proposes a recursive dictionary structure and a word partitioning technique that significantly reduce the memory size of the parallel dictionaries.

HyFAT: Affordable Hybrid Fast Address Translating Device Driver for Multichannel-Based Flash Devices

Artificial intelligence (AI)-based consumer electronic (CE) devices generate massive amounts of accumulated hot data. Persisting this data into such devices’ storage media like the universal flash storage (USF) becomes an issue for flash storage system to manage hot data optimally. Consequently, efforts have been made to support many CE applications and achieve high performance and scalability storage in CE devices. However, it is challenging to find a compatible flash translation layer (FTL) for such flash devices, which can efficiently handle frequent updates imposed by the incoming hot data. Moreover, FTL should be able to handle the hot multimedia data that induces cache-miss penalties which in-turn degrades our flash storage performance. This paper proposes a hybrid flash device for fast address translations called HyFAT which is workload-compatible. HyFAT improves device performance and efficiently manages the combined QuadLevel cell (QLC) for data storage and scalability with SingleLevel cell (SLC) for fast mapping entry storage. The experimental results with realistic workloads show that our approach can improve device performance throughput by 18% on average, compared to traditional DFTL and RFTL.

An optimized active disturbance rejection approach to fan control in server

As more and more massive data storage drives are used in super high density, the power used to cool the servers has become an increasingly large component of the total power consumption. Therefore, improving server cooling efficiency has become an essential requirement in data centers. However, because the thermal dynamics of the server system has characteristics such as nonlinearity, significant inter-loop coupling, and continuously fast-changing/unknown workload disturbances, these pose huge challenges to control engineers and data center architect engineers. To address the above concerns, this paper presents an active disturbance rejection control based decoupling control algorithm for flash storage systems and CPUs in a one-unit (1U) server to simultaneously improve fan power consumption efficiency and regulate the server components’ temperature to avoid downgraded performance caused by overheating. In the study, a benchmark system is established based on the Samsung Mission Peak (MP) server where the thermal characteristics and existing solutions are both systematically evaluated. Performance of the design concept is proven in both simulation and a hardware testbed. With the proposed control solution, experiment results show that the temperature overshoot is greatly eliminated, temperatures are more tightly controlled, and the drive throttling rate are greatly decreased. Furthermore, the proposed method is shown to be able to save up to 45% energy versus a PID controller, save about 77% energy versus dynamic fan speed control method, and save about 98% energy versus native fan speed control.

Research on Experiment Technology for High Reliability Flash Storage Systems

Research on Experiment Technology for High Reliability Flash Storage Systems

Research on Experiment Technology for High Reliability Flash Storage Systems

Research on Experiment Technology for High Reliability Flash Storage Systems

FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency

Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction capability. However, to achieve better performance, LDPC code demands extra memory sensing operations and more data transfer cycles, directly leading to longer read latency. To achieve both system reliability and read efficiency, we propose the FlexLevel NAND flash storage system design in this paper. FlexLevel consists of two levels of optimization: 1) LevelAdjust and 2) AccessEval. At device level, the LevelAdjust technique is proposed to reduce BER by broadening noise margin via threshold voltage level reduction. With LevelAdjust, BER is greatly reduced and no extra sensing levels are required to protect data integrity. Hence, read performance is improved. However, while LevelAdjust can improve system reliability and read performance, it causes density loss. To balance read performance improvement and density loss, we propose the AccessEval technique at system level. AccessEval identifies data with high LDPC overhead and only applies LevelAdjust technique to these data. The experimental results show that compared with the best existing works, the proposed design can achieve up to 11% read speedup with negligible density loss.

Duplication-assisted reliability enhancement in flash storage system

Duplication-assisted reliability enhancement in flash storage system

Durable Address Translation in PCM-based Flash Storage Systems

Phase change memory (PCM) is a promising DRAM alternative because of its non-volatility, high density, low standby power and close-to-DRAM performance. These features make PCM an attractive solution to optimize the management of NAND flash memory in embedded systems. However, PCM's limited write endurance hinders its application in embedded systems. Therefore, how to manage flash memory with PCM-particularly guarantee PCM a reasonable lifetime-becomes a challenging issue. In this paper, we propose to partially replace DRAM using PCM to optimize the management of flash memory metadata for better system reliability in the presence of power failure and system crash. To prolong PCM's lifetime, we present a write-activity-aware PCM-assisted flash memory management scheme, called PCM-FTL. By differentiating sequential and random I/O behaviors, a novel two-level mapping mechanism and a customized wear-leveling scheme are developed to reduce writes to PCM and extend its lifetime. We evaluate PCM-FTL with a variety of general-purpose and mobile I/O workloads. Experimental results show that PCM-FTL can significantly reduce write activities and achieve an even distribution of writes in PCM with very low overhead.