Flash Storage Systems Research Articles

Exploring Data-Level Error Tolerance in High-Performance Solid-State Drives

Flash storage systems have exhibited great benefits over magnetic hard drives such as low input-output (I-O) latency, and high throughput. However, NAND flash based Solid-State Drives (SSDs) are inherently prone to soft errors from various sources, e.g., wear-out, program and read disturbance, and hot-electron injections. To address this issue, flash devices employ different error-correction codes (ECC) to detect and correct soft errors. Using ECC induces non-trivial overhead costs in terms of flash area, performance, and energy consumption. In this work, we evaluate the feasibility of reducing the need for strong ECC while maintaining the correct execution of the applications. Specifically, we explore data-level error tolerance in various data-centric applications, and study the system implications for designing a low-cost yet high performance flash storage system, SoftFlash. We explore three key aspects of enabling SoftFlash. First, we design an error modeling framework that can be used in runtime for monitoring and estimating the error rates of real-world flash devices. Our experiments show that the error rate of SSDs can be modeled with reasonable accuracy (13%) using parameters accessible from operating systems. Second, we carry out extensive fault-injection experiments on a wide range of applications including multimedia, scientific computation, and cloud computing to understand the requirements and characteristics of data level error tolerance. We find that the data from these applications show high error resiliency, and can produce acceptable results even with high error rates. Third, we conduct a case study to show the benefits of leveraging data-level error tolerance in flash devices. Our results show that, for many data-centric applications, the proposed SoftFlash system can achieve acceptable results (or better in certain cases), with more than a 40% performance improvement, and a third of the energy consumption.

Map cache management using dual granularity for mobile storage systems

NAND flash memories have been used in many mobile consumer devices as storage media because they are small, fast, shock-resistant, and energy-efficient. However, the flash storage systems based on these flash devices need a special software layer, the FTL, to translate logical addresses from a host system to physical addresses in NAND flash memories. Recently, the flash storage systems in mobile devices tend to employ a page-level mapping scheme as they are required to yield higher access bandwidth. Unlike common SSDs, which often keep the majority of mapping information in fast but volatile DRAM, the flash storage systems in mobile consumer devices keep only a limited subset of mapping information in a small-sized SRAM due to the restrictions in size, cost, and power consumption. For this reason, many cache management schemes proposed for SSDs may not be suitable for the flash storage systems in mobile consumer devices, though most map cache management schemes used in mobile storage are basically designed for SSD. This paper proposes a novel cache management scheme targeting mobile consumer devices. The proposed scheme uses different management granularities in allocating and evacuating cache space. Experimental results show that the proposed scheme improves map cache performance by up to 36% compared to the existing cache management techniques.

A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory

The linear scaling down of NAND flash memory is approaching its physical, electrical, and reliability limitations. To maintain the current trend of increasing bit density and reducing bit per cost, 3-D flash memory is emerging as a viable solution to fulfill the ever-increasing demands of storage capacity. In 3-D NAND flash memory, multiple layers are stacked to provide ultrahigh density storage devices. However, the physical architecture of 3-D flash memory leads to a higher probability of disturbance to adjacent physical pages and greatly increases bit error rates. This paper presents a novel physical-location-aware address mapping strategy for 3-D NAND flash memory. It permutes the physical mapping of pages and maximizes the distance between the consecutively logical pages, which can significantly reduce the disturbance to adjacent physical pages and effectively enhance the reliability. The proposed mapping strategy is applied to a representative flash storage system. Experimental results show that the proposed scheme can reduce uncorrectable page errors by 70.16% with less than 10.01% space overhead in comparison with the baseline scheme.

Virtually Separable Block Management in Flash Storage System

File systems treats Flash storage device as a traditional storage media with their logical address. However inside the Flash storage device, Flash Translation Layer (FTL) remaps logical address to physical address to hide physical limitation of Flash memory cells. Due to the address translation, intentional logical separation of file system’s layout does not directly applied to physical separation. As a result, the separate-intended file systems’ requests are mixed in physical location, which degrades write throughput, as well as Flash’s lifecycle. In this paper, we propose virtually separable Block management scheme for Flash storage system by introducing new common command interface and separable Block management in FTL. The experimental results show that the proposed scheme increases IO performance, as well as reduces flash-internal overhead.

The Design and Implementation of a High-Speed and Large-Capacity NAND Flash Storage System

Now, the quality of higher speed and larger capacity are required to the real-time storage system. This paper designs a high-speed and large-capacity storage system which uses FPGA as the master of SOPC system controlling NAND Flash chips. This system puts forward an advanced storage structure which has several NAND Flashes with multi-buses, forming a parallel pipeline design. By using the key technologies of bad block management and the ECC algorithm, which greatly avoids the influence of the invalid block to the storage system and reduces the probability of error data as well. It can not only improve the storage bandwidth and capacity substantially, but also ensure the reliability of the storage system effectively. As a result, the storage system achieves the capacity of 1.5TB and the bandwidth of 1280MBps. Also, this system uses high-speed exchange interface to link to the external network, which achieve the real-time transmission and control of data, and make the storage system standard, universal, and scalable.

On-Demand Block-Level Address Mapping in Large-Scale NAND Flash Storage Systems

The density of flash memory chips has doubled every two years in the past decade and the trend is expected to continue. The increasing capacity of NAND flash memory leads to large RAM footprint on address mapping management. This paper proposes a novel Demand-based block-level Address mapping scheme with a two-level Caching mechanism (DAC) for large-scale NAND flash storage systems. The objective is to reduce RAM footprint without excessively compromising system response time. In our technique, the block-level address mapping table is stored in fixed pages (called the translation pages) in the flash memory. Considering temporal locality that workloads exhibit, we maintain one cache in RAM to store the on-demand address mapping entries. Meanwhile, by exploring both spatial locality and access frequency of workloads with another two caches, the second-level cache is designed to cache selected translation pages. In such a way, both the most-frequently-accessed and sequentially accessed address mapping entries can be stored in the cache so the cache hit ratio can be increased and the system response time can be improved. To the best of our knowledge, this is the first work to reduce the RAM cost by employing the demand-based approach on block-level address mapping schemes. The experiments have been conducted on a real embedded platform. The experimental results show that our technique can effectively reduce the RAM footprint while maintaining similar average system response time compared with previous work.

PCRAM-assisted ECC management for enhanced data reliability in flash storage systems

Recent advance in per-cell bit density and semiconductor technology for NAND flash memories have led to significant cost reduction in non-volatile storage implementation. However, the reliability of data stored in flash memory has dramatically decreased, requiring an efficient mechanism to detect and correct bit errors during read and write operations of the data. For this purpose, when user data are often written into a flash page, an Error Correction Code (ECC) for the data is generated and stored in the spare area of the page. ECCs tend to become longer to correct more bit errors, sometimes beyond what is affordable by the spare area. In order to cope with this problem, there have been many attempts to keep ECCs in the data area, as opposed to the spare area of the flash memory. However, an additional mapping mechanism is required to locate ECCs for a given data page, and the program time and cycle are increased due to reading/storing the ECCs. In this paper, we present a novel ECC management mechanism with an assist from PCM for NAND flash storage systems. This technique uses PCM as a temporal storage to store ECCs for the data in log blocks. Later, the pages in log blocks are merged into data blocks with their ECCs kept in the PCM. Our experimental results show that the overhead from ECC management has been improved by 57% and 69% over previous attempts in BAST and FAST mapping schemes, respectively.

A flash-aware write buffer scheme to enhance the performance of superblock-based NAND flash storage systems

Most superblock-based NAND flash storage systems employ a high-speed write buffer to enhance their writing performance. The main objective is to bind data of adjacent addresses as much as possible in order to transform random data into sequential data, which then facilitates interleaving in the storage system. We have designed a new superblock-based buffer scheme for NAND flash storage systems that improves on traditional schemes. For buffer management, a series of lists need to be specified to monitor the dataflow changes in the current state of the buffered data and the NAND flash memory in order to maximize interleaving during the flush operation. Experimental results show that the proposed scheme achieves higher write speed performance in almost all configurations, with greater than 50% speedup in some cases. Our proposed flash-aware write buffer (FAWB) scheme achieves this higher write performance with a required buffer space of only 1/4th–1/8th that of other schemes, resulting in higher efficiency.

AN EFFICIENT DYNAMIC WEAR LEVELING FOR HUGE-CAPACITY FLASH STORAGE SYSTEMS WITH CACHE

Flash memory won its edge than other storage media for its advantages, such as shock resistance, low power consumption and high data transmission speed. However, new data is written out-of-place due to the characteristics of flash memory, which is diverse from traditional magnetic media. Out-of-place update results in the wear-leveling issue over flash memory for erasing blocks to reclaim invalid pages. This paper proposed a dynamic wear (DW)-leveling design without substantially increasing overhead and without modifying Flash Translation Layer (FTL) for huge-capacity flash storage systems with cache, which is based on segmentation threshold and Least Recently Used (LRU). Experimental results show that our design levels the wear of different physical blocks, reduces extra page coping and block erasing, and improves the read/write performance. Additionally, different thresholds impacting wear leveling are also discussed.

A Space Reuse Strategy for Flash Translation Layers in SLC NAND Flash Memory Storage Systems

This paper presents a space reuse strategy for flash translation layers in SLC nand flash storage systems. The basic idea is to prevent a block with many free pages from being erased in a merge operation. The preserved blocks are further reused as replacement blocks. In such a way, the space utilization and the number of erase counts of each block in a nand flash are enhanced. By employing the reuse strategy, we propose a reuse-aware flash translation layer (FTL) called reuse-aware NFTL (RNFTL) to improve the endurance and space utilization of single level cell (SLC) nand flash. We provide the performance analysis of RNFTL for frequent update operations and sequential write operations, and theoretically compare RNFTL with representative FTL schemes. We also discuss the opportunity to apply the reuse strategy in log-block-based FTL schemes. To the best of our knowledge, this is the first work to employ a space reuse strategy in FTLs to improve the space utilization and endurance of nand flash. The experiments have been conducted on a set of traces collected from real workload in daily life. The results show that the space reuse strategy can effectively improve space utilization, block lifetime and wear-leveling compared with the previous work.

A parallel flash translation layer based on page group-block hybrid-mapping method

NAND flash memory has been widely used in consumer electronic devices. However, the write and erase operations consume too much time, creating a bottleneck in system performance, which is its main drawback. Thus, improving flash memory performance is critical in enhancing user experience of consumer electronic devices. Parallel flash memory was developed to support parallel operations of flash memories. However, no currently used flash translation layers (FTLs) can fully support this ideal feature of the flash memory. An efficient and simple parallel FTL (PFTL) is presented in the present paper to maximize the I/O parallelizability of flash memories. PFTL not only addresses the requests from the upper layer file system in parallel but also reclaims the invalid blocks in parallel. A trace-driven simulation using flash storage system simulator was conducted to evaluate PFTL. The experimental results show that the time used for the read and write operations was decreased by approximately 30% under both real-world and benchmark workloads. In addition, PFTL cut the erase time by around 50%. Thus, the I/O performance of consumer electronic devices can be largely improved by using PFTL.

Enhancing Endurance of Huge-Capacity Flash Storage Systems by Selectively Replacing Data Blocks

The wear leveling is a critical factor which significantly impacts the lifetime and the performance of flash storage systems. To extend lifespan and reduce memory requirements, this paper proposed an efficient wear leveling without substantially increasing overhead and without modifying Flash Translation Layer (FTL) for huge-capacity flash storage systems, which is based on selective replacement. Experimental results show that our design levels the wear of different physical blocks with limited system overhead compared with previous algorithms.

Understanding of Rewrite Penalty for Flash Memory SSD based High Performance Computing Real Time Systems

Flash memory is continuously been dominating on hard disk drives for high computing applications by last more than two decades. Currently the high capacity MLC flash SSDs are becoming center of attraction for modern real time systems to support their increasing storage and throughput demands. However, special hardware erase-before-write characteristics impose considerable performance penalty on flash storage systems. This paper evaluates the performance of modern MLC flash SSDs in their factory-fresh and used form from well known manufacturers and compares the response time and throughput results. Experimental results based on modern benchmark are provided and discussed to give the better idea to users for suitable storage devices for their real time systems.

Ozone (O3): An Out-of-Order Flash Memory Controller Architecture

Ozone (O3) is a flash memory controller that increases the performance of a flash storage system by executing multiple flash operations out of order. In the O3 flash controller, data dependencies are the only ordering constraints on the execution of multiple flash operations. This allows O3 to exploit the multichip parallelism inherent in flash memory much more effectively than interleaving. The O3 controller also provides a prioritized handling of flash operations, equipping flash management software, such as the FTL (flash translation layer), with control knobs for managing flash operations of different time criticalities. Running a range of workloads on an FPGA implementation showed that the O3 flash controller achieves 3 to 100 percent more throughput than interleaving, with 46 to 88 percent lower response times.

플래쉬 메모리 시스템을 위한 인덱스 블록 매핑

Flash memory is non-volatile and can retain data even after system is powered off. Besides, it has many other features such as fast access speed, low power consumption, attractive shock resistance, small size, and light-weight. As its price decreases and capacity increases, the flash memory is expected to be widely used in consumer electronics, embedded systems, and mobile devices. Flash storage systems generally adopt a software layer, called FTL. In this research, we proposed a new FTL mechanism for overcoming the major drawback of conventional block mapping algorithm. In addition to the block mapping table, a index block mapping table with a small size is used to indicate sector location. The proposed indexed block mapping algorithm by adding a small size. By the simulation result, the proposed FTL provides an enhanced speed than a conventional hybrid mapping algorithm by around 45% in average, and the requirement of mapping memory is also reduced by around 12%.