Flash Memory Research Articles

Operation Scheme Optimizations to Achieve Ultrahigh Endurance (1010) in Flash Memory

Operation Scheme Optimizations to Achieve Ultrahigh Endurance (10¹⁰) in Flash Memory

An Overview of the Future of Memory Cells: Advances in SSD Technology

This paper explores the topic of Solid-State Drives (SSDs) and NAND flash memory. Information of this paper is mainly obtained from authoritative academic websites and papers related to SSDs and flash memory. Memory cells are fundamental components in various electronic devices. In the field of data storage, SSDs represent the latest generation of storage devices, offering significantly better performance and functionality than traditional hard disk drives (HDDs). NAND flash memory chips are crucial component of SSDs, particularly 3D NAND, which exhibits exceptional performance and holds significant potential for future advancements. This paper will commence by providing an overview of SSDs and HDDs, followed by a comparison between NAND flash and NOR flash, and ultimately analysing the future of NAND flash memory technology employed in SSDs, with a focus on elucidating the advantages of 2D NAND over 3D NAND. Additionally, this paper explains a few challenges that NAND technology faces currently, as well as some possible solutions.

The structure and formation of non-volatile memory cells of Superflash

Split-gate embedded Flash memory technology has been around for decades and has become the standard for a wide range of devices, such as microcontrollers and smart cards. Among the, due to a number of advantages, Silicon Storage Technology Super Flash non-volatile memory technology has become the most widespread. This article presents the results of a study of the memory cells structure, examines in detail the principle of their operation and the main technological stages of the production process of forming transistor structures.

Charge-Selective 2D Heterointerface-Driven Multifunctional Floating Gate Memory for In Situ Sensing-Memory-Computing.

Flash memory, dominating data storage due to its substantial storage density and cost efficiency, faces limitations such as slow response, high operating voltages, absence of optoelectronic response, etc., hindering the development of sensing-memory-computing capability. Here, we present an ultrathin platinum disulfide (PtS2)/hexagonal boron nitride (hBN)/multilayer graphene (MLG) van der Waals heterojunction with atomically sharp interfaces, achieving selective charge tunneling behavior and demonstrating ultrafast operations, a high on/off ratio (108), extremely low operating voltage, robust endurance (105 cycles), and retention exceeding 10 years. Additionally, we achieve highly linear synaptic potentiation and depression, and observe the reversibly gate-tunable transitions between positive and negative photoconductivity. Furthermore, we employed the VGG11 neural network for in situ trained in-sensor-memory-computing to classify the CIFAR-10 data set, pushing accuracy levels comparable to pure digital systems. This work could pave the way for seamlessly integrated sensing, memory, and computing capabilities for diverse edge computing.

Enhancing Charge Trapping Performance of Hafnia Thin Films Using Sequential Plasma Atomic Layer Deposition.

We aimed to fabricate reliable memory devices using HfO2, which is gaining attention as a charge-trapping layer material for next-generation NAND flash memory. To this end, a new atomic layer deposition process using sequential remote plasma (RP) and direct plasma (DP) was designed to create charge-trapping memory devices. Subsequently, the operational characteristics of the devices were analyzed based on the thickness ratio of thin films deposited using the sequential RP and DP processes. As the thickness of the initially RP-deposited thin film increased, the memory window and retention also increased, while the interface defect density and leakage current decreased. When the thickness of the RP-deposited thin film was 7 nm, a maximum memory window of 10.1 V was achieved at an operating voltage of ±10 V, and the interface trap density (Dit) reached a minimum value of 1.0 × 1012 eV-1cm-2. Once the RP-deposited thin film reaches a certain thickness, the ion bombardment effect from DP on the substrate is expected to decrease, improving the Si/SiO2/HfO2 interface and thereby enhancing device endurance and reliability. This study confirmed that the proposed sequential RP and DP deposition processes could resolve issues related to unstable interface layers, improve device performance, and enhance process throughput.

A Study on the Channel Holes’ Diameter Effects of High-Performance Vertical-Channel Flash Memory Cells

Abstract High-performance vertical-channel flash (HVF) memory cells were fabricated on the single crystalline Si (c-Si) sidewalls of the cylindrical deep wells in c-Si substrate. To investigate the diameter effects of the cylindrical deep wells, namely channel holes, on HVF cells, the channel holes with different diameters, ranging from 65 nm to 260 nm, were made. Memory gate stacks of SiO2/ Al2O3/HfO2/Al2O3/TiN/W were formed by ozone oxidation and then ALD with the deposition thicknesses of 1/5/7/8/2/150 nm, respectively. For the devices with their diameters equal to or greater than 150 nm, their electrical properties, such as Vt, SS, DIBL, and program/erase characteristics, are close. As expected, DIBL and SS become better as the diameter increasing due to better gate control with larger diameter. However, large changes were occurred for the devices with the diameters of 90 nm and 65 nm. A simple model based on cylinder bulk for vertical flash memory devices was presented to obtain an approximate analytical solution for depletion-width and explain our experimental data. For the devices with the diameters of 150 nm, the high On/Off current ratio of 107 and relatively large memory window of 4.5 V were achieved. However, programming/erasing efficiency were degraded with hole diameter decreasing.

Resource-optimized cnns for real-time rice disease detection with ARM cortex-M microprocessors

This study explores the application of Artificial Intelligence (AI), specifically Convolutional Neural Networks (CNNs), for detecting rice plant diseases using ARM Cortex-M microprocessors. Given the significant role of rice as a staple food, particularly in Malaysia where the rice self-sufficiency ratio dropped from 65.2% in 2021 to 62.6% in 2022, there is a pressing need for advanced disease detection methods to enhance agricultural productivity and sustainability. The research utilizes two extensive datasets for model training and validation: the first dataset includes 5932 images across four rice disease classes, and the second comprises 10,407 images across ten classes. These datasets facilitate comprehensive disease detection analysis, leveraging MobileNetV2 and FD-MobileNet models optimized for the ARM Cortex-M4 microprocessor. The performance of these models is rigorously evaluated in terms of accuracy and computational efficiency. MobileNetV2, for instance, demonstrates a high accuracy rate of 97.5%, significantly outperforming FD-MobileNet, especially in detecting complex disease patterns such as tungro with a 93% accuracy rate. Despite FD-MobileNet’s lower resource consumption, its accuracy is limited to 90% across varied testing conditions. Resource optimization strategies highlight that even slight adjustments, such as a 0.5% reduction in RAM usage and a 1.14% decrease in flash memory, can result in a notable 9% increase in validation accuracy. This underscores the critical balance between computational resource management and model performance, particularly in resource-constrained settings like those provided by microcontrollers. In summary, the deployment of CNNs on microcontrollers presents a viable solution for real-time, on-site plant disease detection, demonstrating potential improvements in detection accuracy and operational efficiency. This study advances the field of smart agriculture by integrating cutting-edge AI with practical agricultural needs, aiming to address the challenges of food security in vulnerable regions.

Comprehensive investigations on defects’ stability caused lateral charge loss in Ti-doped 3D NAND

Abstract The comprehensive investigations on defects’ stability caused lateral charge loss are investigated in Ti-doped 3D NAND. The detailed study shows Ti-doping strategy could reduce pre-existing shallow traps in pure Si3N4. The stability of TiSi and Tii defects are observed under program/erase stress, but unstable TiN defects with shallow-trap levels (0.41 eV) also occur. Based on unstable defects, the device simulations are carried out revealing its effects on lateral charge loss, which indicating that TiN defects should be reduced for reliability. Our results strongly suggest the stability of Ti-related defects could be key points for lateral charge loss.

TeraHeap: Exploiting Flash Storage for Mitigating DRAM Pressure in Managed Big Data Frameworks

Big data analytics frameworks, such as Spark and Giraph, need to process and cache massive datasets that do not always fit on the managed heap. Therefore, frameworks temporarily move long-lived objects outside the heap (off-heap) on a fast storage device. However, this practice results in (1) high serialization/deserialization (S/D) cost and (2) high memory pressure when off-heap objects are moved back for processing. In this article, we propose TeraHeap , a system that eliminates S/D overhead and expensive GC scans for a large portion of objects in analytics frameworks. TeraHeap relies on three concepts: (1) It eliminates S/D by extending the managed runtime (JVM) to use a second high-capacity heap (H2) over a fast storage device. (2) It offers a simple hint-based interface, allowing analytics frameworks to leverage object knowledge to populate H2. (3) It reduces GC cost by fencing the collector from scanning H2 objects while maintaining the illusion of a single managed heap, ensuring memory safety. We implement TeraHeap in OpenJDK8 and OpenJDK17 and evaluate it with fifteen widely used applications in two real-world big data frameworks, Spark and Giraph. We find that for the same DRAM size, TeraHeap improves performance by up to 73% and 28% compared to native Spark and Giraph. Also, it can still provide better performance by consuming up to \(4.6\times\) and \(1.2\times\) less DRAM than native Spark and Giraph, respectively. TeraHeap can also be used for in-memory frameworks and applying it to the Neo4j Graph Data Science library improves its performance by up to 26%. Finally, it outperforms Panthera, a state-of-the-art garbage collector for hybrid DRAM-NVM memories, by up to 69%.

Deep Learning Algorithms for Cryptocurrency Price Prediction: a Comparative Analysis

Over the past years, cryptocurrencies have experienced a surge in popularity within the financial markets. As of today, besides being considered for investment purposes, they also serve as a widely accepted form of currency for everyday transactions. Due to the intricate characteristics of financial markets and their dependence on various factors to determine the prices of stocks and assets, the ability to predict such price is crucial to make investment choices, especially in terms of cryptocurrencies. In this work, a comparative analysis on the suitability of Deep Learning (DL) algorithms (effective for time series forecasting) in predicting the price of three cryptocurrencies (namely: Bitcoin, BTC; Ethereum, ETH; and Ripple, XRP) is assessed in terms of both short-term and long-term prediction accuracy. The results, evaluated using Root Mean Square Error (RMSE), Mean Absolute Error (MAE), Mean Absolute Percentage Error (MAPE), and coefficient of determination (denoted as \(R^{2}\) ), reveal that: Transformer is generally more effective for short-term forecasts and also performs well for long-term predictions; Convolutional Neural Network-Recurrent Neural Network (CNN-RNN) demonstrates the lowest complexity in terms of number of Multiply and ACcumulate (MAC) operations; SimpleRNN has the fewest parameters and the smallest FLASH memory requirement. Overall, CNN-Gated Recurrent Unit (CNN-GRU) provides the best joint accuracy-complexity for predicting BTC and ETH prices, whereas CNN-RNN yields superior results for XRP price prediction.

Thermal atomic layer deposition-processed InHfZnO thin film transistors with excellent stability

In recent years, the downscaling of transistors has sparked considerable interest in the advancement of amorphous oxide semiconductors, particularly indium-hafnium-zinc oxide (IHZO) has remarkable potential in applications such as high-resolution displays and 3D NAND. For the first time, we propose the fabrication of IHZO thin film transistors (TFTs) via thermal atomic layer deposition (TH-ALD). The preparation, electrical properties, and stability of IHZO TFTs are investigated. The performance of TFT deposited at 250 °C and annealed in N2 atmosphere at 300 °C exhibits a high field-effect mobility (μ) of 22.53 cm2/Vs, a high Ion/Ioff of ∼107, a low threshold voltage (Vth) of 0.15 V, and a minimum subthreshold swing (SS) of 0.24 V/decade. Furthermore, the threshold voltage shifts (ΔVth) in TFTs annealed in N2 and O2 are 0.31 and 0.16 V, respectively. These enhancements are attributed to the defects suppression and remaining ionized oxygen vacancies result in increased electron concentration in N2-annealed films. In comparison, O2 annealing causes a reduction in field effect mobility but concurrently enhances stability due to the direct passivation of defects, which leads to fewer oxygen vacancies. Additionally, Hf content can also impact the performance of TFT devices, even a small addition of Hf also results in the effective reduction of the carrier concentration. These findings provide valuable insights into the device mechanism of IHZO TFTs, presenting a novel avenue for comprehending and augmenting their overall performance.

Paving the Way for Pass Disturb-Free Vertical NAND Storage via a Dedicated and String-Compatible Pass Gate.

In this work, we propose a dual-port cell design to address the pass disturbance in vertical NAND storage, which can pass signals through a dedicated and string-compatible pass gate. We demonstrate that (i) the pass disturb-free feature originates from weakening of the depolarization field by the pass bias at the high-VTH (HVT) state and the screening of the applied field by the channel at the low-VTH (LVT) state; (ii) combined simulations and experimental demonstrations of dual-port design verify the disturb-free operation in a NAND string, overcoming a key challenge in single-port designs; (iii) the proposed design can be incorporated into a highly scaled vertical NAND FeFET string, and the pass gate can be incorporated into the existing three-dimensional (3D) NAND with the negligible overhead of the pass gate interconnection through a global bottom pass gate contact in the substrate.

Reversing File Access Control Using Disk Forensics on Low-Level Flash Memory

In the history of access control, nearly every system designed has relied on the operating system (OS) to enforce the access control protocols. However, if the OS (and specifically root access) is compromised, there are few if any solutions that can get users back into their system efficiently. In this work, we have proposed a novel approach that allows secure and efficient rollback of file access control after an adversary compromises the OS and corrupts the access control metadata. Our key observation is that the underlying flash memory typically performs out-of-place updates. Taking advantage of this unique feature, we can extract the “stale data” specific for OS access control, by performing low-level disk forensics over the raw flash memory. This allows efficiently rolling back the OS access control to a state pre-dating the compromise. To justify the feasibility of the proposed approach, we have implemented it in a computing device using file system EXT2/EXT3 and open-sourced flash memory firmware OpenNFM. We also evaluated the potential impact of our design on the original system. Experimental results indicate that the performance of the affected drive is not significantly impacted.

Decomposition of Charge Loss Mechanisms in 3-D Nand Flash Memory: Impact of Cell Dimension via High-Temperature Long-Term Retention Characteristics

Decomposition of Charge Loss Mechanisms in 3-D Nand Flash Memory: Impact of Cell Dimension via High-Temperature Long-Term Retention Characteristics

Advanced spectroscopic methods for probing in-gap defect states in amorphous SiNx for charge trap memory applications

Silicon nitride (SiNx) serves as the charge trap layer in current 3D NAND flash memory devices. The precise formation mechanism and electronic structure of localized defect trap states in SiNx remain elusive. Here, we present a refined experimental methodology to elucidate the in-gap defect states and the band gaps in amorphous SiNx thin films. Our approach integrates high-resolution reflection electron energy loss spectroscopy (REELS) and spectroscopic ellipsometry (SE) for comprehensive analysis. By systematical analysis, we aim to provide a robust method for determining in-gap electronic states in SiNx. We investigated two different SiNx films prepared by plasma-enhanced chemical vapor deposition and sputtering. Our analysis revealed several distinct in-gap states and determined band gap energies. This approach not only provide advanced spectroscopic methods to characterize the defect electronic states in SiNx, but also applicable to other large band gap semiconductors or dielectrics to predict device-level characteristics for future devices.

Evidence of Widely Distributed Time Constants in the Vertical Charge Loss of 3-D Charge-Trap NAND Flash Memories

Evidence of Widely Distributed Time Constants in the Vertical Charge Loss of 3-D Charge-Trap NAND Flash Memories

FUZZY MODEL OF ELECTRICITY CONTROL WITH WIRELESS INFORMATION PROCESSED ON GPU

Methods of processing information transmitted through wireless networks with software development are investigated in the work. Innovative methods of data transmission such as optical technologies, quantum data transmission and wireless data transmission technologies are disclosed. It is noted that in the modern understanding, the concept of distributed computing defines the process of convergence (convergence) of distributed processing methods, such as GRID, cloud and fog computing, with the combination of virtual cluster systems (grid clusters, cloud clusters and fog clusters) into a single information communication and computing system . It is emphasized that, unlike cellular modems, ZigBee technology nodes have microcontrollers with a pre-installed operating system and flash memory, which allows solving simple computational tasks in real time before sending data. It is advisable to solve such tasks within the framework of a multi-agent approach, which will increase the efficiency of the use of sensor nodes and the entire sensor network. The advantages of the multi-agent technology of fog computing based on sensor nodes of the wireless network of the ZigBee standard are revealed. The method of multi-agent processing of sensory information and its main components are described. The architecture of the system of distributed sensor data processing is outlined, which includes 4 hardware and software levels: Terminal sensor nodes and controllers of measuring devices and automation devices that implement fuzzy calculations; Coordinators, sensor segment routers and cellular modems that collect, protect and transmit sensor data to the processing center; A data processing center that includes a cluster of servers for GRID calculations and a cloud data storage server; Client devices to access cloud storage, computing cluster servers, and distributed fog computing terminals. It is emphasized that indicators and forecast results can be stored on distributed sensor nodes or transmitted for accumulation in cloud storage for further extraction and intelligent processing in the GRID cluster of the data center.

Design of Superlattice Ferroelectric-Metal Field-effect Transistor for triple-level cell 3D NAND flash

Superlattice ferroelectric-metal field-effect transistor (SL-FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for triple-level cell (TLC) operations. The SL-FeMFET shows a novel approach for designing the gate-stack using a superlattice of ferroelectric/dielectric/ferroelectric for achieving large memory window ∼3.48 V with program/erase voltage ±7 V for 3D NAND architecture. By TCAD modeling, we demonstrate TLC operation of SL-FeMFET with improving memory window and alleviating variability caused by floating metal layer in FeMFET structure. In addition, as the vertical gate stack increases from 256-layer to 512-layer, the read-out current with worst cases in seven read operations for TLC sensing are examined using page buffer circuit for sensing operation. The simulation results suggest that SL-FeMFET based 3D NAND architecture can operate 512-layer with sufficient sense margin for TLC operation.

String-level compact modeling of erase operations in the body-floated vertical channel of 3D charge trapping flash memory

In this study, we examined the use of string-level compact modeling as an effective framework for circuit simulation focusing on erase operation in 3D charge trapping flash (CTF) memory devices. We analyzed the behaviors of the accumulated hole from p-type bulk (p-well) and the corresponding difference of channel electrostatic potential in the CTF cell string, which is attributed to the variation in hole barrier height in the channel of the ground select line (GSL) transistor during erase operation. We derived a formula for the hole current delivering positive potential from the p-well to the channel region and established a modeling procedure. Technology computer-aided design (TCAD) simulation results were used to extract model parameters and analyze channel electrostatic potential during the erase operation. Additionally, experimental data for erase speed were verified using simulation program with integrated circuit emphasis (SPICE) results. Because the erase efficiency is strongly related to hole behaviors based on the conditions of the GSL transistor, the proposed compact modeling is an effective tool for circuit designers and system architects to achieve better performance in erase execution and optimizing the design of 3D CTF memory devices.

An extension to Kendall’s Tau metric to evaluate dissimilarities between data series

Data analysis is performed to examine, interpret, and extract information from data series, and it includes applying various methods and techniques to understand patterns and compare data. An approach to compare data is to use rank metrics that help identify how distinct two data series are when compared to each other according to patterns, formats, criteria, and dimensions in both data series. Among these metrics, Kendall’s Tau metric stands out, as it is robust and inexpensive, widely used in analyzing sequences and genomes, to detect errors in flash memories, and to compare distributions and top-k ranked values. However, a challenge arises when comparing lists with different lengths or when lists do not share the same elements. This happens, for example, when lists are defined by top-k elements, commonly called k-list. In this case, there is no guarantee that two k-lists share the same set of elements. Traditional metrics like Kendall’s Tau are designed to quantify differences only between shared elements in lists. Recognizing this limitation, a possible solution is to apply the metric to the shared elements of the lists. Another solution, named the generalization of Kendall’s Tau, proposed by Fagin et al., considers all elements in two lists. However, this generalization of Kendall Tau is a semi-metric, as it does not satisfy the triangular inequality. To solve this problem, we propose the Extended Kendall Tau (EKT) metric that meets all the conditions of a metric and simultaneously considers the distinct elements of the compared lists. The proposed metric was evaluated by applying conventional Kendall’s Tau and the extended Kendall’s Tau over 40 text files divided into five different languages (eight files per language). We compared KT and EKT measures within the ”same language” and across ”other language” files for the two scenarios. The results revealed that both methods could accurately identify the differences between the groups of texts of the ”same language” and ”other language”. However, the numerical results show that EKT is able to more significantly highlight the difference between groups of texts of different languages.