Flag Register Research Articles

The Grodno Powiat Register and the Names of the Nobility from the Document of 1565

The article presents the analysis of the names of the nobility from the Grodno powiat in the Army Census of the Grand Duchy of Lithuania in 1565. The structure of the Grodno flag register is described along with the instances of the registration of the nobles with their horses and military equipment, and the cases of sending the nobles and non-nobles to the army are listed. Extralinguistic elements of names (horses and military equipment) are indicated. Examination of the onomastics of male nobles showed that they were recorded as three types of names: names without potential surnames, names with only potential surnames, and mixed names. Twelve different ways of arranging proper names were used. The analysis of the structure of the names of male nobility showed that the names, first and second patronymics, -sk- type proper names, suffix-free proper names, and one -in- suffix derived proper name, which was unusual for the sixteenth century, were used in the names. The second patronymics were usually written in the genitive case while the nominative case was rarely used. In some instances, the first patronymic was omitted and only the second patronymic in the genitive case was recorded. Common words-descriptors were rare. The descriptors of the position prevailed; one common word-descriptor denoting the age group was used. Binary names of men prevailed, although there were many ternary names, and only few instances of single and quaternary names were found. A study of the onomastics of female nobles revealed that they were recorded as two types of names: anthroponyms consisting of the proper names of family members only and mixed names. For women, seven different variations of proper names were used. The analysis of the structure of female names revealed that names, andronyms, -sk- type anthroponyms, female patronymics were used, and the male patronymic in the genitive case (proper name from the spouse’s patronymic) occurred once. Five female surnames (four of married women and one of a single girl) were identified. Common words-descriptors were not used when recording women. Binary female names prevailed, although there were several ternary and quaternary names.

Dual Processor Based Centralized Device for Spectrum Handoff in Cognitive Radio Networks

Wireless communication has been evidently proven to be the best source of communication technology. This has led to a rapid growth in this technology. This growth in the wireless communication technology has been done on the cost of the valuable resource spectrum which is depleting slowly. The time has shifted from Fixed to Dynamic allocation of spectrum. Cognitive Radio Networks (CRN) has been the emerging Dynamic scheme lately. CRNs allow the unlicensed user also termed as secondary user (SU) to utilize the licensed channel in the absence of the licensed users which are termed as primary users (PU). When a PU visits a channel that is currently being utilized by a SU, the channel needs to be vacated to switch to some other vacant channel in the spectrum. This switch of the channel is termed as spectrum handoff. It helps the system as a whole for better usage of the spectrum on the cost of the performance of the SU transmission increasing its data delivery time. This paper uses a centralized cognitive device in order to decrease the handoff latency of the SU. The centralized device used in this paper is dual processor based which helps in increasing the accuracy of the target channel selection process. The central cognitive device chooses the right channel for transmitting the data using the current channel status flag register in the memory of the device along with a probabilistic approach as presented in this paper. This novel technique improves the parameters such as accuracy, handoff latency, processor speed and processor memory.

An Engineering Design of 4-bit Special Purpose Microprogrammed Processor

This work is a complementary part for what we proposed in [1]. In this paper, an undergraduate design experience for special purpose 4-bit microprocessor using the skills learned from digital logic design and Microprocessors courses is presented. The experience started in [1] by designing the ALU using the hardware printed circuit board and we are following it by completing the design by the instruction set architecture and the microprogram code. Our microprocessor contains – in addition to the ALU- six registers: A 4-bit accumulator register, Flag register that holds only zero (Z) and carry (C) flags, Program counter register (PC), Memory address register (MAR), Instruction register (IR), and Buffer Register. All programs and data are stored in the 1k RAM.

Программная конвейеризация циклов на платформе ARM

This article describes improvements we made in the implementation of swing modulo scheduling (SMS), a well-known software pipelining technique, in the GNU Compiler Collection (GCC) for ARM platform. Prior GCC implementation required a loop being pipelined to conform to the do-loop pattern, which needs a special hardware instruction. However, such hardware instruction is absent on ARM. First we implemented a “fake” do-loop instruction in the ARM backend, which helped us to verify whether GCC SMS implementation is profitable on ARM. Then we designed and implemented support for loops which loop counter varies as an arithmetic progression. In do-loops the loop counter must be used only in control part of the loop, and we allow reading loop counter register by other loop instructions. For such loops we improved the algorithm for creating prologue and epilogue as well as implemented much more complex algorithm of verification conditions for entering performance-optimized version of the loop. Also we made necessary changes in data dependency graph to generate correct code. When dependency graph is built we create additional anti-dependencies between instructions which use flag register. The resulting performance improvement is 3-4% for selected test applications on ARM platform. For x86-64 platform, performance results are mostly neutral, with exception of 2-3% improvement on matrix multiplication tests.

A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities

This paper describes an architecture and implementation of a digital vision chip that features mixed asynchronous/synchronous processing techniques. The vision chip is based on a massively parallel cellular array of processing elements, which incorporate a photo-sensor with an ADC and digital processing circuit, consisting of 64 bits of local memory, ALU, flag register and communication units. The architecture has two modes of operation: synchronous SIMD mode for low-level image processing based on local pixel data, and continuous-time mode for global operations. Additionally, the periphery circuits enable asynchronous address extraction, fixed pattern addressing and flexible, random access data I/O. A 19 × 22 proof-of-concept array has been manufactured in 0.35 μm CMOS technology. The chip delivers 15.6 GOPS for binary and 1 GOPS for grayscale operations dissipating 26.4 mW, while operating at 2.5 V and 75 MHz clock. Experimental measurements indicate that the presented concept favorably compares with other digital and analog vision chips. The results of low- and medium-level image processing on the chip are presented.