Fixed-point Number System Research Articles

Digital Image Watermarking Processor Based on Deep Learning

Much research and development have been made to implement deep neural networks for various purposes with hardware. We implement the deep learning algorithm with a dedicated processor. Watermarking technology for ultra-high resolution digital images and videos needs to be implemented in hardware for real-time or high-speed operation. We propose an optimization methodology to implement a deep learning-based watermarking algorithm in hardware. The proposed optimization methodology includes algorithm and memory optimization. Next, we analyze a fixed-point number system suitable for implementing neural networks as hardware for watermarking. Using these, a hardware structure of a dedicated processor for watermarking based on deep learning technology is proposed and implemented as an application-specific integrated circuit (ASIC).

Open Source Synthesis and Verification Tool for Fixed-to-Floating and Floating-to-Fixed Points Conversions

An open source high level synthesis fixed-to-floating and floating-to-fixed conversion tool is presented for embedded design, communication systems, and signal processing applications. Many systems use a fixed point number system. Fixed point numbers often need to be converted to floating point numbers for higher accuracy, dynamic range, fixed-length transmission limitations or end user requirements. A similar conversion system is needed to convert floating point numbers to fixed point numbers due to the advantages that fixed point numbers offer when compared with floating point number systems, such as compact hardware, reduced verification time and design effort. The latest embedded and SoC designs use both number systems together to improve accuracy or reduce required hardware in the same design. The proposed open source design and verification tool converts fixed point numbers to floating point numbers, and floating point numbers to fixed point numbers using the IEEE-754 floating point number standard. This open source design tool generates HDL code and its test bench that can be implemented in FPGA and VLSI systems. The design can be compiled and simulated using open source Iverilog/GTKWave and verified using Octave. A high level synthesis tool and GUI are designed using C#. The proposed design tool can increase productivity by reducing the design and verification time, as well as reduce the development cost due to the open source nature of the design tool. The proposed design tool can be used as a standalone block generator or implemented into current designs to improve range, accuracy, and reduce the development cost. The generated design has been implemented on Xilinx FPGAs.

Options for Denormal Representation in Logarithmic Arithmetic

Economical hardware often uses a FiXed-point Number System (FXNS), whose constant absolute precision is acceptable for many signal-processing algorithms. The almost-constant relative precision of the more expensive Floating-Point (FP) number system simplifies design, for example, by eliminating worries about FXNS overflow because the range of FP is much larger than FXNS for the same wordsize; however, primitive FP introduces another problem: underflow. The Signed Logarithmic Number System (SLNS) offers similar range and precision as FP with much better performance (in terms of power, speed and area) for multiplication, division, powers and roots. This paper proposes three variations of a new number system, respectively called the Denormal LNS (DLNS), Denormal Mitchell LNS (DMLNS) and Denormal Offset Mitchell LNS (DOMLNS), which are all hybrids of the properties of FXNS and SLNS. The inspiration for D(OM)LNS comes from the denormal (aka subnormal) numbers found in IEEE-754 (that provide better, gradual underflow) and the μ-law often used for speech encoding; the novel DLNS circuit here allows arithmetic to be performed directly on such encoded data. The proposed approach allows customizing the range in which gradual underflow occurs. Our first DLNS implementation leverages existing SLNS basic blocks. Synthesis shows the novel circuit primarily consists of traditional SLNS addition and subtraction tables, with additional datapaths that allow the novel arithmetic unit to act on conventional SLNS as well as DLNS and mixed data, for a worst-case area overhead of 26 %. Unlike SLNS, this DLNS implementation is still costly for general (non-constant) multiplication, division and roots. To overcome this difficulty, this paper proposes the other variations called Denormal Mitchell LNS (DMLNS) and Denormal Offset Mitchell LNS (DOMLNS), in which the well-known Mitchell’s method makes the cost of general multiplication, division and roots closer to that of SLNS. Taylor-series computations suggest subnormal values in DMLNS and DOMLNS also behave similarly to those in the IEEE-754 FP standard. Synthesis shows that DMLNS and DOMLNS respectively have average area overheads of 25 % and 17 % compared to an equivalent SLNS 5-operation unit.

Improved narrowband low-pass IIR filters in fixed-point systems [DSP Tips & Tricks

Due to their resistance to quantized-coefficient errors, traditional second-order infinite impulse response (IIR) filters are the fundamental building blocks in computationally efficient high-order IIR digital filter implementations. However, when used in fixed-point number systems, the inherent properties of quantized-coefficient second-order IIR filters do not readily permit their use in narrowband low-pass filtering applications. Narrowband low- pass IIR filters have traditionally had a bad reputation; for example, MATLAB's Signal Processing Toolbox documentation warns: "All classical IIR low-pass filters are ill conditioned for extremely low cutoff frequencies." This article presents a neat trick that can be used to overcome the shortcomings of narrowband second-order low- pass IIR filters, with no increase in filter coefficient bit widths and no increase in the number of filter multiplies per output sample.

Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems

A unified computation method of vector and elementary functions is proposed for handheld 3D graphics systems. It unifies vector operations like vector multiply, multiply-and-add, divide, divide-by-square-root, and dot product and elementary functions like trigonometric, inverse trigonometric, hyperbolic, inverse hyperbolic, power (xy with two variables), and logarithm to an arbitrary base into a single four-way arithmetic platform. A number system called the fixed-point hybrid number system (FXP-HNS), which combines the fixed-point number system (FXP) and the logarithmic number system (LNS), is proposed for the power and area-efficient unification. Power and area-efficient logarithmic and antilogarithmic conversion schemes are also proposed for the data conversions between fixed-point and logarithmic numbers in the FXP-HNS and achieve 0.41 percent and 0.08 percent maximum conversion errors, respectively. The unified arithmetic unit based on the proposed schemes is presented with less than 6.3 percent operation error. Its fully pipelined architecture achieves single-cycle throughput with maximum four-cycle latency for all of the supported operations. Comparison results show that the proposed arithmetic unit achieves 30 percent power and 10.9 percent area reductions and runs two times faster than the previous approach.

The Negative Two’s Complement Number System

The two's complement fractional fixed-point number system is widely used to implement digital signal processing on VLSI chips. It has a range of values from ?1 to one least significant bit below +1. Either the multiplication of ?1 ? ?1 or taking the absolute value of ?1 produces a result (+1) that cannot be represented. A new system, the negative two's complement number system, is described here that has a range of one least significant bit above ?1 to +1 which eliminates the problem. This paper presents the new number system and describes algorithms for the basic arithmetic operations.

Formalization of Fixed-Point Arithmetic in HOL

This paper addresses the formalization in higher order logic of fixed-point arithmetic. We encoded the fixed-point number system and specified the different quantization modes in fixed-point arithmetic such as the directed and even quantization modes. We also considered the formalization of exceptions detection and their handling like overflow and invalid operation. An error analysis is then performed to check the correctness of the quantized result after carrying out basic arithmetic operations, such as addition, subtraction, multiplication and division against their mathematical counterparts. Finally, we showed by an example how this formalization can be used to enable the verification of the transition from floating-point to fixed-point algorithmic level in the signal processing design flow.

Fast Fourier Transforms Using the Complex Logarithmic Number System

The complex-logarithmic number system (CLNS), which represents each complex point in log/polar coordinates, may be practical to implement the Fast Fourier Transform (FFT). The roots of unity needed by the FFT have exact representations in CLNS and do not require a ROM. We present an error analysis and simulation results for a radix-two FFT that compares a rectangular fixed-point representation of complex numbers to CLNS. We observe that CLNS saves 9–12 bits in word-size for 256–1024 point FFTs compared to the fixed-point number system while producing comparable accuracy. The consequence of the word-size advantage is that the number of full adders required for CLNS is significantly smaller than for an equivalent fixed-point implementation. The major cost of CLNS is the memory, which unlike conventional LNS, is addressed by both real and imaginary parts. Table-reduction techniques can mitigate this. The simplicity of the CLNS approach requires significantly fewer full adders, which pays for some or all of the extra memory. In applications needing the magnitude of the complex parts, such as a power spectrum, the CLNS approach can actually require less memory than the conventional approach.

High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture

The accuracy and speed characteristics of implementations of several line integration models required for Radon (1917) transform (used for computed tomography image reconstruction) and backprojection computations are described and compared. The fixed-point number system used is evaluated by error comparisons to identical floating-point calculations. An expandable multiprocessor architecture for high-speed computation that has been realized as a prototype using commercially available digital signal processor (DSP) chips as the basic processing elements is described. The simulated performances of two popular DSP chips for this application are discussed and compared. Performance characteristics of the complete prototype hardware system are presented. The computational speed of a four-chip system is measured to be more than 190 times better than that of a Sun 3/160 with a math coprocessor. The architecture and prototype organization are not dependent on the DSP chip chosen, and substitution of the most up-to-date DSP chips can yield even better speed performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Accumulation of coefficient roundoff error in fast Fourier transforms implemented with logarithmic number system

When a fast Fourier transform (FFT) is implemented on a digital computer or with special-purpose hardware, quantization errors will arise due to finite word lengths in the digital system. This correspondence presents an analysis of error accumulation due to coefficient rounding in the FFT implemented with a logarithmic number system. The theoretical result of the coefficient roundoff error analysis is verified by computer simulations. The results indicate that the FFT implemented with the logarithmic number system provides better signal-to-noise performance than that implemented with a fixed-point or floating-point number system.