Fixed-point Number Format Research Articles

FPGA implementation of bearing tracking using passive array for underwater acoustics

Within the scope of this study, a Field Programmable Gate Array (FPGA) based system which calculates bearing angles by analyzing the signals emitted by vessels in underwater environment is proposed. An array consisting of 3 non-directional hydrophones were designed and used in tests. Minimum Variance Distortionless Response (MVDR) algorithm was used in the bearing calculations according to the reference hydrophone. In marine tests, hydrophone array was integrated into the buoy, and then tested. The angle between the reference hydrophone and the magnetic north is calculated in order to correct the errors caused by the immobility of the buoy and underwater array. In the developed system, all operations were carried out on Artix 7 FPGA. Fixed point number format is used and implementation stages are designed as pipeline architecture. In the marine tests performed, it was monitored in real time that the bearing information calculated by the system was compatible with the route of the vessel used in the tests. The signals received by bearing information and the hydrophones were recorded. The records were run offline, and the calculated values were compared. The results obtained showed that the developed FPGA-based system successfully calculates the bearing angle of the vessels by passive listening.

High speed FPGA-based chaotic oscillator design

In this study, autonomous Lü-Chen (2002) chaotic system has been implemented on FPGA using Heun numerical algorithm in VHDL 32-bit IQ-Math fixed-point number format for developing embedded chaos-based engineering applications. The core units like multiplier, adder and subtractor units, which are compatible with fixed-point number standart used in FPGA-based design, have been created by IP CORE Generator that developed for Xilinx. The designed system has been simulated and synthesized for the Virtex–6 FPGA chip. The chip statistics obtained from Place&Route processing of FPGA-based system and the phase portraits of the results received from the outputs have been presented. The results obtained from FPGA-based Lü-Chen chaotic oscillator have been compared with the computer-based results and the accuracy of the digital circuit-based design has been certified with the successful results. The maximum operating frequency of designed FPGA-based Lü-Chen chaotic oscillator is 464.688 MHz. The performed FPGA-based Lü-Chen chaotic oscillator presents the highest operating frequency among the others in the literature. Besides, the design provides better results than the other 3D FPGA-based chaotic oscillator structures with respect to FPGA resource utilization. In addition, MSE and RMSE accuracy analyzes were performed on the designed chaotic oscillator. The design provides the highest operating frequency among the others in the literature. In addition, it presents better results than the alternatives with respect to FPGA resource utilization. For this reason, this study demonstrates that hardware-based design of Lü-Chen chaotic system can be used in various chaos-based embedded system applications including cryptography, secure communication and random number generation.

Performance analysis and prototype filter design for perfect-reconstruction cosine-modulated filter banks with fixed-point implementation

Cosine modulated filter banks have gained popularity for their ability to provide perfect reconstruction (PR) while maintaining an efficient design and implementation. However, this effectiveness is hindered if the filter bank is implemented in the fixed-point domain where quantization, rounding, and overflow occur, and result in reconstruction errors. In this article we demonstrate how to maintain PR of the filter bank when implementing it in fixed-point number format with constant wordlength. We explore how the frequency selectivity of the analysis and synthesis filters changes from the floating point ones due to fixed-point errors and present new design criteria for filter banks that will be implemented in fixed-point number format.

Number format conversion: algorithm and VLSI module generator

An algorithm, an architecture and an automatic parametric VLSI design in the form of a module generator for a number format converter used in data processing applications is presented. It converts any fixed point number format to an expansion of the I.E.E.E. standard extended format for floating point number representation and vice versa. The generator accepts any standard cell library and design rule file and can produce the layout, net-list, footprint and delay of the converter for any bit size of the numbers involved.

A generator for a number format conversion IC

An algorithm, architecture and automatic parametric VLSI design for a number format converter is presented. It converts any fixed point number format to an expansion of the IEEE standard extended format for floating point number representation and vice versa. The generator, written in C and implemented under UNIX, accepts a minimum set of input parameters and produces, for any bit size of the numbers involved, an input file tailored to the Siemens VENUS-S Semicustom Design System.