High speed FPGA-based chaotic oscillator design

Abstract

In this study, autonomous Lü-Chen (2002) chaotic system has been implemented on FPGA using Heun numerical algorithm in VHDL 32-bit IQ-Math fixed-point number format for developing embedded chaos-based engineering applications. The core units like multiplier, adder and subtractor units, which are compatible with fixed-point number standart used in FPGA-based design, have been created by IP CORE Generator that developed for Xilinx. The designed system has been simulated and synthesized for the Virtex–6 FPGA chip. The chip statistics obtained from Place&Route processing of FPGA-based system and the phase portraits of the results received from the outputs have been presented. The results obtained from FPGA-based Lü-Chen chaotic oscillator have been compared with the computer-based results and the accuracy of the digital circuit-based design has been certified with the successful results. The maximum operating frequency of designed FPGA-based Lü-Chen chaotic oscillator is 464.688 MHz. The performed FPGA-based Lü-Chen chaotic oscillator presents the highest operating frequency among the others in the literature. Besides, the design provides better results than the other 3D FPGA-based chaotic oscillator structures with respect to FPGA resource utilization. In addition, MSE and RMSE accuracy analyzes were performed on the designed chaotic oscillator. The design provides the highest operating frequency among the others in the literature. In addition, it presents better results than the alternatives with respect to FPGA resource utilization. For this reason, this study demonstrates that hardware-based design of Lü-Chen chaotic system can be used in various chaos-based embedded system applications including cryptography, secure communication and random number generation.