Fixed-point Hardware Research Articles

Expanding the range of convergence of the CORDIC algorithm

The limitations on the numerical values of the functional arguments that are passed to the CORDIC computational units are discussed, with a special emphasis on the binary, fixed-point hardware implementation. Research in the area of expanding the allowed ranges of the input variables for which accurate output values can be obtained is presented. The methods proposed to expand the range of convergence for the CORDIC algorithm do not necessitate any unwidely overhead calculation, thus making this work amenable to a hardware implementation. The number of extra iterations introduced in the modified CORDIC algorithms is significantly less than the number of extra iterations discussed elsewhere. This reduction in the number of extra iterations will lead to a faster hardware implementation. Examples demonstrate the usefulness of the methods in realistic situations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A fixed-point implementation of the unnormalized least-squares lattice using scaled-integer arithmetic

The unnormalized least-squares lattice algorithm is modified for fixed-point hardware by appropriate scaling of the cross-correlation, covariance, and likelihood parameters. The scaling reveals the dependence of the unnormalized parameter magnitudes on the number of error signal observations used in their respective updates. Comparing fixed-point and floating-point simulations shows no significant loss of precision in the estimated PARCOR coefficients in the fixed-point environment with scaled parameters. Scaling requires seven more multiplies per lattice stage but provides a least-squares lattice algorithm suitable for a wide variety of fast low-power signal processing chips without square-root normalization.

Fast transformation of three-dimensional graphics structures via mixed-point arithmetic

Real-time animation of three-dimensional structures on refreshed tube interactive graphics processors usually requires floating-point arithmetic hardware for matrix manipulation and object transformation by the resultant matrix. An algorithm is described which uses fixed-point hardware to effect the required transformations at speeds surpassing that possible with floating-point hardware with no effective loss in accuracy. The algorithm involves ‘mixed-point arithmetic’—limited precision floating-point multiplication, conversion to an integer-fraction doubleword, and fixed-point addition.