Fixed-point Arithmetic Research Articles

Performance Evaluation of FPGA-Based Design of Modified Chua Oscillator

The chaotic systems are one of the most important areas that increasing the popularity and are actively used in several fields. One of the most essential structures in chaotic systems is chaotic oscillator which generates chaotic signals. IQ-Math and floating point number systems are one of the preferred number standards. Presented in this study, the Modified Chua chaotic oscillator has been designed to work on FPGA chips using fixed point and floating point number systems. Euler numeric algorithm has been used for the design of the Modified Chua chaotic oscillator. The first section of the study, Modified Chua chaotic system based on fixed point has been composed the model in the Matlab Simulink and transformed to VHDL with the help of Matlab HDL Coder Toolbox. The second section of the study, Modified Chua chaotic oscillator has been designed with VHDL based on floating point. Modified Chua chaotic oscillators which are composed with two different number standards have been tested using Xilinx ISE Design Tools in VHDL. Modified Chua chaotic oscillators which have two different numbers standards and designed, are synthesized for Virtex-6 on ML605 FPGA development board with Xilinx ISE Design Tools 14.2 program. Values that are achieved from the process of synthesizing and maximum operating frequency have been presented. As a result, the study has obtained that fixed point number standard maximum operating frequency is 50.242 MHz and floating point number standard maximum operating frequency is 273.631 MHz.

Implementation of Artificial Neural Networks on Field-Programmable Gate Arrays

Implementing Artificial Neural Networks (ANNs) on Field-Programmable Gate Arrays (FPGAs) provides a promising solution for achieving high-performance, low-latency, and energy-efficient computations in complex tasks. This paper investigates the methodology for mapping ANNs onto FPGAs, focusing on critical aspects such as architecture selection, hardware design, and optimization techniques. By harnessing the parallel processing capabilities and reconfigurability of FPGAs, neural network computations are significantly accelerated, making them ideal for real-time applications like image processing and embedded systems. The implementation process addresses key considerations, including fixed-point arithmetic, memory management, and dataflow optimization, while employing advanced techniques such as pipelining, quantization, and pruning. The research compares the accuracy and performance speedup of ANNs on CPUs versus FPGAs, revealing that FPGA-based simulations are 4680 times faster than CPU-based simulations using MATLAB, without compromising prediction accuracy.

Multiple-base Logarithmic Quantization and Application in Reduced Precision AI Computations

The power of logarithmic quantizations and computations has been recognized as a useful tool in optimizing the performance of large ML models. There are plenty of applications of ML techniques in digital preservation. The accuracy of computations may play a crucial role in the corresponding algorithms. In this article, we provide results that demonstrate significantly better quantization signal-to-noise ratio performance thanks to multiple-base logarithmic number systems (MDLNS) in comparison with the floating point quantizations that use the same number of bits. On a hardware level, we present details about our Xilinx VCU-128 FPGA design for dot product and matrix vector computations. The MDLNS matrix-vector design significantly outperforms equivalent fixed-point binary designs in terms of area (A) and time (T) complexity and power consumption as evidenced by a 4 × scaling of AT 2 metric for VLSI performance, and 57% increase in computational throughput per watt compared to fixed-point arithmetic.

Code Generation for Neural Networks Based on Fixed-point Arithmetic

Over the past few years, neural networks have started penetrating safety critical systems to make decisions as, for example, in robots, rockets, and autonomous driving cars. Neural networks based on floating-point arithmetic are very time and memory consuming, which are not compatible with embedded systems known to have limited resources. They are also very sensitive to the precision in which they have been trained, so changing this precision generally degrades the quality of their answers. To deal with that, we introduce a new technique to generate a fixed-point code for a trained neural network. This technique is based on fixed-point arithmetic with mixed-precision. This arithmetic is based on integer operations only, which are compatible with small memory devices. The obtained neural network has the same behavior as the initial one (based on the floating-point arithmetic) up to an error threshold defined by the user. The experimental results show the efficiency of our tool SyFix in terms of memory saved and the accuracy of the computations.

A Survey of Computationally Efficient Graph Neural Networks for Reconfigurable Systems

Graph neural networks (GNNs) are powerful models capable of managing intricate connections in non-Euclidean data, such as social networks, physical systems, chemical structures, and communication networks. Despite their effectiveness, the large-scale and complex nature of graph data demand substantial computational resources and high performance during both training and inference stages, presenting significant challenges, particularly in the context of embedded systems. Recent studies on GNNs have investigated both software and hardware solutions to enhance computational efficiency. Earlier studies on deep neural networks (DNNs) have indicated that methods like reconfigurable hardware and quantization are beneficial in addressing these issues. Unlike DNN research, studies on efficient computational methods for GNNs are less developed and require more exploration. This survey reviews the latest developments in quantization and FPGA-based acceleration for GNNs, showcasing the capabilities of reconfigurable systems (often FPGAs) to offer customized solutions in environments marked by significant sparsity and the necessity for dynamic load management. It also emphasizes the role of quantization in reducing both computational and memory demands through the use of fixed-point arithmetic and streamlined vector formats. This paper concentrates on low-power, resource-limited devices over general hardware accelerators and reviews research applicable to embedded systems. Additionally, it provides a detailed discussion of potential research gaps, foundational knowledge, obstacles, and prospective future directions.

"Enhanced DA Algorithm for FIR Filter Design and FPGA Implementation"

Abstract: This study looks into the difficulties of using the Distributed Arithmetic (DA) method for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). It focuses on how coefficients are represented, balancing precision using fixed-point arithmetic and quantization. The research explores ways to optimize memory use, aiming to store data more efficiently within FPGA resources and reduce memory needs. To speed up computations, it examines how to make accessing lookup tables faster and suggests improvements in design. The study also considers how to manage FPGA resources effectively, balancing latency, throughput, and resource use. It looks at specific improvements to the DA method for FIR filters to make better use of resources and enhance performance. Overall, this work provides insights and solutions for algorithm design, memory use, lookup table speed, and FPGA architecture to make DA-based FIR filter implementations on FPGAs more efficient.

The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW

The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW

A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic

A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic

Lorenz Kaotik Devre Tabanlı Entropi Kaynağı ile Özgün Gerçek Rasgele Sayı Üretimi ve Ses Şifreleme Uygulaması

This paper introduces a methodology for generating secure cryptographic key bits from analog values obtained from the Lorenz chaotic circuit. The analog values are transferred from the chaotic circuit to the computer via an Analog Discovery-2 device and then post-processed by using a fixed-point number representation format and Von-Neumann corrector for the sampled values on the MATLAB program. By employing this method, the analog values are digitized and randomized as the main idea is to obtain secure and efficient statistically random bits. Furthermore, the generated random bits are utilized for secure audio transmission by demonstrating a practical application of the proposed methodology. In addition to the classical randomness test criteria, and NIST 800.22 statistical test suite, the throughput bit stream is also subjected to Chi-square and FIPS 140-1 tests to further evaluate its effectiveness. The results of these comprehensive tests confirm the successful performance of the proposed system in generating statistically random bits and its secure audio encryption system. The utilization of the Lorenz chaotic circuit as an entropy source in generating true random bits for secure audio transmission applications showcases the potential of the proposed system.

Rationalized diffraction calculations for high accuracy and high speed with few bits.

Diffraction calculations in few-bit formats, such as single-precision floating-point and fixed-point numbers, are important because they yield faster calculations and lower memory usage. However, these methods suffer from low accuracy owing to the loss of trailing digits. Fresnel diffraction is widely known to prevent the loss of trailing digits. However, it can only be used when the paraxial approximation is valid. In this study, a few-bit diffraction calculation method that achieves high accuracy without using any approximation is proposed. The proposed method is derived only by rationalizing the numerator of conventional formulas. Even for scenarios requiring double-precision floating-point numbers using conventional methods, the proposed method exhibits higher accuracy and faster computation time using single-precision floating-point numbers.

Design and Implementation of Nursing-Secure-Care System with mmWave Radar by YOLO-v4 Computing Methods

In computer vision and image processing, the shift from traditional cameras to emerging sensing tools, such as gesture recognition and object detection, addresses privacy concerns. This study navigates the Integrated Sensing and Communication (ISAC) era, using millimeter-wave signals as radar via a Convolutional Neural Network (CNN) model for event sensing. Our focus is on leveraging deep learning to detect security-critical gestures, converting millimeter-wave parameters into point cloud images, and enhancing recognition accuracy. CNNs present complexity challenges in deep learning. To address this, we developed flexible quantization methods, simplifying You Only Look Once (YOLO)-v4 operations with an 8-bit fixed-point number representation. Cross-simulation validation showed that CPU-based quantization improves speed by 300% with minimal accuracy loss, even doubling the YOLO-tiny model’s speed in a GPU environment. We established a Raspberry Pi 4-based system, combining simplified deep learning with Message Queuing Telemetry Transport (MQTT) Internet of Things (IoT) technology for nursing care. Our quantification method significantly boosted identification speed by nearly 2.9 times, enabling millimeter-wave sensing in embedded systems. Additionally, we implemented hardware-based quantization, directly quantifying data from images or weight files, leading to circuit synthesis and chip design. This work integrates AI with mmWave sensors in the domain of nursing security and hardware implementation to enhance recognition accuracy and computational efficiency. Employing millimeter-wave radar in medical institutions or homes offers a strong solution to privacy concerns compared to conventional cameras that capture and analyze the appearance of patients or residents.

FPGA realization of an image encryption system using the DCSK-CDMA technique

This paper describes a four-wing chaotic oscillator-based DCSK-CDMA modulation technique for image encryption and decryption. The system consists of a transmission module for the encrypted and modulated color matrices, and a reception module for the decrypted and demodulated original data. Among our main contributions is the integration for the first time in the state of the art of DCSK chaotic modulation techniques with the CDMA communication scheme, as well as the implementation of our DCSK and CDMA algorithms in VHDL language for Xilinx FPGA cards. The DCSK-CDMA technique enables demodulation and decryption without any loss in the original data. Other contributions arising from this investigation are the encryption process implemented using DCSK-CDMA techniques based on a four-wing chaotic oscillator and the realization on the FPGA of a chaos-based communications system for the secure transmission of images of grayscale and RGB formats using DCSK-CDMA techniques. The system architecture in this work was designed using fixed-point binary arithmetic, with the application of the 4th order Runge–Kutta numerical method for the four-wing chaotic oscillator. The analysis of the correlation coefficients between the original and encrypted information indicates the values of 5.367×10−4 and −2.205×10−7 for grayscale and RGB images, respectively, with a full recovery of the original information. The results of simulations in MATLAB/Simulink coincide with the implementation of the complete system in VHDL on the Xilinx Artix-7 AC701 board.

A Fast Fixed-Point Logarithmic Functions Based on ARM Microprocessor

The fixed-point mathematical library refers to a highly optimized collection of high-precision mathematical functions primarily used for fast and high-precision real-time calculations. It can execute equivalent code written in the C language with floating-point format faster, while maintaining considerable accuracy. Current mainstream fixed-point mathematical libraries face issues such as being non-open source, having unknown models, incomplete basic mathematical operation functions, and insufficient precision. Therefore, designing an open-source, fast, more optimized, and high-precision fixed-point mathematical library will have a groundbreaking impact. It can not only play a crucial role in industrial control algorithms but also eliminate the dependency of domestic fixed-point MCUs on foreign library functions. This paper conducts research on fixed-point arithmetic for logarithmic functions, designs, and improves the implementation of fast logarithmic functions.Taking Q12 as an example, Simulation experiments and MCU experiments show that, in the Q12 format, the highest precision that can be represented by a 32-bit fixed-point number is 0.000244141. From the test results, it can be observed that for 98.15% of the test data, the computational errors of the two mathematical libraries are both smaller than the highest precision value. Both two logarithmic function computations can maintain good computational accuracy within the ARM microprocessor. In terms of computational speeds, the average computation cycle of the fixed-point logarithmic function designed in this paper is reduced by 31.88% compared to the counterpart. This substantial improvement in computational speed, while ensuring computational accuracy, enhances the performance of fixed-point logarithmic operations based on ARM microprocessors.

Fast and Clean: Auditable high-performance assembly via constraint solving

Handwritten assembly is a widely used tool in the development of highperformance cryptography: By providing full control over instruction selection, instruction scheduling, and register allocation, highest performance can be unlocked. On the flip side, developing handwritten assembly is not only time-consuming, but the artifacts produced also tend to be difficult to review and maintain – threatening their suitability for use in practice.In this work, we present SLOTHY (Super (Lazy) Optimization of Tricky Handwritten assemblY), a framework for the automated superoptimization of assembly with respect to instruction scheduling, register allocation, and loop optimization (software pipelining): With SLOTHY, the developer controls and focuses on algorithm and instruction selection, providing a readable “base” implementation in assembly, while SLOTHY automatically finds optimal and traceable instruction scheduling and register allocation strategies with respect to a model of the target (micro)architecture.We demonstrate the flexibility of SLOTHY by instantiating it with models of the Cortex-M55, Cortex-M85, Cortex-A55 and Cortex-A72microarchitectures, implementing the Armv8.1-M+Helium and AArch64+Neon architectures. We use the resulting tools to optimize three workloads: First, for Cortex-M55 and Cortex-M85, a radix-4 complex Fast Fourier Transform (FFT) in fixed-point and floating-point arithmetic, fundamental in Digital Signal Processing. Second, on Cortex-M55, Cortex-M85, Cortex-A55 and Cortex-A72, the instances of the Number Theoretic Transform (NTT) underlying CRYSTALS-Kyber and CRYSTALS-Dilithium, two recently announced winners of the NIST Post-Quantum Cryptography standardization project. Third, for Cortex-A55, the scalar multiplication for the elliptic curve key exchange X25519. The SLOTHY-optimized code matches or beats the performance of prior art in all cases, while maintaining compactness and readability.

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

In this article, a low-complexity VLSI architecture based on a radix-4 hyperbolic COordinate Rotion DIgital Computer (CORDIC) is proposed to compute the N{{rm th}} root and N{{rm th}} power of a fixed-point number. The most recent techniques use the radix-2 CORDIC algorithm to compute the root and power. The high computation latency of radix-2 CORDIC is the primary concern for the designers. N{{rm th}} root and N{{rm th}} power computations are divided into three phases, and each phase is performed by a different class of the proposed modified radix-4 CORDIC algorithms in the proposed architecture. Although radix-4 CORDIC can converge faster with fewer recurrences, it demands more hardware resources and computational steps due to its intricate angle selection logic and variable scale factor. We have employed the modified radix-4 hyperbolic vectoring (R4HV) CORDIC to compute logarithms, radix-4 linear vectoring (R4LV) to perform division, and the modified scaling-free radix-4 hyperbolic rotation (R4HR) CORDIC to compute exponential. The criteria to select the amount of rotation in R4HV CORDIC is complicated and depends on the coordinates X^j and Y^j of the rotating vector. In the proposed modified R4HV CORDIC, we have derived the simple selection criteria based on the fact that the inputs to R4HV CORDIC are related. The proposed criteria only depend on the coordinate Y^j that reduces the hardware complexity of the R4HV CORDIC. The R4HR CORDIC shows the complex scale factor, and compensation of such scale factor necessitates the complex hardware. The complexity of R4HR CORDIC is reduced by pre-computing the scale factor for initial iterations and by employing scaling-free rotations for later iterations. Quantitative hardware analysis suggests better hardware utilization than the recent approaches. The proposed architecture is implemented on a Virtex-6 FPGA, and FPGA implementation demonstrates 19% less hardware utilization with better error performance than the approach with the radix-2 CORDIC algorithm.

Certification of the proximal gradient method under fixed-point arithmetic for box-constrained QP problems

In safety-critical applications that rely on the solution of an optimization problem, the certification of the optimization algorithm is of vital importance. Certification and suboptimality results are available for a wide range of optimization algorithms. However, a typical underlying assumption is that the operations performed by the algorithm are exact, i.e., that there is no numerical error during the mathematical operations, which is hardly a valid assumption in a real hardware implementation. This is particularly true in the case of fixed-point hardware, where computational inaccuracies are not uncommon. This article presents a certification procedure for the proximal gradient method for box-constrained QP problems implemented in fixed-point arithmetic. The procedure provides a method to select the minimal fractional precision required to obtain a certain suboptimality bound, indicating the maximum number of iterations of the optimization method required to obtain it. The procedure makes use of formal verification methods to provide arbitrarily tight bounds on the suboptimality guarantee. We apply the proposed certification procedure on the implementation of a non-trivial model predictive controller on 32-bit fixed-point hardware.

Echo state network implementation for chaotic time series prediction

The implementation of an Echo State Neural Network (ESNN) for chaotic time series prediction is introduced. First, the ESNN is simulated using floating-point arithmetic and afterwards fixed-point arithmetic. The synthesis of the ESNN is done in a field-programmable gate array (FPGA), in which the activation function of the neurons’ outputs is a hyperbolic tangent one, and is approximated with a new design of quadratic order b-splines and four integer multipliers. The FPGA implementation of the ESNN is applied to predict four chaotic time series associated to the Lorenz, Chua, Lü, and Rossler chaotic oscillators. The experimental results show that with 50 hidden neurons, the fixed-point arithmetic is good enough when using 15 or 16 bits in the fractional part: using more bits does not reduce the mean-squared error prediction. The neurons are limited to four inputs in the hidden layer to achieve a more efficient hardware implementation, guaranteeing a prediction of more than 10 steps ahead.

A high speed and power efficient multiplier based on counter-based stacking

<span>High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of <a name="_Hlk140074299"></a>arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products that are to be added to get final product. These partial products in number and the process of summing up partial products dictate the latency and power consumption of the multiplier design. Here, we present a novel binary counter design that hires stacking circuits, that groups all logic “1” bits as one, followed by a novel symmetric method to merge pairs of 3-bit stacks into 6-bit stacks and then changes them to binary counts. This results in drastic improvements in power and area utilization of the multiplier. Additionally, this paper also focuses on implementation of novel approximate compressor and exploits the same for the design of approximate multipliers that can be effectively employed in any electronic systems that are characterized by power and speed constraints.</span>

A streaming algorithm and hardware accelerator to estimate the empirical entropy of network flows

The empirical entropy is used in network traffic monitoring and classification to detect anomalous events and manage network resources. Computing the entropy of high-speed traffic in real time requires dedicated hardware, such as programmable switches and FPGA-based accelerators. While these devices can achieve high performance by exploiting the parallelism of the algorithm, they possess limited on-chip storage. Thus, designing algorithms that estimate the entropy of network traffic with low error and memory usage is challenging. In this paper, we present an entropy-estimation streaming algorithm that operates on large datasets with sublinear memory usage. We use sketches to estimate the frequency and cardinality of network flows during an observation interval. We only store the frequencies of the most frequent flows and use them to estimate the rest of the frequencies by assuming a power-law distribution. Our results show that, using real network traces with observation intervals of up to 50 million flows, we can estimate their empirical entropy with 0.69% mean relative error, using more than three orders of magnitude less memory than an exact entropy-computation method. We also present an FPGA-based hardware accelerator for the algorithm that can operate at a line rate of more than 200 Gbps and an estimation latency of 16μs. Using fixed-point arithmetic and function approximations in the accelerator increases the mean estimation error of our algorithm by only 0.07%.

Divisions and Square Roots with Tight Error Analysis from Newton–Raphson Iteration in Secure Fixed-Point Arithmetic

In this paper, we present new variants of Newton–Raphson-based protocols for the secure computation of the reciprocal and the (reciprocal) square root. The protocols rely on secure fixed-point arithmetic with arbitrary precision parameterized by the total bit length of the fixed-point numbers and the bit length of the fractional part. We perform a rigorous error analysis aiming for tight accuracy claims while minimizing the overall cost of the protocols. Due to the nature of secure fixed-point arithmetic, we perform the analysis in terms of absolute errors. Whenever possible, we allow for stochastic (or probabilistic) rounding as an efficient alternative to deterministic rounding. We also present a new protocol for secure integer division based on our protocol for secure fixed-point reciprocals. The resulting protocol is parameterized by the bit length of the inputs and yields exact results for the integral quotient and remainder. The protocol is very efficient, minimizing the number of secure comparisons. Similarly, we present a new protocol for integer square roots based on our protocol for secure fixed-point square roots. The quadratic convergence of the Newton–Raphson method implies a logarithmic number of iterations as a function of the required precision (independent of the input value). The standard error analysis of the Newton–Raphson method focuses on the termination condition for attaining the required precision, assuming sufficiently precise floating-point arithmetic. We perform an intricate error analysis assuming fixed-point arithmetic of minimal precision throughout and minimizing the number of iterations in the worst case.