Fixed Delay Tree Search Research Articles

Performance evaluation of detectors for perpendicular recording systems

This paper evaluates the performance of detectors with d = 1 constraint for perpendicular recording systems under assumptions of nonlinear distortion. Nonlinear distortions considered are transition jitter and DC-offset. Detectors used in this study are the partial response maximum likelihood (PRML), noise-predictive maximum likelihood (NPML), fixed delay tree search with decision feedback (FDTS/DF), dual decision feedback equalizer (DDFE) and multilevel decision feedback equalizer (MDFE). Their performances are discussed in terms of mean squared error (MSE) and noise power spectra of equalizer at discrimination point and similarity of frequency response between overall system and partial response (PR) target polynomial.

다차원 신호공간 분할을 이용한 데이터 복원

본 논문에서는 심볼간의 간섭이 존재하는 채널에서 고정 지연 값을 가지는 트리검색 신호검출기의 효율적인 구성방법을 다룬다. 이 접근방법은 효율적인 다차원 신호공간 분할에 기반을 두고 있다 다차원 공간에서의 Voronoi 다이어그램 (VoD)과 Delaunay 분할 (DT)이 신호검출 알고리즘의 구현에 적용된다 제안된 방식에서는 VOD/DT에 포함되어 있는 기하학적인 정보를 활용하여 관찰된 순차적인 신호의 상대적인 위치가 결정되며 이러한 방식이 구현치 복잡도를 감소시키는 장점이 있음을 보인다. 구체적인 구성 절차가 심볼간의 간섭이 존재하는 통신채널에서의 예를 가지고 논의되며 시뮬레이션 결과가 논의된다. This paper deals with a systematic approach for the construction of the fixed-delay tree search (FDTS) detector in the intersymbol interference channel. The approach is based on the efficient multi-dimensional space partitioning. The Voronoi diagram (VoD) and the Delaunay tessellation (DT) of the multi-dimensional space are applied to implement the algorithm. In the proposed approach, utilizing the geometric information contained in the VOD/DT, the relative location of the observation sequence is determined which has been shown to reduce the implementation complexity. Detailed construction procedures are discussed followed by an example from the intersymbol interference communication channel.

Mostly analog disk drive read channel with practical depth-of-two fixed delay tree search

A new read-channel arrangement for use with d=1 codes equalizes the input to extended partial response IV (EPR4) for clock recovery, and follows this with a new realization of a fixed delay tree search with decision feedback detector with search depth of two. The detector and a discrete-time phase detector for clock recovery share a five-tap finite-impulse response forward equalizer. Clock recovery from EPR4 is fast, while forward and feedback equalizers need no adaptation of tap weights. The read channel, originally developed for a rate-4/5 X{101} code, is extended to the more efficient rate-6/7 maximum-transition-run (MTR) codes. The detector consists of a conventional decision feedback equalizer, assisted by an error-correction circuit to sense and eliminate the major error events, thus performing as well as tree search with depth of two. With MTR code, the read channel outperforms EPR4 with Viterbi detection by 1 dB.

Simplified signal space detector for optical recording

A signal space detector is a low-complexity approximation of fixed-delay tree search with decision feedback (FDTS/DF). This paper proposes the simplest version possible of a /spl tau/ = 2 FDTS/DF for a minimum run-length constraint of d = 2. The hardware needs only two multiplications and additions, facilitating high data-rate/low-complexity implementations. Simulation results show that the performance of the proposed detector equals that of the /spl tau/ = 2 FDTS/DF even when jitter noise is present. It is shown that for d = 2, a partial response maximum-likelihood detector with the target response /spl Sigma//sub k=0//sup 3/ D/sup k/ outperforms one with (1 + D)/sup 3/ because of good spectral matching at normalized density S /spl ges/ 4.6.

Dual FDTS/DF: a unified approach to dual-detection and modification for MTR codes

Dual-detector decision-feedback schemes have recently gained considerable interest in magnetic recording. Schemes such as dual decision feedback equalization (DDFE), M2DFE, and dual FDTS/DF are dual-detector versions of DFE, multilevel DFE (MDFE), and fixed delay tree search with decision feedback fixed-delay tree search with decision feedback (FDTS/DF) detectors, respectively. At high recording densities, the dual-detector versions significantly improve bit-error-rate (BER) performance and reduce error propagation. In this paper, we first give a unified approach to the bit-error-rate analysis of dual-detector decision feedback schemes in an attempt to highlight their relationship, and then we show that the performance of dual FDTS/DF reduces to that of DDFE for /spl tau/=0 and reduces to that of M2DFE for /spl tau/=1 with d=1 code constraint. Further, we extend the dual FDTS/DF detection scheme to maximum transition run-length (MTR) coded channels. On the basis of both BER and error event analysis, we propose a modified dual FDTS/DF detection scheme for MTR-coded channels that improves BER performance. The new scheme modifies certain bits in the detection profess for preventing the dominant error event. Simulation results on 6/7 MTR-coded Lorentzian channel show that the modified detector gives around 1 dB SNR improvement over the advanced (trellis-coded extended partial response) TC-E/sup 2/PR detector.

A novel fast approach for estimating error propagation in decision feedback detectors

The study of error-burst statistics is important for all detection systems, and more so for the decision feedback class. In data storage applications, many detection systems use decision feedback in one form or another. Fixed-delay tree search with decision feedback (FDTS/DF) and decision feedback equalization (DFE) are the direct forms, whereas the partial response detectors such as the reduced state sequence estimator (RSSE) and noise predictive maximum likelihood (NPML) detectors are the other forms. Although DF reduces the system complexity, it is inevitably linked with error propagation (EP), which can be quantified using error-burst statistics. Analytical evaluation of these statistics is difficult, if not impossible, because of the complexity of the problem. Hence, the usual practice is to use computer simulations. However, the computational time in traditional bit-by-bit simulations can be prohibitive at meaningful signal-to-noise ratios. In this paper, we propose a novel approach for fast estimation of error-burst statistics in FDTS/DF detectors, which is also applicable to other detection systems. In this approach, error events are initiated more frequently than natural by artificially injecting noise samples. These noise samples are generated using a transformation that results in significant reduction in computational complexity. Simulation studies show that the EP performance obtained by the proposed method matches closely with those obtained by bit-by-bit simulations, while saving as much as 99% of simulation time.

Signal space detection for DVD optical recording

A signal space detector (SSD) based on a single hyperplane is proposed which offers nearly the same performance as the fixed delay tree search with decision feedback (FDTS/DF) for the digital versatile disk (DVD) channel. The FDTS/DF detector with a reasonable decision delay performs almost as well as the optimal maximum likelihood sequence detector (MLSD) due to the FDTS/DF plus modulation code that includes the d=2 minimum runlength constraint. The single-hyperplane approximation of the FDTS/DF detector is made possible by considering only the critical signal points in the three-dimensional signal space. When the jitter noise is significant, the slope of the hyperplane decision boundary can readily be adjusted to improve the performance beyond that of the standard FDTS/DF detector. We also provide analysis and simulation results that verify the performance advantage of the SSD over partial response (PR) based threshold and Viterbi detectors. The distance between the received signal in signal space and the single hyperplane can be interpreted as soft information. The soft SSD can be used along with iterative error correction codes, such as low density parity check codes (LDPC), resulting in large performance gains.

Performance of Run-Length-Limited (3, 11) Code for Optical Storage

This paper introduces a run-length-limited (RLL) (3, 11) code and compares its performance with that of the EFMPlus code using four different detection methods including partial response maximum likelihood (PRML), fixed delay tree search with decision feedback (FDTS/DF), partial response with decision feedback equalizer (PR-DFE) and decision feedback equalizer (DFE). The advantages of the proposed code are: (1) the larger density ratio and (2) the simple encoder/decoder.

An Advanced Signal Detection Technique for Digital Versatile Disc Systems

We compare various signal detection techniques for high-density digital versatile disc (DVD) systems in terms of performance and hardware complexity, and propose a fixed-delay trellis search with decision feedback (FDTrS/DF) suitable for ASIC chip implementation. Based on various simulation and implementation results, it is shown that the proposed FDTrS/DF provides the best performance among various signal detection techniques, such as partial response maximum likelihood (PRML), decision feedback equalizer (DFE), fixed-delay tree search with decision feedback (FDTS/DF), and signal space detection with decision feedback (SSD/DF), even with low hardware complexity.

A 300-MHz fixed-delay tree search-DFE analog CMOS disk-drive read channel

A decision feedback equalizer (DFE) with digital error detection and correction implements a fixed-delay tree search with depth of 2. The disk-drive read waveform is first equalized to EPR4 for clock recovery and then re-equalized to the DFE target. A mostly analog implementation of this read channel in 0.6-/spl mu/m CMOS implements a tapped delay-line forward filter with a cascade of track-and-hold circuits and variable transconductors. Using MTR (2,k) code, the compact read channel IC surpasses a conventional EPR4 read channel with Viterbi detector at user densities in the range 2.0-3.0.

A CMOS two-path tree search detector

Two-path tree search (TPTS) is a detection algorithm combining a decision-feedback equalizer and a two-path tree search estimator. This sub-optimal tree search overcomes the exponential increase in hardware complexity with tree length in a fixed-delay tree search structure. An adaptive mixed-signal CMOS TPTS detector is presented in this paper. The integrated circuit occupies 2.77 mm by 2.44 mm (including the bonding pads) in a 0.6 /spl mu/m CMOS process. It performs about 0.8 dB better than a conventional decision-feedback equalization for a disk drive read channel.

Implementation of an FDTrS/DF signal detector for high-density DVD systems

In this paper, a signal detection technique, called a fixed-delay trellis search with decision feedback (FDTrS/DF), is proposed for high-density DVD systems and implemented with FPGA and ASIC chips. The proposed FDTrS/DF always performs better than the signal detection techniques based on tree search structure such as the fixed-delay tree search with decision feedback (FDTS/DF) and the signal space detection with decision feedback (SSD/DF). Also, the FDTrS/DF can reduce hardware complexity significantly due to the unique structure of FDTrS composed of only one trellis stage, requiring no traceback procedure. The hardware complexity of the proposed FDTrS/DF is further reduced by employing the criterion of the absolute branch metric (instead of square branch metric) and applying a pipelining technique. It is shown by simulation and implementation results that the proposed FDTrS/DF provides the best performance among various signal detection techniques such as PRML, DFE, FDTS/DE and SSD/DF, even with a small hardware complexity.

The role of SP in data-storage systems

Among the key components in the development of a successful storage system are heads, media, and signal processing. In the past, major breakthroughs in the heads and media technologies have been mainly responsible for the spectacular growth in storage capacity, but signal processing is increasingly recognized as a cost-efficient means of improving density. This article addresses the issues relevant to signal processing. While the focus is on magnetic storage, most of the signal-processing strategies discussed are also applicable to optical storage. This article begins with a description of the read/write (R/W) process in magnetic storage. The characteristics of noise and nonlinearity present in real magnetic storage channels are also discussed, and a discussion on channel modeling is followed by a description of different modulation codes. Different suboptimal sequence detectors and equalizers are then presented that represent the techniques that are either already in use in commercial systems or being investigated for near-future applications. We then discuss sequence detectors, with in-depth treatment given to those based on tree search, particularly finite or fixed delay tree search (FDTS) detectors. Finally, performance evaluation results are presented under various channel conditions, which should be useful in assessing the potential benefits of different coding and sequence-detection strategies.

High speed implementation of signal space detectors

In this paper, we generalize the concept of signal space detection to construct a fixed delay tree search (FDTS) detector which estimates a block of n channel symbols at a time. This technique is useful for high speed implementation. Two approaches are discussed both of which are based on signal space partitioning. In the first approach, symbol detection is performed based on a multi-class partitioning of the signal space. This approach is a generalization of binary symbol detection based on two-class pattern classification. In the second approach, binary signal detection is combined with a look-ahead technique, resulting in a highly parallel detector architecture.

Sequence detection for binary ISI channels using signal-space partitioning

Binary symbol detection based on a sequence of finite observation signals is formulated in the multidimensional signal space. A systematic space partitioning method is proposed to divide the entire space into two decision regions using a set of hyperplanes. The resulting detector structure consists of K parallel linear classifiers followed by a K-to-1 Boolean mapper, and is well suited to high-speed implementation. Compared to direct implementation of the fixed-delay tree search (FDTS) detection rule, the proposed signal-space formulation results in a considerable saving in digital hardware. Examples taken from binary-input intersymbol interference (ISI) channels are used to demonstrate the proposed technique. Block processing strategies suitable for high-speed applications are also discussed.

Correlation-sensitive adaptive sequence detection

In high density magnetic recording, noise samples corresponding to adjacent signal samples are heavily correlated as a result of front-end equalizers, media noise, and signal nonlinearities combined with nonlinear filters to cancel them. This correlation significantly deteriorates the performance of detectors at high densities. In this paper, we propose a novel sequence detector that is correlation sensitive and adaptive to the nonstationary signal sample statistics. We derive the correlation-sensitive maximum likelihood detector. It can be used with any Viterbi-like receiver (e.g., partial response maximum likelihood, fixed delay tree search, multilevel decision feedback equalization) that relies on a tree/trellis structure. Our detector adjusts the metric computation to the noise correlation statistics. Because these statistics are nonstationary, we develop an adaptive algorithm that tracks the data correlation matrices. Simulation results are presented that show the applicability of the new correlation-sensitive adaptive sequence detector.

High-speed CMOS continuous-time complex graphic equalizer for magnetic recording

A high-speed continuous-time CMOS analog adaptive equalizer for use in magnetic recording read channels is presented. The equalizer is implemented as the summation of several bandpass filters covering different frequency bands as in a graphic equalizer. The outputs from each filter are weighted by a complex coefficient and summed, which results in a linear combiner structure guaranteed to converge under least mean square (LMS) adaptation. System-level simulations of our "complex graphic equalizer (CGE)" show that its performance is comparable to that of a ten-tap finite impulse response (FIR) equalizer following a fourth-order low-pass filter when tested with two different sequence detectors: EPR4-MLSD and fixed delay tree search with decision feedback (FDTS/DF). A five-band tunable CGE has been fabricated using a 0.8-/spl mu/m CMOS technology. The highest band of the fabricated CGE was centered at 80 MHz (corresponding to channel data rate of about 200 Msymbols/s). Measured dynamic range was 68 dB, and measured total harmonic distortion was only -75 dB while consuming 97 mW at 3.3 V. The measured CGE performance agreed within 0.2 dB with the simulation results for an FDTS/DF system with an ideal CGE operating at 2.5 user bits/PW50.

A comparison of detection methods in the presence of nonlinearities

In this paper we evaluate the detectability of nonlinear signals characteristic of high-density, magnetic recording channels read by a magneto-resistive (MR) head. We first introduce a signal model which performs nonlinear superposition of experimentally-collected MR-head transition responses. Feeding signals synthesized from this model through a detection simulator, we compare the performance of Decision Feedback Equalization (DFE), RAM DFE, Partial Response Maximum-likelihood detection with PR4, EPR4, and E/sup 2/PR4 targets, and Fixed Delay Tree Search with Decision Feedback (FDTS/DF) in the presence of time and amplitude nonlinearities. Signals are generated at a variety of signal-to-noise ratios (SNRs) and densities with runlength constraints of (0,3) and (1,7). We found that the most detrimental nonlinearities come from amplitude asymmetry characteristic of poorly biased MR heads, and such nonlinearities cause a loss of between 0.5 and 1 orders of magnitude in bit error rate. We found that of the schemes, FDTS/DF provided the great robustness against all nonlinearities in the presence of RLL(1,7) coding, and EPR4ML and E/sup 2/PR4ML preformed the best with RLL(0,3) coding.

A BiCMOS implementation of a 276 MS/s forward equalizer and 200 MS/s FDTS detector

An analog finite impulse response filter (FIR) and an analog fixed delay tree search (FDTS) tau=l detector suitable for disk drive applications are presented. The FIR uses a rotary architecture with interleaved operation which allows clock rates up to 276 MS/s to be used. The FIR has seven taps, all programmable to six bit weights, and is implemented in fully differential form. The detector operates with clock rates up to 200 MS/s with no code restrictions. It makes use of a reduced minimum mean square error equation set to simplify the detector. Dual feedback filters are also used to shorten the critical path. A seven tap feedback filter is used with six bits of resolution per tap. The FIR consumes 180 mW while the detector uses 270 mW. The die size including all test buffers for the FIR and detector is 5.2 mm/sup 2/.

Practical MTR-FDTS (τ=2) read channel for the <200 Mbit/sec Era

This paper presents an architecture for a fixed-delay tree search with feedback (FDTS/DF) channel which uses a maximum transition run-length code. The critical timing path in this new detector is comparable to that of a decision feedback detector. The forward filter consists of a first-order all-pass filter cascaded with a fourth-order Bessel filter. Timing and gain recovery are also discussed.