Abstract

A decision feedback equalizer (DFE) with digital error detection and correction implements a fixed-delay tree search with depth of 2. The disk-drive read waveform is first equalized to EPR4 for clock recovery and then re-equalized to the DFE target. A mostly analog implementation of this read channel in 0.6-/spl mu/m CMOS implements a tapped delay-line forward filter with a cascade of track-and-hold circuits and variable transconductors. Using MTR (2,k) code, the compact read channel IC surpasses a conventional EPR4 read channel with Viterbi detector at user densities in the range 2.0-3.0.

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