In this study, an IDC applicable for use with temperature and humidity sensors was designed. To this end, we take into account the factors of area and accuracy, a simple second-order chain of integrators with forward (CIFF) architecture was used to achieve an effective number of bits (ENOB) of 16.5. A gain-boosted operational amplifier (op amp) with a gain of up to 145 dB was adopted for the first-order integrator, and the digital filter adopted a sincL structure. In Section 2.1, the working principle of the proposed second-order. IDC is introduced. In Section 2.2, the design specifications are presented, the system timing and circuit structure are introduced, the circuit structure of the first-order integrator is described in detail, and the overall simulation results are provided. In Section 3, the test results obtained for a physical chip implemented using the SMIC 0.18 μm process are presented and compared with those obtained by similar previously proposed designs. Measurements show that the incremental converter achieves 99.1 dB SNR higher than the other second-orders or even some three-order IDC. And the chip occupied an effective area of 0.211 mm2 smaller than the other IDC. Finally, the conclusions of this study are given in Section 5.