First-level Interconnects Research Articles

Development of Model for Identification of Process Parameters for Wet Decapsulation of Copper–Aluminum Wirebond in PEMs

Decapsulation is a failure analysis technique often used to expose the die and first-level interconnects such as wirebonds by dissolving the surrounding epoxy molding compound (EMC). The wet decapsulation technique, which uses fuming acids, works very well for traditional gold (Au) wirebonds. On the other hand, its latest alternative, copper (Cu) wirebond, reacts with the nitric acid vigorously and undergoes severe corrosion. It is important to develop an acid chemistry that can be used to perform decapsulation of Cu–Al incorporated plastic encapsulated microelectronics (PEMs) without damaging the Cu wires. This paper presents the wet decapsulation technique based on different ratios of the red fuming nitric acid and concentrated sulfuric acid. Quality of post-decap part was examined using reduction in the wire diameter and changes in ball shear strength. Reduction in wire diameter was monitored with the scanning electron microscopy (SEM), and shear strength was measured using a DAGE2400 shear tester. These tests were performed on the PEMs molded with different EMCs, wire diameters, and pad thickness to cover process as well as geometric variability. Artificial neural network with Bayesian regularization-based model has been developed correlating the decapsulation process parameters with the post-decap wire diameter reduction and shear strength of the wirebond. Stepwise regression was used to identify the significant variables that affect the decap process. The influential variables were then used to develop a predictive model for prediction of the percent reduction in wire diameter and change in shear strength separately. Models were then validated with the test data set.

Prognostics Health Monitoring (PHM) for Prior Damage Assessment in Electronics Equipment Under Thermo-Mechanical Loads

Methodologies for prognostication and health monitoring (HM) can significantly impact electronic reliability for applications in which even minimal risk of failure may be unbearable. Presently, HM approaches such as the built-in self-test are based on reactive failure diagnostics and unable to determine residual-life (RL) or estimate residual-reliability. Prognostics health-monitoring (PHM) approach presented in this paper is different from state-of-art diagnostics and resides in the prefailure-space of the electronic system, in which no macro-indicators such as cracks or delamination exist. Applications for the presented PHM framework include, consumer and defense applications such as automotive safety systems including front and rear impact protection systems, chassis-control systems, x-by-wire systems, and defense applications such as avionics systems, naval electronic warfare systems. The presented PHM methodologies enable the estimation of prior damage in deployed electronics by the interrogation of the system state for systems in which the prior stress-history may be unknown or unavailable. The primary focus is on thermo-mechanical stresses. The presented methodologies will trigger repair or replacement, significantly prior to failure. The approach involves the use of condition monitoring devices which can be interrogated for damage proxies at finite time-intervals. The system's residual life is computed based on residual-life computation algorithms. Previously, we have developed several leading indicators of failure. In this paper, a mathematical approach has been presented to calculate the prior damage in electronics subjected to cyclic and isothermal thermo-mechanical loads. Electronic components operating in a harsh environment may be subjected to both temperature variations in addition to thermal aging during use-life. Data have been collected for leading indicators of failure for 95.5Sn4Ag0.5Cu first-level interconnects under both single and sequential applications of cyclic and isothermal thermo-mechanical loads. Methodology for the determination of prior damage history has been presented using non-linear least-squares method based on interrogation techniques. The methodology presented used the Levenberg-Marquardt Algorithm. The test vehicle includes various area-array packaging architectures soldered on immersion Ag finish, subjected to thermal cycling in the range of -40 οC to 125 οC and isothermal aging at 125 οC.

Design, assembly and reliability of large die and fine-pitch Cu/low- k flip chip package

This paper reports the design, assembly and reliability assessment of 21 × 21 mm 2 Cu/low- k flip chip (65 nm node) with 150 μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low- k layers, Metal Redistribution Layer (RDL) and Polymer Encapsulated Dicing Lane (PEDL) are applied to the Cu/low- k wafer. Lead-free Sn2.5Ag, high-lead Pb5Sn and Cu-post/Sn37Pb bumps are evaluated as the first-level interconnects. It is found that the flip chip assembly of high-lead bumped test vehicle requires the right choice of flux and good alignment between the high-lead solder bumps and substrate pre-solder alloy to ensure proper solder bump and substrate pre-solder alloy wetting. Joint Electron Device Engineering Council (JEDEC) standard reliability is performed on the test vehicle with different first-level interconnects, underfill materials and PEDL. By integrating PEDL to the Cu/low- k chip, the reliability performance of the flip chip package has been improved by almost two times. This paper has demonstrated Moisture Sensitivity Test-Level 2 (MST-L2) qualified large die and fine-pitch Cu/low- k flip chip package. The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/low- k generations.

Underfill Induced Tensile Strain Ratcheting and its Effect on Flip Chip Solder Bump Fatigue

The effects of low Tg underfill material on the reliability of high-Pb first level interconnects were assessed through elastic-plastic finite element modeling and inspection of failure sites at the first-level interconnect. Temperature-dependent changes in specific underfill parameters (elastic modulus and coefficient of thermal expansion) induced a primary tensile stress within the solder bump. The presence and magnitude of this tensile stress were highly dependent upon the maximum and minimum temperature of exposure. Under certain specific thermal conditions, a form of tensile ratcheting was identified through finite element modeling. The application of tensile stress was found to induce a change in degradation behavior and rates relative to the nominal shear stress state (see Figure). This effectively eliminated distance-to-neutral point as a predictor of first-level interconnects performance and required the development of new models to predict solder bump behavior. A discussion on this transformation in stress states and the potential influence on changes in part qualification procedures are provided.

Effects of Glue on the Bend Performance of Flip Chip Packages

To combat reliability margin loss in ball grid array (BGA) packages specifically in mechanical shock and vibration testing, companies are exploring the possibility of using glue and complete underfill to mitigate risk to second-level interconnects (SLI). Though glue has been demonstrated to have a positive influence on SLI reliability margin, it can have adverse affects on the rest of the package such as substrate or first-level interconnects (FLI). This paper explains details on how glue modulates the overall reliability of the package. Finite-element modeling (FEM) along with low strain rate bend tests was done to prove the effect of glue on solder joint reliability. Further, shock testing was done to demonstrate how the glue modulates the shock performance. The improvement in SLI reliability was highly dependent on the choice of glue.

Materials Technology for Environmentally Green Micro Electronic Packagin

Intel has been continuously striving to provide environmentally green micro-electronic packaging solutions for high-density interconnect (HDI) product applications. The environmentally green initiative consisted of providing lead-free (Pb-free) packaging materials solutions as well the enabling of halogen-free (HF) substrates technology to eliminate the use of brominated flame retardants. This paper discusses the challenges overcome by Intel to deliver on both aspects of environmentally green packaging. Although Intel’s efforts to enable Pb-free and HF-compliant packaging solutions have been wide-ranging, the scope of this paper is limited to discussing the key technology development challenges faced in transitioning to Pb-free materials in first-level interconnects (FLI), second-level interconnects (2LI), solder thermal interface materials (STIM) applications, and halogen-free (HF) substrate materials. The transition to Pb-free micro-electronic packaging materials and HF substrate technology required a paradigm shift in the industry, needing extensive benchmarking initiatives and sharing cross-technology learnings across the industry and academia. The delivery of Pb-free packaging solutions across FLI, 2LI, and STIM applications as well as HF substrate technology has strongly reinforced Intel’s One Generation Ahead (OGA) philosophy in micro-electronic packaging.

Solder Joint Reliability in Electronics Under Shock and Vibration Using Explicit Finite-Element Submodeling

Modeling approaches for first-level solder interconnects in shock and drop of electronics assemblies have been developed without any assumptions of geometric symmetry or loading symmetry. The problem involves multiple scales from macroscale transient-dynamics of electronic assembly to microstructural damage history of interconnects. Previous modeling approaches include, solid-to-solid submodeling using a half test PCB board, shell-to-solid submodeling technique using a quarter-symmetry model. Inclusion of model symmetry in state-of-the-art models saves computational time but targets primarily symmetric mode shapes. The modeling approach proposed in this paper enables prediction of both symmetric and antisymmetric modes, which may dominate an actual drop-event. Approaches investigated include smeared property models, Timoshenko-beam element models, explicit submodels, and continuum-shell models. Transient dynamic behavior of the board assemblies in free and JEDEC drop has been measured using high-speed strain and displacement measurements. Model predictions have been correlated with experimental data

Rigorous electromagnetic modeling of chip-to-package (first-level) interconnections

A methodology is presented for the rigorous electromagnetic analysis of pulse transmission through first-level interconnects. The methodology combines a full-wave, vectorial, time-dependent Maxwell's equations solver with SPICE circuit models for the nonlinear drivers, to facilitate the accurate modeling of the electromagnetic phenomena occurring at the chip-to-package interface. Comparisons of the results obtained using this method with others calculated using SPICE simulations are used to validate the method and demonstrate its application in the electromagnetic modeling of high-speed packaging structures. >