First-level Interconnect Research Articles

Numerical Analysis of Narrow-gap Underfill Flow in the Flip-chip Process Using the Lattice Boltzmann Method

Flip-chip packaging is a first-level interconnect technology, and to predict its melt front of capillary driven underfill analytical models have been made. Using the Analytical models, prediction of the melt front can be efficiently done, however it is difficult to reflect the flow resistance resulting from complex solder bump arrangement. Therefore, 3D numerical analysis is required. In this study, Lattice Boltzmann method (LBM) is used for observing the micro void generation that occurs in a underfill process with a height of several tens of microns. LBM statistically expresses the motion of the molecule, to solve the mass transfer of the microscale. In particular, LBM has strengths in multiphase flow analysis of several microscales that cannot be solved by continuum assumption. In this paper, underfill process of several tens of micro scales, which was not covered in previous 3D numerical analysis studies, was simulated using LBM. The improvement of the new LBM model, which more accurately simulates the resistance due to pressure by considering collisions between air and molten mold molecules, is introduced. With the hydraulic diameter greatly reduced due to the narrow gap, it is observed how the solder bump pitch affects the micro void generation. And it is observed whether the air ventilation could change significantly according to the ambient pressure.

Defluxing of Copper Pillar Bumped Flip Chips

Flip-chip technology has become increasingly prevalent within the electronics industry due to its lower cost, increased package density, improved performance while maintaining or improving circuit reliability, and increased I/O density. This technology is a method for interconnecting semiconductor devices such as IC chips and MEMS to external circuitry with solder bumps that have been deposited onto the chip pads. However, solder bump technology has proven to be problematic below 125µm pitch as it is challenging to manufacture and assemble. As pitch is reduced, both standoff height and joint reliability decrease, and the risk of shorts are increased. Given this, traditional solder bumps are being replaced by copper pillar technology. Used as first-level interconnect, copper pillar technology is increasing in popularity. Copper pillar technology has been documented to be efficient to pitches of 80 µm and appears to be promising down to pitches of 40µm. Along with reduced pitches, copper pillar brings several other benefits, including improved electrical performance. This technology is becoming popular since it allows for smaller devices, greater control of standoff height and reduces the number of package substrate layers which reduces cost. Devices utilizing copper pillar technology have more interconnects per surface area resulting in tighter pitch and lower standoffs heights. As standoff height reduces, flux residues have less area to outgas during reflow. For that reason, there is a critical need to investigate the conditions that would be required to successfully remove flux residues to ensure the functionality and reliability of the final product. Flux residues can affect reliability, especially with respect to underfill in two different ways. Firstly, if present on the solder bump, substrate or die, thin films of flux residue can significantly reduce interfacial adhesion between the underfill and the surfaces. Once the underfilled device is stressed by thermal shock, humidity or other factors, the underfill delaminates from the surface, and a gap can be detected using acoustic microscopy. Secondly, fluxes can affect reliability by physically impeding the flow of underfill material. Flux residue buildup in the gap between bumps or between the die and the substrate can narrow the gap to a point where the underfill cannot flow or the edges flow faster, encapsulating air and creating a void. To ensure a void-free underfill, homogenous wetting of the underfill must occur on all surfaces. If wetting is not homogeneous, voids in the uncured underfill may translate into reliability problems later. The study involved using straight DI-water and novel low-concentration alkaline cleaning agent on copper pillar bumped flip chips. The challenge was to effectively clean flux residues underneath these components. The outcome of this study could provide a benchmark for conducting further studies involving bump pitch lower than 15 µm and denser packages including 2.5Ds and 3Ds. The cleaning assessment methodologies employed analytical/functional testing including FTIR, Ion Chromatography, SEM/EDX, Thermal Cycling (TC) Test, Underfill Test, High Temp Storage Life (HTSL) Test and Moisture Sensitivity Level 3 (MSL-3) Testing.

Comparative Study on Power Module Architectures for Modularity and Scalability

Abstract Silicon carbide (SiC) wide bandgap power electronics are being applied in hybrid electric vehicle (HEV) and electrical vehicles (EV). The Department of Energy (DOE) has set target performance goals for 2025 to promote EV and HEV as a means of carbon emission reduction and long-term sustainability. Challenges include higher expectations on power density, performance, efficiency, thermal management, compactness, cost, and reliability. This study will benchmark state of the art silicon and SiC technologies. Power modules used in commercial traction inverters are analyzed for their within-package first-level interconnect methods, module architecture, and integration with cooling structure. A few power module package architectures from both industry-adopted standards and proposed patented technologies are compared in modularity and scalability for integration into inverters. The current trends of power module architectures and their integration into inverter are also discussed. The development of an eco-system to support the wide bandgap semiconductors-based power electronics is highlighted as an ongoing challenge.

Transforming Electronic Interconnect

From nanometers at the transistor level to 100's of microns at the ball grid array (BGA) connections, electronic interconnect of semiconductors spans orders of magnitude as it forms the central nervous system of today's advanced electronic products. Tectonic shifts are currently underway within the industries providing electronic interconnect. Traditional supply chain boundaries produce back end of line (BEOL) structures within wafer foundries ranging from 10's of nanometers to 10's of microns. First-level interconnect, or packaging, the classical purvey of semiconductor assembly and test services (SATS) providers operates in 10's to 100's of microns. Second-level interconnect, or board level assembly, historically rests with electronic manufacturing systems (EMS) providers measuring their work in 100's of microns and above. The transformation underway in electronic interconnect will redefine historical supply chain boundaries as it blurs the lines between foundries, SATS and EMS providers. At the heart of the transformation is ‘fan-out’ technology moving from initial capacities in wafer form to an emerging format of large panels. Breaking through capital cost, reliability and yield concerns with novel solutions will open the door for widespread industry growth of fan-out.

Microstructural Indicators for Prognostication of Copper–Aluminum Wire Bond Reliability Under High-Temperature Storage and Temperature Humidity

Gold wire bonding has been widely used as the first-level interconnect in semiconductor packaging. The increase in the gold price has motivated the industry search for an alternative to the gold wire used in wire bonding and the transition to a copper wire bonding technology. Potential advantages of transition to a Cu–Al wire bond system include low cost of copper wire, lower thermal resistivity, lower electrical resistivity, higher deformation strength, damage during ultrasonic squeeze, and stability compared with gold wire. However, the transition to the copper wire brings along some tradeoffs, including poor corrosion resistance, narrow process window, higher hardness, and potential for cratering. Formation of excessive Cu–Al intermetallics may increase the electrical resistance and reduce the mechanical bonding strength. Current state of the art for studying the Cu–Al system focuses on the accumulation of statistically significant number of failures under accelerated testing. In this paper, a new approach has been developed to identify the occurrence of impending apparently random defect fall-outs and premature failures observed in the Cu–Al wire bond system. The use of intermetallic thickness, composition, and corrosion as a leading indicator of failure for the assessment of the remaining useful life for Cu–Al wire bond interconnects has been studied under exposure to high temperature. Damage in the wire bonds has been studied using an X-ray micro-Computed Tomography (CT). Microstructure evolution was studied under the isothermal aging conditions of 150 °C, 175 °C, and 200 °C until failure. Activation energy was calculated using the growth rate of intermetallic at different temperatures. An effect of temperature and humidity on a Cu–Al wire bond system was studied using the Parr bomb technique at different elevated temperature and humidity conditions (110 °C/100%RH, 120 °C/100%RH, and 130 °C/100%RH), and a failure mechanism was developed. The present methodology uses the evolution of the intermetallic compound thickness and composition in conjunction with the Levenberg–Marquardt algorithm to identify accrued damage in wire bond subjected to thermal aging. The proposed method can be used for a quick assessment of Cu–Al parts to ensure manufactured part consistency through sampling.

Packaging and Non-Hermetic Encapsulation Technology for Flip Chip on Implantable MEMS Devices

We report here a successful demonstration of a flip-chip packaging approach for a microelectromechanical systems (MEMS) device with in-plane movable microelectrodes implanted in a rodent brain. The flip-chip processes were carried out using a custom-made apparatus that was capable of the following: 1) creating Ag epoxy microbumps for first-level interconnect; 2) aligning the die and the glass substrate; and 3) creating non-hermetic encapsulation (NHE). The completed flip-chip package had an assembled weight of only 0.5 g significantly less than the previously designed wire-bonded package of 4.5 g. The resistance of the Ag bumps was found to be negligible. The MEMS micro-electrodes were successfully tested for its mechanical movement with microactuators generating forces of 450 μN with a displacement resolution of 8.8 μm/step. An NHE on the front edge of the package was created by patterns of hydrophobic silicone microstructures to prevent contamination from cerebrospinal fluid while simultaneously allowing the microelectrodes to move in and out of the package boundary. The breakdown pressure of the NHE was found to be 80 cm of water, which is significantly (4.5-11 times) larger than normal human intracranial pressures. Bench top tests and in vivo tests of the MEMS flip-chip packages for up to 75 days showed reliable NHE for potential long-term implantation.

Novel First-Level Interconnect Techniques for Flip Chip on MEMS Devices

Flip-chip packaging is desirable for microelectro-mechanical systems (MEMS) devices because it reduces the overall package size and allows scaling up the number of MEMS chips through 3-D stacks. In this report, we demonstrate three novel techniques to create first-level interconnect (FLI) on MEMS: 1) Dip and attach technology for Ag epoxy; 2) Dispense technology for solder paste; 3) Dispense, pull, and attach technology (DPAT) for solder paste. The above techniques required no additional microfabrication steps, produced no visible surface contamination on the MEMS active structures, and generated high-aspect-ratio interconnects. The developed FLIs were successfully tested on MEMS moveable microelectrodes microfabricated by SUMMiTVTM process producing no apparent detrimental effect due to outgassing. The bumping processes were successfully applied on Al-deposited bond pads of 100 μm × 100 μm with an average bump height of 101.3 μm for Ag and 184.8 μm for solder (63Sn, 37Pb). DPAT for solder paste produced bumps with the aspect ratio of 1.8 or more. The average shear strengths of Ag and solder bumps were 78 MPa and 689 kPa, respectively. The electrical test on Ag bumps at 794 A/cm2 demonstrated reliable electrical interconnects with negligible resistance. These scalable FLI technologies are potentially useful for MEMS flip-chip packaging and 3-D stacking.

The Application of Two-Dimensional X-ray Hot Stage in Flip Chip Package Failure Analysis

Advancement of silicon and packaging technologies toward lower power and higher functionality requires better understanding between materials and process interactions. This paper illustrates the applications of 2-D X-ray metrology incorporated with a hot stage system for the first time in the literature, which allows one to simulate heating profiles of up to 300°C and observe the behavior of materials in situ within the packages. Three case studies are discussed: 1) segregation of metal particles in the next-generation thermal interface material, leading to corner thermal resistance (Rjc) degradation; (2) first level interconnect (FLI) solder bump bridging during chip attach of a large die server package with high substrate die area warpage in which limits of the die area substrate warpage need to be set in order to avoid FLI solder bump bridging during the chip attach solder reflow process; and 3) second level interconnect solder joint bridging at the surface mounting process of a large die package attached with an integrated heat spreader. By being able to study failures in situ at high temperatures, a new dimension to the package failure analysis is presented in this paper.

Underfill Induced Tensile Strain Ratcheting and its Effect on Flip Chip Solder Bump Fatigue

The effects of low Tg underfill material on the reliability of high-Pb first level interconnects were assessed through elastic-plastic finite element modeling and inspection of failure sites at the first-level interconnect. Temperature-dependent changes in specific underfill parameters (elastic modulus and coefficient of thermal expansion) induced a primary tensile stress within the solder bump. The presence and magnitude of this tensile stress were highly dependent upon the maximum and minimum temperature of exposure. Under certain specific thermal conditions, a form of tensile ratcheting was identified through finite element modeling. The application of tensile stress was found to induce a change in degradation behavior and rates relative to the nominal shear stress state (see Figure). This effectively eliminated distance-to-neutral point as a predictor of first-level interconnects performance and required the development of new models to predict solder bump behavior. A discussion on this transformation in stress states and the potential influence on changes in part qualification procedures are provided.

The Microelectronic Wire Bond: Past, Present, and Future

Since its very inception, the microelectronic wire bond has been the dominate form of first-level interconnection (chip to package or substrate). Wire bonds account for over 80% of first-level chip interconnections made by the microelectronic industry each year. Wire bonding is reliable, flexible, and low cost when compared to other forms of first-level interconnections. In this article a brief discussion of wire bonding is presented along with bond formation fundamentals. Aspects of wire bond reliability will be explored in conjunction with methods of wire bond testing. Particular attention is given to fine pitch bonding, bonding to stacked die, higher frequency bonding, ball bonding with copper wire, and advanced bond testing methods.

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm times 6.5 mm with 48 spring contacts on a 0.8 mm times 0.65 mm grid array, each spring measuring 400 mum times 100 mum. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone >20 000 hot plate thermal cycles and >1000 oven thermal cycles without failure.

SMT-compatibility of adhesive flip chip on foil interconnections with 40-/spl mu/m pitch

The manufacturing and reliability of a novel type of first-level interconnections is described. Anisotropic conductive and nonconductive adhesives are used to electrically bond flip chip ICs with a pitch of 60 and 40 /spl mu/m to flexible substrates. Analyses cover the initial state of the samples as well as their performance in the JEDEC moisture sensitivity level assessment and subsequent life testing. From the different behavior of the two types of adhesives a failure mechanism issues for the reflow-soldering test.

Processor subsystem interconnect architecture for a large symmetric multiprocessing system

Integral to the significant capacity growth of the IBM eServerTM z990 (the eighth-generation zSeries® CMOS-based server) from its predecessor z900 system is the interconnect architecture, which tightly couples 48 customer CPUs in the system. A major attribute of this architecture is a new swap feature which improves zSeries system availability for customers by permitting the substitution or addition of a field-replaceable unit (FRU) in the processor subsystem without requiring the system to be powered down. The novel two-level interconnect architecture contains a distributed switch which connects up to four processor-memory nodes in book packages. The book packages, which are also FRUs, are connected in a dual concentric ring topology at the second-level (L2) interconnect. This architecture also contains an integrated 32-MB L2 cache and central switch connecting up to eight dual-core processor chips in a star topology at the first-level interconnect inside one of these nodes. This paper describes the bus protocol on the second-level interconnect, the cache coherency management throughout the storage hierarchy, and the ring topology reconfiguration for hot swap. Also described is a memory, power management scheme to support the power demand from the 48 CPUs and up to 256 GB of memory.

Extremely low-noise performance of GaAs MESFETs with wide-head T-shaped gate

Fully ion-implanted low-noise GaAs MESFETs with a 0.11-/spl mu/m Au/WSiN T-shaped gate have been successfully developed for applications in monolithic microwave and millimeter-wave integrated circuits (MMICs). In order to reduce the gate resistance, a wide Au gate head made of a first-level interconnect is employed. As the wide gate head results in parasitic capacitance, the relation between the gate head length (L/sub h/) and the device performance is examined. The gate resistance is also precisely calculated using the cold FET technique and Mahon and Anhold's method. A current gain cutoff frequency (f/sub T/) and a maximum stable gain (MSG) decrease monotonously as L/sub h/ increases on account of parasitic capacitance. However, the device with L/sub h/ of 1.0 /spl mu/m, which has lower gate resistance than 1.0 /spl Omega/, exhibits a noise figure of 0.78 dB with an associated gain of 8.7 dB at an operating frequency of 26 GHz. The measured noise figure is comparable to that of GaAs-based HEMT's.

Rigorous electromagnetic modeling of chip-to-package (first-level) interconnections

A methodology is presented for the rigorous electromagnetic analysis of pulse transmission through first-level interconnects. The methodology combines a full-wave, vectorial, time-dependent Maxwell's equations solver with SPICE circuit models for the nonlinear drivers, to facilitate the accurate modeling of the electromagnetic phenomena occurring at the chip-to-package interface. Comparisons of the results obtained using this method with others calculated using SPICE simulations are used to validate the method and demonstrate its application in the electromagnetic modeling of high-speed packaging structures. >

A novel lossy and dispersive interconnect model for integrated circuit simulation

A method of modeling first-level metal interconnect signal transmission on silicon substrates with arbitrary doping profiles has been developed. The novel interconnect model includes the effects of signal attenuation and signal dispersion encountered in fast transient waveform propagation. Analytical modeling and PISCES device simulation are used for interconnect model development. SPICE simulation of the model shows good agreement with measurements.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Application of MoSi/sub 2/ to the Double-Level Interconnections of I/sup 2/L Circuits

A new MoSi/sub 2/-CVD-Al double-level interconnection system is developed to obtain a high packing density in I/sup 2/L circuits. Taking advantage of MoSi/sub 2/, a fine pattern consisting of a Iinewidth of 2.5 /spl mu/m aid a spacing of 1 /spl mu/m is achieved for the first-level interconnections. This new system has a higher reliability than the normaf Al-CVD-Al structure because of the stability of the MoSi2 surface. The fundamental properties of 1/sup2/L gates with MoSi2 interconnections, namely, gain, propagation delay time, and toggle frequency of a T flip-flop, are measured. At practical injector currents, they show nearly the same values as with Al interconnectiorm The resistance effects of MoSi/sub 2/ interconnections are calculated with regard to the unbalance of the injector currents and increase of the propagation delay time. The calculations show that these effects can be ignored at an injector current of 1 /spl mu/A/gate. At higher injector currents, the MoSi/sub 2/ interconnection resistance must be taken into account in I/sup 2/L pattern layout.

Application of MoSi2to the double-level interconnections of I2L circuits

A new MoSi 2 -CVD-Al double-level interconnection system is developed to obtain a high packing density in I2L circuits. Taking advantage of MoSi 2 , a fine pattern consisting of a linewidth of 2.5 µm and a spacing of 1 µm is achieved for the first-level interconnections. This new system has a higher reliability than the normal Al-CVD-Al structure because of the stability of the MoSi 2 surface. The fundamental properties of I2L gates with MoSi 2 interconnections, namely, gain, propagation delay time, and toggle frequency of a T flip-flop, are measured. At practical injector currents, they show nearly the same values as with Al interconnections. The resistance effects of MoSi 2 interconnections are calculated with regard to the unbalance of the injector currents and increase of the propagation delay time. The calculations show that these effects can be ignored at an injector current of 1 µA/gate. At higher injector currents, the MoSi 2 interconnection resistance must be taken into account in I2L pattern layout.