FIR Taps Research Articles

A Simplified Constrained Bayesian Optimization Approach to Optimize the Tx Equalization in SerDes Channels

Design of high-speed channels has become increasingly more complicated. Due to the eye diagram closure at higher speeds, designers use Tx equalization by placing an FIR filter at Tx. Assigning the FIR tap values can be time consuming and require domain expertise since it can require sweeping hundreds or more combinations of tap values. Therefore, in this paper we propose a machine learning optimization approach to find the FIR tap values which result in the largest eye opening. Conventional optimization techniques may not be applicable in this context since specifications of the channel can require a constraint which is sum of the absolute value of the FIR taps needs to be equal to 1. Therefore, we have developed a simplified constrained Bayesian optimization approach that can automate this process and expedite calculation of the FIR tap values without requiring domain expertise. Numerical examples are provided to show efficiency of the proposed approach and compare its performance with Bayesian optimization and Genetic algorithm for this problem.

Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics

Optimization problem formulation for semi-digital FIR digital-to-analog converter (SDFIR DAC) is investigated in this work. Magnitude and energy metrics with variable coefficient precision are defined for cascaded digital varSigma varDelta modulators, semi-digital FIR filter, and Sinc roll-off frequency response of the DAC. A set of analog metrics as hardware cost is also defined to be included in SDFIR DAC optimization problem formulation. It is shown in this work, that hardware cost of the SDFIR DAC, can be significantly reduced by introducing flexible coefficient precision while the SDFIR DAC is not over designed either. Different use-cases are selected to demonstrate the optimization problem formulations. A combination of magnitude metric, energy metric, coefficient precision and analog metrics are used in different use cases of optimization problem formulation and solved to find out the optimum set of analog FIR taps. A new method with introducing the variable coefficient precision in optimization procedure was proposed to avoid non-convex optimization problems. It was shown that up to 22% in the total number of unit elements of the SDFIR filter can be saved when targeting the analog metric as the optimization objective subject to magnitude constraint in pass-band and stop-band.

On-Chip Two-Tone Synthesizer Based on a Mixing-FIR Architecture

A low-distortion current-steering two-tone sinusoidal signal synthesizer based on a mixing-finite impulse response (FIR) architecture is proposed. The proposed robust synthesizer adopts only digital blocks. It implements a two-stage cascade FIR harmonic cancellation technique that generates a single tone quasi-sinusoidal waveform and suppress the odd-order harmonics up to the 21st order. Differential-mode circuitry and a 50% duty cycle clock are also utilized to cancel the even-order harmonics. The single-tone signal is further up-converted to the desired local oscillator (LO) frequency band, thereby producing the desired two-tone sinusoidal signals. The proposed synthesizer contains a current mirror array implementing the FIR tap coefficients. Accuracy is enhanced using dynamic element matching. The other building blocks consist of a 24-phase clock generator, a current combiner, and a passive mixer with bootstrapped MOS switches. This two-tone synthesizer can be used to conduct a linearity built-in self-test. It is fabricated in 130-nm standard CMOS technology, occupying a 0.056-mm2 silicon area. Measurement shows better than −68 dBc third-order intermodulation (IM3) below 480-MHz LO frequency without calibration. For the LO frequency <76.8 MHz and the two-tone difference <2 MHz, an IM3 better than −75 dBc can be achieved. The imbalance between the two-tone amplitudes is measured <0.1 dB across the whole frequency range from dc to 1 GHz.

Active field control (AFC) -electro-acoustic enhancement system using acoustical feedback control

AFC is an electro-acoustic enhancement system using FIR filters to optimize auditory impressions, such as liveness, loudness, and spaciousness. This system has been under development at Yamaha Corporation for more than 15 years and has been installed in approximately 50 venues in Japan to date. AFC utilizes feedback control techniques for recreation of reverberation from the physical reverberation of the room. In order to prevent coloration problems caused by a closed loop condition, two types of time-varying control techniques are implemented in the AFC system to ensure smooth loop gain and a sufficient margin in frequency characteristics to prevent instability. Those are: (a) EMR (electric microphone rotator) -smoothing frequency responses between microphones and speakers by changing the combinations of inputs and outputs periodically; (b) fluctuating-FIR -smoothing frequency responses of FIR filters and preventing coloration problems caused by fixed FIR filters, by moving each FIR tap periodically on time axis with a different phase and time period. In this paper, these techniques are summarized. A block diagram of AFC using new equipment named AFC1, which has been developed at Yamaha Corporation and released recently in the US, is also presented.

Performance limits in subband beamforming

This paper analyzes subband beamforming schemes mainly aimed at speech enhancement and acoustic echo suppression applications such as hands-free telephony for both mobile and office environments, Internet telephony and video conferencing. Analytical descriptions of both causal finite-length and noncausal infinite-length subband microphone array structures are given. More specifically, this paper compares finite Wiener filter performance with the noncausal Wiener solution, giving a comprehensive theoretical suppression limit. It is shown that even short filters will yield a good approximation of the infinite solution, provided that the element spacing and temporal sampling is matched to the frequency band of interest. Typically, 10-20 FIR taps are sufficient in each subband.

Equalizer architecture tradeoffs for magnetic recording channels

The bit error rate (BER) performance of various equalizer architectures consisting of a continuous time filter (CTF) and analog adaptive FIR filter are evaluated. Among the CTFs examined are the 4th and 6th order Butterworth, and 7th order equiripple linear phase filter. FIR filters of length 3 to 10 are considered. It is shown that, with adequate optimization of the CTF boost and bandwidth, the performance of the equalizers is relatively insensitive to the number of FIR taps or the CTF type. However it is also shown that choosing a very small number of FIR taps is impractical because the space of CTF boost and bandwidth settings yielding close to optimum performance becomes extremely small.

Realisation and implementation of a sigma-delta bitstream FIR filter

Sigma-delta signal processing or SDSP has been proposed as a method for reducing system costs by eliminating the decoding of a ΣΔ bitstream prior to processing. The design problems inherent in this are examined, and the tradeoff to the more conventional approach through the study of a bitstream FIR filter is analysed. It is found that the system imposes particular constraints on the design of the digital ΣΔ modulator used to remodulate the FIR filter output. Also, the system cost of the SDSP FIR filter is less than that for the decoded PCM filter below a certain number of taps, currently estimated as at least 80. The design of a VLSI demonstrator that implements 16 FIR taps and remodulator, has 16-bit dynamic range and is cascadable for higher filter orders is also presented.

A high speed, low power PRML read channel device

A complete read channel device using PR-IV signalling and maximum likelihood detection is described. Descriptions, simulated performance and measured results of the digital adaptive feedback loops (AGC, FIR tap weights, DFE tap weights, frequency and phase) in the read channel are presented. Analog FIR filter and hash A/D converter performance is presented. The weighted averaging servo demodulation technique used in the device is described and compared to integration. This monolithic CMOS device consumes less than 0.75 W when reading at 85 Mbps, and occupies a step-and-repeat area of 24.6 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>