FIR Filter Research Articles

Projection-Based Multiple Notch Filtering

A method for multi-frequency notch filtering is described. The approach is based on quadratic programming, which leads to projecting the signal vector onto the orthogonal complement of the subspace spanned by a set of sinusoidal basis vectors, each corresponding to a notch frequency. The projection matrix uses a weighted inner product whose weights are samples of a standard spectral analysis window. An overlap-add method suitable for block processing is also described. The projection-based notch filter (PNF) is compared with linear-phase FIR and IIR multiple notch filters and is found to have improved amplitude and phase distortion.

2-D lossless FIR filter design using synthesis of the paraunitary transfer function matrix

2-D lossless FIR filter design using synthesis of the paraunitary transfer function matrix

An efficient way of identification of protein coding regions of eukaryotic genes using digital FIR filter governed by Ramanujan's Sum

An efficient way of identification of protein coding regions of eukaryotic genes using digital FIR filter governed by Ramanujan's Sum

A Sensor-Based Modified FMD Method to Identify Fault Feature for Mechanical Fault Diagnosis of Ship-Borne Antennae

It is necessary to perform condition monitoring and fault identification on ship-borne antennae to ensure navigation safety. However, timely fault identification of key parts in a complicated drivetrain of the ship-borne antenna is still a challenging task since fault features are usually modulated and inevitably submerged by heavy noise. Therefore, a new adaptive feature extraction method based on Feature Mode Decomposition (FMD) is proposed in this paper for diagnostic purpose. First, scale transform is applied on the spectrum of the monitoring signal to determine the parameters of FMD, including the number of FIR filters, the location of each filter and the order of the filter bank. Second, a modified feature mode decomposition (MFMD) algorithm is proposed to adaptively extract mono-component modes and combine similar modes for weak feature enhancement. Finally, the combined modes are analyzed for mechanical fault identification based on Hilbert demodulation. Two application cases show that the proposed method owns superior performance during feature extraction, compared with the traditional methods.

High-Speed DSP Pipelining and Retiming techniques for Distributed-Arithmetic RNS-based FIR Filter Design

Digital FIR Filters plays a major role in many signal processing applications. Generally, these filters are designed with multipliers and adders to find the filter output. This paper acquaints how to reduce the complexity of higher order FIR filter by using performance optimization techniques like retiming and pipelining. The filter’s throughput, energy efficiency, and latency, as well as the complexity of its technology, all need to be improved. By adopting pipelining technique, the arithmetic processes of addition and multiplication are separated. The break addition procedure is retimed. The architecture of Pipelining and Retiming with m-tap filters and n-bit word lengths were designed. The smallest delay achieved by the proposed distributed arithmetic-based FIR Filter with pipelining was 2.564ns for a 4tap implementation receiving an 8bit input, while the largest delay achieved was 56.04ns for a 64-tap implementation receiving a 32-bit word length. Delays as low as 0.68ns for a 4-tap implementation receiving an 8-bit input and as high as 4.53ns for a 64tap implementation receiving a 32bit word length have been achieved by using the suggested distributed arithmetic-based FIR Filter with retiming approach. Delay has been reduced by 73.2% for 4tap with 8bit input and by 91.9% for 64tap with 32bit word length compared to the pipelining approach.

Design and Implementation of an Area and Power-efficient Reconfigurable Hearing Aid using Interpolated Sub-band Distribution Technique

A hearing aid is a compensatory device that helps in overcoming various hearing disabilities. Since different people possess different hearing problems and the requirement gets changed over time, it is necessary to design a reconfigurable hearing aid which is generic in nature such that it supports various hearing disabilities without modifying the hardware components. The objective of the paper is to implement a reconfigurable digital hearing aid which is hardware efficient and it is auto-adaptable to disabilities ranging from mild to severe intensities. Since multipliers and LUTs are power hungry elements, we have proposed a design which is multiplier less and LUT-less DA Architecture. The prototype filter is a FIR filter which is designed using LUT-less Distributed Arithmetic Algorithm that saves 64% of logic elements & memory and 76% of power utilization. As it is a multiplier-less as well as LUT- less architecture, hence this can be claimed to be area and power efficient design. The delays and matching errors are within the standard limits which are accepted globally. The input audio spectrum is divided into three regions and for each region there are four different filter banks are proposed using interpolated sub-bands distribution. Xilinx System Generator is used to implement the proposed design. The proposed design requires least manual configuration for selection of filter banks for audiogram matching which also minimizes the trial-anderror method to establish the best match with the person’s audiogram.

Design of Digital Low Pass FIR Filter Using Hybrid Particle Swarm – Grey Wolf Optimization Algorithm

In this study, digital low-pass FIR filter is designed using Hybrid Particle Swarm – Grey Wolf Optimization Algorithm (HPSGWO). The purpose of digital FIR filter design with HPSGWO is to optimized filter coefficients that are closest to the characteristics of the ideal filter. The obtained results are compared with PSO, and GWO which were previously used for FIR filters design in the literature. According to the obtained results, HPSGWO has better filter response and less stop band ripple than other methods.

Filtered-error RLS for self-tuning disturbance feedforward control with application to a multi-axis vibration isolator

High performance vibration isolation can be realized by disturbance feedforward control with a self-tuning generalized FIR filter and residual noise shaping. For this application, filtered-error recursive least squares (FeRLS) self-tuning is proposed in a multi-input multi-output context. In comparison to filtered-error least mean squares (FeLMS), FeRLS achieves faster and more uniform parameter convergence without the need of pre-whitening. Efficient implementation is realized by exploiting sparsity in the involved matrices. Feasibility of implementation is demonstrated on a multi-axis hard-mount vibration isolation setup. Experimental results show the better parameter convergence and the ability to track changes in the floor vibration spectrum. A reduction of the transmissibility of floor vibrations up to 40 dB in the frequency range of interest is obtained, reducing vibration power by 90–94% in the 1–300 Hz frequency band in multiple directions.

Design of Power and Area Efficient Carry Skip Adder and FIR filter Implementation

Adders are used in processing units such as Arithmetic and Logic Units (ALUs) as an essential building block, and in many blocks of microprocessor chips critical path, adders occupy an important place. Hence reducing power, area and increasing the speed of adders are significantly important. This paper proposes a modified structure of Carry Skip Adder (CSKA) with a reduction in consumption of power and area without affecting the speed when compared with the conventional adder structures. In order to get better effectiveness of the modified CSKA by including concatenation, incrementation schemes, and variable latency for the proposed hybrid structure, which reduces the power utilized without affecting the operating speed of the adder. The modified structure in CSKA helps in improving the slack time, which further reduces the voltage with the parallel structure. Experimental results show that the 32-bit implementation of the proposed adder has a significant power reduction of 42% and 38.3%, area reduction of 27%, and 18.3% with respect to Conventional CSKA and CI CSKA adder with a little over ahead in delay. The proposed adder is used to implement a 5-tap FIR filter which shows a significant reduction in power consumption and area.

A Frequency Measurement Method for Protection of Smart Circuit-breaker

The application scale of new energy such as wind energy and solar energy in China is increasingly large. One of the characteristics of these energy sources is instability. Circuit-breakers play an important role protection in distributing these energy sources. Aiming at a new type of smart circuit-breaker architecture, this paper proposes a frequency measurement method for protection function, that is, the waveform sample value of high precision and high sample rate output by the DMA of the metering chip. The FIR filter is used to eliminate harmonic interference, impulse interference, etc of sample value. The frequency value is calculated by the interval duration between the two cross-zero points of sample value, and the simulation process, as well as the results, are given.

Power Minimization by Designing Novel Architecture for Multimodal Biometric System

Abstract: The reduction of power, area, and delay parameters are increasing as the range of sophistication of applications in VLSI circuit designs. Adders and multipliers play a vital role in VLSI circuit designs to minimize the power consumed by the circuit. The Finite Impulse Response Filter is widely used in Digital Signal Processing Applications, such as speech processing, loudspeaker equalization, echo cancellation, noise cancellation, arithmetic computations and, image-processing applications. In FIR filter, the adders and multipliers are the important components to reduce the power, delay and area. Therefore, this proposed method faced with more constraints: as minimal power as possible. This work proposes a design of low power Finite Impulse Response Filter using Carry Skip Adder.The recent electronics industry uses digital filters for various real time applications. A novel VLSI architecture is designed by using ALU based FIR filters for biometric system. Where in ALU includes adders and multipliers, comparing different adders for there better performance with respect to power and identifying carry skip adder will consume less power compared to other adders. power consumption of overall architecture by including carry skip adder is very less and we can use this same adder for multimodal architecture also.

Design of special structure FIR filters and two-channel quadrature mirror FIR filter bank with sparse coefficients

The sparse design of special structure FIR filters (e.g., matrix-decomposition based FIR filter and frequency response mask based FIR filter) or special purpose FIR filters (e.g., the prototype FIR filter in the two-channel quadrature mirror FIR filter bank) is scarcely addressed previously. In this study, we deal with the sparse design of special structure/purpose FIR filters. A convergent scheme for the sparse design of special structure/purpose FIR filters is proposed. Its technical essence is a convergent scheme for minimizing the ℓk (k=1,2,…,∞) norm of the variable coefficients while the design error satisfying the desired requirement. The basic idea of the proposed scheme, for minimizing the ℓk norm of the variable coefficients, is approximately transforming all the sub-functions in the design error expression into linear ones using Taylor-Series. Thereby, the original non-convex design error turns to be convex. As part of the proposed scheme for the sparse design of special structure/purpose FIR filters, three new criteria of obtaining one more sparse coefficient are proposed. Simulation results validate the effectiveness of the proposed scheme in minimizing the ℓk norm of the variable coefficients and obtaining sparse coefficients in the sparse design of special structure/purpose FIR filters.

Maximum correlation Pearson correlation coefficient deconvolution and its application in fault diagnosis of rolling bearings

Blind deconvolution (BD) has been proved to be an effective tool for recovering periodic impulses from strong background noise signals is widely used for fault diagnosis of bearings and gears. However, the existing BD focus more on improving the quantity and amplitude-frequency characteristics of interested periodic impulses without considering their phase-frequency characteristics and impulse waveform characteristics (attenuation coefficient and oscillation frequency), which results in severe distortion of the reconstructed signal. In this scenario, a new BD method, named maximum correlation Pearson correlation coefficient deconvolution (MCPCCD), is presented in this paper. Firstly, a new objective function is constructed which include two terms: correlation Pearson correlation coefficient (CPC) and signal fidelity term (SFT). CPC is a new norm with strong sensitivity to interested impulse signals, while SFT is a dimensionless error measure similar to RMSE. Then, the optimal FIR filter is obtained by maximizing the objective function of the reconstructed signal. Meanwhile, a new preprocessing step is designed to reduce the requirement of MCPCCD for periodic prior. Finally, the application on simulated and two experimental signals indicates that MCPCCD significantly outperforms the traditional BD method in recovering the periodic impulses.

A Distortionless Anti-Jamming Method Based on STAP for GNSS Receiver

Global Navigation Satellite System (GNSS) receivers often realize anti-jamming capabilities by combining array antennas with space-time adaptive processing (STAP). Unfortunately, in suppressing the interference, basic STAP degrades the GNSS signal. For one thing, additional carrier phase errors and code phase errors to the GNSS signal are introduced; for another, the shape of the cross-correlation function (CCF) will be distorted by STAP, introducing tracking errors when the receiver is in tracking mode. Both of them will eventually cause additional Pseudo-Range (PR) bias, and these problems prevent STAP from being directly applied to high-precision satellite navigation receivers. The paper proposes a novel anti-jamming method based on STAP that solves the above problems. First, the proposed method constructs a symmetric STAP by constraining the STAP coefficients. Subsequently, with the information of the steering vector, a compensation FIR filter is cascaded after the symmetric STAP. This approach ensures that the proposed method introduces only a fixed offset to the code phase and carrier phase, and the order of the STAP completely determines the offset, which can be compensated during PR measurements. Meanwhile, the proposed method maintains the symmetry of the CCF, and the receiver can accurately track the carrier phase and code phase in tracking mode. The effectiveness of the proposed method is validated through simulations, which suggest that, in the worst case, our method does not increase carrier and code phase errors and tracking error at the expense of only a 2.86dB drop in interference suppression performance.

A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS

This article shows the design of a wideband 3-0 sturdy-multi-stage noise-shaping (SMASH) continuous-time (CT) incremental delta–sigma (I- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\Delta \Sigma }$ </tex-math></inline-formula> ) analog-to-digital converter (ADC). The two stages’ quantizers (QTZs) are implemented by a single re-configurable multibit (MB) asynchronous (A)SAR ADC. The digital-to-analog converter (DAC) nonlinearities are suppressed by reconfiguring the asynchronous successive-approximation register (ASAR) ADC from 2 to 5 b, and correspondingly, the DACs dynamically switch from 1.5- to 4-b tri-level outputs within each Nyquist conversion cycle. This results in a DAC-calibration-free MB operation. A two-tap FIR filter is implemented in the feedback DACs to reduce jitter requirements in the initial 1.5-b cycles. Through the design representation, a detailed fundamental comparison between an X-0 SMASH architecture and an X-order single-loop modulator is discussed. This discussion highlights the introduction of an efficient tri-level combination between the MSB and the LSBs of the ASAR QTZ. The resulting SMASH CT I- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\Delta \Sigma }$ </tex-math></inline-formula> modulator was fabricated in 28-nm CMOS technology with an active area of 0.125 mm2. It achieves 97-dB spurious-free dynamic range (SFDR) without calibration, 89-dB dynamic range (DR), and 81.2-dB SNDR in a 1-MHz bandwidth (BW). It consumes 3.6 mW from a single 0.9-V supply. The design shows very good robustness across different tested samples, supply variations, and across temperatures from −20 °C to 80 °C.

Design and Optimization of Fuzzy-Based FIR Filters for Noise Reduction in ECG Signals Using Neural Network

Cardiovascular disease (CVD) has been identified as a threat to human life for decades, with the majority of individuals dying as a result of delayed diagnosis and treatment. An electrocardiogram (ECG) plays a vital role in the prognosis of such an ailment. The presence of noise and artifacts complicates the accurate detection and identification of CVD. As a result, reliable signal recovery tasks necessitate noise removal, which is an inverse problem. The main noises present in electrocardiogram (ECG) signals are EMG noise, electrode motion artifact noise. In this paper, radial basis function (RBF) and multi swarm optimization neural network (MSONN) are used to denoise the ECG signal. The cut-off frequency is calculated using a low-pass filter. By using, fuzzy FIR filtering technique baseline wander noises can be removed. Results show that MOS based approach outperforms existing approaches in terms of accuracy and is observed to be 87% even when the dataset size is small. Further, noises if any exists are also removed by the use of cascaded multiplier less Fuzzy FIR filters

Effects of noise and filtering strategies on the extraction of pulse rate variability from photoplethysmograms

Pulse rate variability (PRV) describes the changes in pulse rate through time, when measured using pulsatile signals such as photoplethysmograms (PPG). PRV has been used as a surrogate of heart rate variability (HRV), but their relationship is not straightforward, both due to physiological differences and to effects of technical aspects on the extraction of PRV information from pulsatile signals such as the PPG. One of the factors that may affect PRV analysis is the presence of noise and the filtering strategy used to pre-process the PPG signal. In this study, the aim was to evaluate the best performing filtering strategy for the extraction of PRV information reliably from noise-contaminated synthetic PPG signals. Time domain, frequency domain and Poincaré plot indices were extracted from PRV trends obtained from the filtered PPG signals and compared against indices measured from a gold-standard simulated PRV function. It was found that PRV information can be reliably extracted from PPG signals filtered using lower low cutoff frequencies and elliptic IIR or equiripple or Parks–McClellan FIR filters, however the filtering parameters depend on the type of noise present in the signal. Moreover, special care should be taken to assess the pNN50 index from contaminated PPG signals, regardless of the type of noise. Future studies should aim to validate these results from real PPG data.

Fusion classification of stroke patients' biosignals by weighted cross-validation-based feature selection (W-CVFS) method

A multi-source information fusion-based disease class classification of stroke patients was implemented to address the low classification accuracy of pure input motion and electromyographic signals. sEMG sensor MYO arm ring and wearable wireless motion sensor Shimmer were used as data acquisition devices. The Butterworth high-pass filter filtering and envelope thresholding method detected the activity segment. Detection and FIR filtering using the window function method remove interference from the motion signal. A weighted cross-validation-based feature selection (W-CVFS) method is proposed for feature fusion selection. The top 10 features selected by the W-CVFS method and all 18 features are input to the deep neural network for training and testing, and the feature classification result of the W-CVFS method is 79.17%, which is better than the existing mRMR method (66.67%) and ILFS method (62.50%). The classificatip9uon accuracy of multi-source information fusion was 95.385%, which was higher than that of a single input motion signal or sEMG. The experiments showed that the proposed method can retain the features that have more influence on the classification results and can improve the classification accuracy of the rehabilitation model for stroke patients.

A Review on Finite Impulse Response and Infinite Impulse Response Filter Combined Circuit

Filters are electronic circuits which used in many applications. Basically filters are circuit of linear type. This is work on the principle of removing the noisy signal, interference in input signal and unwanted distortion from the signal. it is widely used in electronics devices and circuits to improve efficiency related to removing noisy signals and unwanted interference and distortion in noisy signals filters are vital parts of electronics devices various types of filters are found in electronics devices which work on the principle of reducing noise in signals and removed unwanted signals from the channels. In this paper we Review FIR and IIR filters with top level architecture of the combined FIR and IIR filters which used in circuit for remove noise in communication devices and improved efficiency.

Scalable Hardware Efficient Architecture for Parallel FIR Filters with Symmetric Coefficients

Symmetric convolutions can be utilized for potential hardware resource reduction. However, they have not been realized in state-of-the-art transposed block FIR designs. Therefore, we explore the feasibility of symmetric convolution in transposed parallel FIRs and propose a scalable hardware efficient parallel architecture. The proposed design inserts delay elements after multipliers for temporal reuse of intermediate tap products. By doing this, the number of required multipliers can be reduced by half. As a result, we can achieve up to 3.2× and 1.64× area efficiency improvements over the modern transposed block method on reconfigurable and fixed designs, respectively. These results confirm the effectiveness of the proposed STB-FIR architecture for hardware-efficient, high-speed signal processing.