Finite Word Length Effects Research Articles

Performance evaluation of infinite impulse response filter synthesis using parallel-Direct-Ladder form under finiteword-Length effects

Synthesizing a parallel-form IIR filter from a given non-strictly-proper transfer function requires a polynomial long division method, which results in dynamical range problem under finite word-length (FWL) fixed-point implementations. Based on the state-space similarity transformation, in this paper, a synthesis scheme for parallel-form IIR filters is proposed without requiring long division of polynomials operations to reduce dynamical range problems for obtaining parallelized first or second-order sections either in direct-form or coupled-form. The main advantage of the proposed scheme is that the parallelized IIR filter can be synthesized based on state-space normal-form similarity transformation from any digital filter transfer functions. In addition, the proposed two modified coupled-form filters based on the parallelized IIR filter have benefits of less computational consumption and zero-input limit-cycle free, especially for modified second-order coupled forms in contrast with the conventional coupled-form biquad. Finally, two numerical examples are performed to illustrate the effectiveness of the proposed scheme.

A unified approach for digital realization of fractional order operator in delta domain

The fractional order operator (s?a,0 < a <1) plays the pivotal role for the realization of fractional orders systems (FOS). For the realization of the FOS, fractional order operator (FOO) needs to be realized either in discrete or continuous time domain. Discrete time rational approximation of FOO in the z -domain fails to provide meaningful information at fast sampling interval. Moreover, z domain rational transfer function becomes highly sensitive with respect to its coefficients variation resulting to the poor finite word length effects for digital realization. In the other hand delta operator parameterized system allows to develop unification of continuous and discrete time formulations leading to the development of a unified framework for digital realization at fast sampling interval. The discrete time approximation of the FOO in delta domain is found to be robust to its coefficient variation in comparison to the shift operator based discretization of FOO. In this paper, discrete d -operator parameterization is proposed for the digital realization using direct discretization of FOO. As a result, superior finite word length effect is observed for the realization of the FOO in discrete delta domain. Fractional order operator with different orders (a ) are considered for the realization purpose using the proposed method and the results obtained using MATLare presented for validation.

Formal synthesis of non-fragile state-feedback digital controllers considering performance requirements for step response

This work describes an approach for synthesizing state-feedback controllers for discrete-time systems, taking into account performance aspects. The proposed methodology is based on counterexample-guided inductive synthesis (CEGIS), producing safe controllers based on step response performance requirements, such as settling time and maximum-overshoot. Controller candidates are generated through constrained optimization based on genetic algorithms. Each iteration that does not satisfy the initial system requirements is learned as a failed result and then used in another attempt. During the verification phase, it is considered the controller fragility to ensure deployable implementations. Such an approach assists the discrete-time control system design since weaknesses occur during implementation on digital platforms, where systems that meet design requirements are employed. The proposed method is implemented in DSVerifier, a tool that uses bounded (and unbounded) model checking based on satisfiability modulo theories. Experimental results showed that our approach is practical and sound regarding the synthesis of discrete state-feedback control systems that present performance requirements. It considers finite word-length effects, unlike other methods that routinely ignore them.

Complementary mean square deviation and stability analyses of the widely linear recursive least squares algorithm

The widely linear recursive least squares (WL-RLS) algorithm is useful for dealing with noncircular signals. In this paper, we focus on the theoretical prediction and stability of the WL-RLS algorithm. First, the steady-state complementary mean square deviation (CMSD) behavior under a time-varying system is analyzed, which is different from the traditional standard mean square analysis that takes the form of real-valued evolution. Second, the Lyapunov stability and numerical stability are taken into account to provide an in-depth understanding of the stability issue. Specifically, by employing the Lyapunov stability theory (LST) approach, we perform the stability analysis of the WL-RLS algorithm for time-invariant system and noise-free output, illustrating that the WL-RLS algorithm is exponentially convergent in the sense of Lyapunov. Moreover, the numerical stability is analyzed by considering the finite word-length effects, and it is shown that the WL-RLS algorithm is numerically stable when the forgetting factor λ<1. Numerical simulations for system identification scenarios verify the accuracy of the steady-state theoretical prediction.

Design of Infinite Impulse Response Filter Using Fractional Derivative Constraints and Hybrid Particle Swarm Optimization

In this paper, a new method for designing digital infinite impulse response filter with nearly linear-phase response is presented using fractional derivative constraints (FDC). The design problem is constructed as a phase optimization problem between the desired and designed phase response of a filter. In order to achieve the highly accurate passband (pb) response, phase response is fitted to desired response more precisely using FDC, due to which design problem becomes a multimodal error surface that is constructed from sum of passband error (ep) and stopband error (es). Optimal value of FDC is accomplished by minimizing the total error (er0) using improved swarm-based optimization technique, which is formulated by associating the scout bee mechanism of artificial bee colony algorithm with particle swarm optimization and termed as hybrid particle swarm optimization. The simulated results reflect that the improved response in passband along with better transition width is achieved using the proposed method. It is observed that about 90–99% of improvement in passband error can be achieved with 100% reduction in maximum passband ripple. However, slight reduction in stopband attenuation (As), in some cases, results within the permissible limit. The designed filters using this method are also stable toward finite word length effect.

Formal Non-fragile Verification of Step Response Requirements for Digital State-Feedback Control Systems

We describe and evaluate a novel approach to formally verify whether a digital control system meets specifications related to step response parameters. In particular, we obtain a state feedback controller designed for a system represented by a state-space model. Then, we analyze whether its required specifications regarding settling time and maximum overshoot are met, using both open- and closed-loop forms and considering finite-word-length (FWL) effects for the latter. We developed our verification approaches inside DSVerifier, which is a verification tool that employs bounded (and unbounded) model checking based on satisfiability modulo theories. Thus, DSVerifier checks performance requirements of digital control systems considering fragility, such as round-off and numerical quantization errors. Our approaches were also evaluated over a set of standard control-system benchmarks extracted from the control literature. Experimental results show that DSVerifier can check settling time and overshoot in control systems suffering from FWL effects, while other existing approaches routinely ignore those issues.

Design and Realizations of Networked Estimators: A Descriptor Model Approach

This paper addresses the design and realization of a networked estimator, which requires further digital implementation using several subsystems. Implementation on a digital process entails finite word length effects on the coefficients’ representation, and a multiple-subsystem architecture also introduces internal time delays in the information interaction. Dealing with these intrinsic defects requires finding a resilient realization. A corresponding descriptor model-based approach is thus constructed to describe the internal time delays and equivalent realizations with finite word length effects in a unifying framework, which enables simultaneous consideration of design and realization. Based on the obtained descriptor model, a stability analysis condition is deduced and a design method for the estimator is further obtained. An algorithm is also proposed for finding the optimal realization requiring the minimum word length for stabilization. Finally, a simulation with two cooperative robots is considered to illustrate the effectiveness of the results.

Robust and Computationally Efficient Digital IIR Filter Synthesis and Stability Analysis Under Finite Precision Implementations

In this paper, an analytical synthesis method for obtaining an optimal infinite impulse response (IIR) state-space realization, say minimal pole-zero and pole-L2 sensitivity realizations, based on minimizing zero/L2 sensitivity measures subject to sparse normal-form state transition matrix is proposed. The proposed nth order realization possesses strong robustness and at most only 4n + 1 multiplications per output sample to prevent instability and output distortion, as well as to keep computational efficiency under finite word-length (FWL) effects. This is important for the IIR filter implemented in fixed-point and portable digital devices. In this paper, the proposed pole-L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> sensitivity minimization method, an alternative approach of pole-zero sensitivity minimization, may solve the issue of zero multiplicity. A normal-form realization has been proven that it can achieve a global minimum of un-weighted pole sensitivity measure as well as zero-input limit-cycle free property. The sparse normal-form realization can be synthesized from an arbitrary initial realization with distinct poles by using an analytical similarity transformation. Based on the derived fixed-point arithmetic model in state-space realizations, the Bellman-Gronwall Lemma, and normal-form transformation, a new word-length estimation to guarantee stability is derived. Finally, numerical simulations are performed to verify the correctness and the effectiveness of the theoretical results.

Verifying fragility in digital systems with uncertainties using DSVerifier v2.0

Control-system robustness verification with respect to implementation aspects lacks automated verification approaches for checking stability and performance of uncertain control systems, when considering finite word-length (FWL) effects. Here we describe and evaluate novel verification procedures for digital systems with uncertainties, based on software model checking and satisfiability modulo theories, named as DSVerifier v2.0, which is able to check robust stability of closed-loop control systems with respect to FWL effects. In particular, we describe our verification algorithms to check for limit-cycle oscillations (LCOs), output quantization error, and robust non-fragile stability on common closed-loop associations of digital control systems (i.e., series and feedback). DSVerifier v2.0 model checks new properties of closed-loop systems (e.g., LCO), including stability and output quantization error for uncertain plant models, and considers unknown parameters and FWL effects. Experimental results over a large set of benchmarks show that 35%, 34%, and 41% of success can be reached for stability, LCO, and output quantization error verification procedures, respectively, for a set of 396 closed-loop control system implementations and realizations.

Design of Bandpass and Bandstop Infinite Impulse Response Filters Using Fractional Derivative

In this paper, a new design method for digital bandpass and bandstop infinite impulse response filters with nearly linear-phase response is proposed. In this method, the phase response of an all-pass filter is optimized in the frequency domain to yield less passband error ${\text{Er}}_{p}$ and stopband error ${\text{Er}}_{s}$ with optimal stopband attenuation $A_{s}$ . To achieve high accuracy in passband and stopband regions, fractional derivative (FD) constraints are evaluated in the respective regions, and the filter coefficients are computed using the Lagrange multiplier method. The behavior of fidelity parameters measured in terms of ${\text{Er}}_{p}{,\text{Er}}_{s}$ , and phase error ${\text{Er}}_{{\text{ph}}}$ is multimodel w.r.t. FD values. Therefore, modern heuristic technique, known as cuckoo search optimization is used for determining the optimal value of FDs and reference frequency simultaneously to minimize the fitness function, which is constructed as a sum of the squared error in passband and stopband. The designed filter yields up to 60% reduction in ${\text{Er}}_{p}$ and ${\text{Er}}_{{\text{ph}}}$ in the case of bandpass filter. Meanwhile, the response of filter is not degraded due to the finite word length effect.

High‐throughput and compact reconfigurable architectures for recursive filters

This study presents various high-throughput reconfigurable architectures and their hardware implementation characteristics for infinite impulse response (IIR) filters. It is known that finite word length effects can be alleviated, to some extent, by realising a high-order IIR filter using the cascade of lower-order filter sections. The authors utilise the cascade structure of the first-order and second-order filters and apply a set of optimisation techniques, such as cutset retiming, look-ahead transformations, and interleaving for high-throughput realisations of IIR filters. Since the cascade structure may require a relatively large number of computational resources and storage elements, which depends linearly on the number of sections, the authors also present a filter processor architecture for the compact implementation of IIR filters. Filter architectures are developed in the fully parameterisable fixed-point representation and verified against their synthesisable Verilog descriptions. The authors present the implementation results of the transformed filter architectures on a Xilinx Virtex-7 field-programmable gate array (FPGA). To the best of their knowledge, this is the first presentation of various high-throughput and compact IIR filter architectures and their FPGA implementation characteristics.

Stability analysis of nonlinear digital systems under hardware overflow constraint for dealing with finite word-length effects of digital technologies

The purpose of this paper is to examine stability and originate stability criteria for nonlinear digital systems under the influence of saturation overflow, both in the absence and presence of external interference. The developed approaches can be employed to analyse overflow oscillation-free implementation of a nonlinear digital system under saturation overflow nonlinearity, caused by the finite word-length limitation of a digital hardware, such as computer processor or micro-controller. Asymptotic stability is examined in the absence of disturbance, whereas in the presence of external interference, the form of stability ensured is uniformly ultimately bounded stability, in which the states trajectories converge to an ellipsoidal region around the origin. In most of the studies reported so far, the authors have performed the overflow stability analysis of linear systems but very little (if any) work has been reported on the overflow oscillation elimination (for nonlinear systems). In the present work, sector conditions derived from saturation constraint along with Lipschitz condition are used with a suitable Lyapunov function for the stability analysis of nonlinear digital systems under overflow. The validity and efficacy of these criteria are tested by using examples from real nonlinear physical systems, including Moon chaotic system’s observer and recurrent neural network.

Formal Non-Fragile Stability Verification of Digital Control Systems with Uncertainty

A verification methodology is described and evaluated to formally determine uncertain linear systems stability in digital controllers with considerations to the implementation aspects. In particular, this methodology is combined with the digital-system verifier (DSVerifier), which is a verification tool that employs Bounded Model Checking based on Satisfiability Modulo Theories to check the stability of digital control systems with uncertainty. DSVerifier determines the control system stability, considering all the plant interval variation set, together with the Finite Word-length (FWL) effects in the digital controller implementation; DSVerifier checks the robust non-fragile stability of a given closed-loop system. The proposed methodology and respective tool are evaluated considering non-fragile control examples from literature. Experimental results show that the approach used in this study is able to foresee fragility problems in robust controllers, which could be overlooked by other existing approaches due to underestimating of FWL effects.

Variable state-space digital filters using series approximations

This paper proposes new state-space formulations of IIR Variable Digital Filters (VDFs) based on frequency transformations. The existing frequency transformation-based state-space VDFs require restrictions on the transfer functions, state-space representations, and tuning characteristics. On the other hand, the proposed method is free from such restrictions. We achieve this goal by applying series approximations to the conventional state-space formulations of frequency transformations. This approach also allows us to realize the proposed VDFs without complicated computations such as the inverse matrix and the square root. Furthermore, the proposed VDFs show high accuracy with respect to the finite wordlength effects as well as the approximation errors.

On the Extended Thin-Wire Kernel

A number of recent works have shown that moment-method solutions of Hallen’s and Pocklington’s equations with the approximate kernel present undesirable and unphysical oscillations near the ends of the antenna and possibly (depending on the feed model) near the driving point. Such oscillations have been associated with the nonsolvability of the underlying integral equations. They necessarily occur when the number of basis functions is sufficiently large and cannot be blamed on finite computer word length or matrix ill-conditioning effects. In this communication, we show that similar phenomena occur when one uses the extended thin-wire kernel, originally proposed by Poggio and Adams in the 1970s and currently used by the Numerical Electromagnetics Code, which is an antenna modeling software suite that has many variants (e.g., GNEC, EZNEC Pro, SuperNeC, MiniNEC). We discuss the nature and properties of the oscillations. In particular, we show that they are milder and less rapid than those with the approximate kernel. Our main tools of study are: 1) numerical investigations that carefully distinguish from effects due to roundoff and 2) an analytical study for the case of the antenna of infinite length. We finally apply the so-called effective-current method as a remedy to the issues arising from the said oscillations.

A Note on the Induced $${\varvec{l}}_\infty $$ l ∞ Stability of Fixed-Point Digital Filters Without Overflow Oscillations and Instability Due to Finite Wordlength Effects

A recently reported criterion due to Ahn and Lee (Adv Differ Equ 51:1---7, 2012) for the induced $${\varvec{l}}_\infty $$lź stability of fixed-point digital filters without overflow oscillations and instability due to finite wordlength effects is reviewed. This article points out that there is a technical error in the main result and at the same time presents an approach to correcting the main result. Moreover, a relaxed version of the criterion is made available. Illustrative examples are given to demonstrate the effectiveness of the proposed result.

AN ANALYSIS TO DESIGN MERGED DELAY TRANSFORMED IIR DOWN SAMPLER FILTER: AN EFFICIENT DOWN SAMPLER FILTER ARCHITECTURE

An efficient architecture of Down Sampler Filter using Merged Delay Transformed Technique in terms of cost reduction and increase throughput has been proposed. The stability analysis of Merged Delay Transformed filters, finite word length effect on Transformed filters as well as conventional filters and peak error between the output from transformed IIR filters and from conventional filters have been investigated on the basis of commercially available software and mathematical calculations. The Butterworth, Chebyshev-1, Chebyshev-2 and Elliptic filters have been considered in this paper for the sake of comparison. The simulation results show that 84.59%, 73.56% and 50.83%&78.71%, 73.85% and 51.89% reduction in cost can be achieved with different specifications by using the proposed scheme when it is compared with conventional FIR filter, conventional IIR filter and conventional polyphase IIR filter, respectively. It has been elaborated that the stability of transformed IIR Decimation filters will not disturb as the Decimation Factor M increases. It is also shown that the transformed Elliptic filter is more stable and the transformed Chebyshev-2 filter is a marginally stable filter. The simulation results show that the peak error is in the range of 10 -10 to 10 -17 which increases with an increase in order of the filter. On the basis of simulation results and mathematical calculations, it is shown that the decomposition of higher order system into 1 st order and 2 nd order systems using parallel implementation architecture with Merged Delay Transform increases the processing rate of the filter and a reduction in the cost of implementation as well as peak error.

Covariance matrix adaptation evolution strategy based design of fixed structure robust H∞ loop shaping controller

This paper proposes the application of Covariance Matrix Adaptation Evolution Strategy (CMA-ES) in fixed structure H∞ loop shaping controller design. Integral Time Absolute Error (ITAE) performance requirement is incorporated as a constraint with an objective of maximization of stability margin in the fixed structure H∞ loop shaping controller design problem. Pneumatic servo system, separating tower process and F18 fighter aircraft system are considered as test systems. The CMA-ES designed fixed structure H∞ loop-shaping controller is compared with the traditional H∞ loop shaping controller, non-smooth optimization and Heuristic Kalman Algorithm (HKA) based fixed structure H∞ loop shaping controllers in terms of stability margin. 20% perturbation in the nominal plant is used to validate the robustness of the CMA-ES designed H∞ loop shaping controller. The effect of Finite Word Length (FWL) is considered to show the implementation difficulties of controller in digital processors. Simulation results demonstrated that CMA-ES based fixed structure H∞ loop shaping controller is suitable for real time implementation with good robust stability and performance.

Chaotic map implementation based on digital-analog hybrid method

Random number generator plays an important role in many domains, including secret communication, radar waveform generation, etc. However, the existing methods for generating random numbers cannot meet the actual demand for speed. Even worse, the use of analog device will restrict the speed of generator and robustness of system. As a result, researchers start to turn their eyes to digital implementation which is stabler and more efficient than the analog counterpart. Unfortunately, digital methods still have the disadvantages of dynamical degradation because of word length limitation effect. Though some remedies, such as increasing computing precision, cascading multiple chaotic systems, pseudo-randomly perturbing the chaotic system, the switching multiple chaotic systems and error compensation method are proposed, but the limitations are still inevitable. In recent researches, continuous-time chaotic oscillators are used with digital devices to realize random number generator, and a new approach is proposed to solve the dynamical degradation of digital chaotic system by coupling the given digital chaotic map with an analog chaotic system, where the analog chaotic system is applied to anti-control the given digital chaotic map. However, this method also requires a whole continuous-time system realized with analog devices, which confines the system performance. In this paper, a new digital-analog hybrid chaotic map with only one analog capacitor is constructed to produce random numbers. Firstly, the block diagram of digital-analog hybrid system based on the single capacitance feedback is given, and the model of the system is derived from the block diagram. Secondly, the simple logistic map is applied to the model and its nonlinear dynamics behaviors are analyzed and compared to verify the correctness and effectiveness of the proposed method. Then a more complex two-way coupled saw tooth map is used to produce pseudorandom sequences through simulation smoothly. When designing the circuits of the system, a digital-analog hybrid implementation with field programmable logic gate array and a single analog capacitor is used to realize chaotic maps, showing that it can overcome the finite word length effect of digital implementation. NIST, a general statistical test suiting for random and pseudorandom number generator cryptographic applications, is used to test the sequences produced by the new system. The results show that the new hybrid system is insensitive to the evolution of circuit parameters and the randomness of sequence is in accordance with the practical application. The circuit implementation verifies the numerical simulation and theoretical results. The high speed digital devices and a single analog capacitance are applied to the proposed random sequence generator, and therefore it can be integrated easily into the systems of digital encryption, secure communication and radar waveform generation.

Study of finite word-length effect on the performance of watermarking methods

This present paper represents a simple framework for the novel study of the effect of finite word-length FWL on the performance of different watermarking methods in the computer environment. We have evaluated the performance of discrete wavelet transform DWT and singular value decomposition SVD-based watermarking methods at different word-lengths and found a reliable word-length the word-length up to which change in the performance is significant and beyond this, is unnoticeable for each watermarking method. The reliable word-length can be used as a new benchmark for comparing different watermarking methods for their real-time implementation, where optimisation with respect to memory, implementation area, performance, and power consumption are the foremost demand.