Implementation Of Finite State Machines Research Articles

Autonomous diode laser weeding mobile robot in cotton field using deep learning, visual servoing and finite state machine

Small autonomous robotic platforms can be utilized in agricultural environments to target weeds in their early stages of growth and eliminate them. Autonomous solutions reduce the need for labor, cut costs, and enhance productivity. To eliminate the need for chemicals in weeding, and other solutions that can interfere with the crop’s growth, lasers have emerged as a viable alternative. Lasers can precisely target weed stems, effectively eliminating or stunting their growth. In this study an autonomous robot that employs a diode laser for weed elimination was developed and its performance in removing weeds in a cotton field was evaluated. The robot utilized a combination of visual servoing for motion control, the Robotic operating system (ROS) finite state machine implementation (SMACH) to manage its states, actions, and transitions. Furthermore, the robot utilized deep learning for weed detection, as well as navigation when combined with GPS and dynamic window approach path planning algorithm. Employing its 2D cartesian arm, the robot positioned the laser diode attached to a rotating pan-and-tilt mechanism for precise weed targeting. In a cotton field, without weed tracking, the robot achieved an overall weed elimination rate of 47% in a single pass, with a 9.5 second cycle time per weed treatment when the laser diode was positioned parallel to the ground. When the diode was placed at a 10°downward angle from the horizontal axis, the robot achieved a 63% overall elimination rate on a single pass with 8 seconds cycle time per weed treatment. With the implementation of weed tracking using DeepSORT tracking algorithm, the robot achieved an overall weed elimination rate of 72.35% at 8 seconds cycle time per weed treatment. With a strong potential for generalizing to other crops, these results provide strong evidence of the feasibility of autonomous weed elimination using low-cost diode lasers and small robotic platforms.

Experimental assessment of a JANUS-based consensus protocol

This paper proposes a distributed, JANUS-based protocol that enables an underwater acoustic network to reach consensus on arbitrary local opinions as numeric state variables. An envisioned scenario where nodes shall agree on parameters describing the acoustic environment is used to evaluate the protocol. The scenario exemplifies the protocol’s potential in future applications where nodes use the environment description to decide on appropriate modulation and coding schemes.The evaluation is based on numerical simulations and sea experiments in a challenging acoustic environment. The numerical simulations allowed examining the performance for different parameter values regarding the timing of transmission events and state transitions in the finite state machine implementation of the protocol. The best parameter configuration was used in the sea experiments conducted in a bay in the Baltic Sea. The experiments comprised several deployments of five to six commercial modems.Results from the experiments show that the protocol can achieve a consensus up to 89% of the time in the tested environment, and up to 96% of the time if the state variables are permitted to differ by one discretisation step maximum across the network. In addition, if the network separates due to environmental conditions, connected components appear to achieve consensus more often when the links are more reliable. Finally, it is shown that when different consensus processes are active in parallel, packets from one process do not interfere with the opinions in different processes, besides the existing probability of packet loss due to packet collision.

Implementation of Finite State Machine Algorithm for Interactive Physics Learning in a 3D Game

Physics is a subject taught in high schools as per the established curriculum. Teachers often employ traditional teaching methods where students study independently without active participation, leading to boredom and reduced enthusiasm for learning. Physics is frequently perceived as difficult and perplexing by most students, and the utilization of 3D games as a learning tool can help overcome these challenges. This research aims to integrate the Finite State Machine (FSM) algorithm into a 3D game to create a more effective and engaging learning experience for students. The study employs the waterfall method in application development, encompassing stages such as needs analysis, application design, FSM implementation in games, and game testing and evaluation. 3D physics games have been successfully developed and tested for their feasibility. This game serves as an effective means of entertainment and learning, aiding students in enhancing their understanding of physics subjects. According to the results of a questionnaire with 50 respondents, it is evident that this 3D game is quite user-friendly (90%) and possesses a very good user interface (89%). Approximately 78% of respondents stated that their experience in using the game was very good. Moreover, 82% of respondents found that this educational physics game was highly beneficial for learning physics material.

Recurrent neural network implementation of digital integrated circuits to mitigate challenges in design verification

Design verification is the dominant stage that consumes the most resources in the digital integrated circuit (IC) design process. Design verification is important because human designers imperfectly convert high-level specifications to low-level circuit implementations using standard cell logic, which is nonlinear and complex to predict and characterize. The widening process variations in shrinking process technologies while digital designs grow in scale and complexity to the extent of being impossible to fully or intuitively identify all temporal interactions of a specific design. Deep neural networks (DNN) are being progressively integrated into the sophisticated software tool chain and design process flow of digital IC as artificial intelligence can learn relationships and correlations in complex, high-dimensional, and multi-factorial problems. In this work, we propose to apply DNN to implement digital IC to minimize the complexity of digital design verification. We posit that DNN can learn to implement circuit functions directly from high-level specifications without requiring detailed specifications from the designer. Trained neural networks can be implemented on neuromorphic hardware to achieve greater power and compute efficiencies than the conventional standard cell implementation. We demonstrate that over 150 randomly generated finite state machines (FSM) can be learned effectively with Recurrent Neural Network (RNN) comprising Gated Recurrent Units (GRU) with different complexity as indicated by the number of states and inputs to the FSM. Our proposed methodology of learning RNN GRU implementations of FSM demonstrates a way forward to reduce the cost and effort of design verification, ultimately leading towards faster digital IC design cycles.

Implementation of FSM Based Chat-Bots in a Graphical Designer

Finite state machine (FSM) is a powerful tool to model object behavior. Using FSM and its extensions to model program behavior followed by the automatic generation of executable code is the approach encouraged by the model-driven development (MDD) – a software development methodology based on the concepts of model and model transformation.In this paper, a brief overview of FSM-based common methods to model and develop software programs of any nature is given. These methods include David Harel’s statecharts, UML State Machines, Virtual Finite State Machine, etc. Examples of all types of software systems (transformational, interactive, reactive) implemented using FSM are cited.Chat-bots as an example of an interactive software system are considered: concept, classification methods, implementation techniques. A graphical designer of rule-based chat-bots to be integrated in the messenger Telegram is developed and implemented. In this designer, chat-bot behavior is modeled using FSM.Formal method to model a rule-based chat-bot using FSM is provided. The FSM concept is extended by disabled transitions to save history of transition changes made during the FSM design process. A brief overview of code generation methods from FSM specification is done; advantages and disadvantages of the most popular approaches are considered. Dynamic approach to generate code by FSM specification saved in DB is proposed. To implement this approach, document MongoDB and in-memory key-value Redis DB are used; FSM is kept as a JSON-document. This approach is efficient in flexibility, speed and memory needs.Architecture diagram of developed chat-bot graphical designer is given. It has the microservice architecture. The FSM model-to-code transformation is carried out by the bot-execution service written using compiled language Go. Other services include the front-end (UI for end-user, CRUD API for chat-bot) and the bot-management (synchronization of document and key-value databases) services.

Mapping Outputs and States Encoding Bits to Outputs Using Multiplexers in Finite State Machine Implementations

This paper proposes a new technique for implementing Finite State Machines (FSMs) in Field Programmable Gate Arrays (FPGAs). The proposed approach extends the called column compaction in two ways. First, it is applied to the state-encoding bits in addition to the outputs, allowing a reduction in the number of logic functions required both by the state transition function and by the output function. Second, the technique exploits the dedicated multiplexers usually included in FPGAs to increase the number of columns that can be compacted. Unlike conventional state-encoding techniques, the proposed approach reduces the number of logic functions instead of their complexity. An Integer Linear Programming (ILP) formulation that maximizes the number of compacted columns has been proposed. In order to evaluate the effectiveness of the proposed approach, experimental results using standard benchmarks are presented. In most cases, the proposed approach reduces the number of used Look-Up Tables (LUTs) with respect to the conventional FSM implementation.

Design and Implementation of Power-Efficient FSM based UART

The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.

Fast Adaptive Character Animation Synthesis Based on Greedy Algorithm

On the premise of ensuring the animation effect and real-time performance, it is of great significance and value for large-scale group character animation synthesis how to reduce the disaster coincidence degree among various models of fast adaptive character animation synthesis. The realization method of object-oriented finite state machine is studied in detail. Finite state machine (FSM) is an efficient behavior modeling method, which can describe the behavioral decisions of fast adaptive character animation synthesis in a complex virtual environment. Based on the implementation defects of the finite state machine in the traditional structure, using object-oriented thinking, combined with the state design mode, we further studied a finite state machine implementation method based on object-oriented technology. This achieves code reuse and simple program maintenance. The effect is extensible and effectively overcomes the shortcomings of traditional character animation synthesis. Secondly, the multipath matching tracking algorithm of the greedy algorithm is studied to generate multiple candidate sets through multiple paths, and finally, the candidate set with the minimum residual error is selected as the estimated support set, so as to improve the reconstruction performance. Further, based on the idea of multipath, using the regularization method of the ROMP algorithm, the regularized multipath matching tracking RMSP algorithm is proposed. It uses the regularized subset method to generate multiple paths and chooses the path with the fastest residual reduction as the support set of this iteration. The simulation results show that the RMSP algorithm has better reconstruction performance than the SP algorithm.

Finite State Machine-Based Realization of Sparse Matrix Converter

Matrix converters (MCs), compared to traditional back-to-back converters, offer a series of advantages for ac-ac power conversion. However, increased realization complexity and cost have restricted the proliferation of MCs to a limited number of commercially available solutions. In this article, an efficient sparse matrix converter realization is presented as a step toward the development of simpler, lower-cost, and reliable realization architectures. In contrast to common practices that utilize a flexible logic fabric, such as a field programmable gate array or a complex programmable logic device, and a digital signal processor, the proposed implementation is based on a single commercial off-the-shelf microcontroller unit. This method is possible due to the novel implementation of a synchronous finite state machine that realizes the four-step commutation strategy required by the current source rectifier stage. Since the complete control scheme is implemented in one IC, it inherently avoids important MC realization issues, such as communication delays and synchronization between controllers. In addition, both software and hardware requirements are reduced and lower the overall development effort and cost.

Methodology for Distributed-ROM-Based Implementation of Finite State Machines

This brief explores the optimization of distributed-ROM-based finite state machine (FSM) implementations as an alternative to conventional implementations based on look-up tables (LUTs). In distributed-ROM implementations, LUTs with constant output value (called constant LUTs) and LUTs with the same content (called equivalent LUTs) can be saved. We propose a methodology to implement FSMs using distributed ROM that includes: 1) a greedy state encoding algorithm; 2) an algorithm to find the way of interconnecting the address signals to the ROM that maximize the number of constant or equivalent LUTs; and 3) a set of architectures to implement the columns of the ROM. The results obtained have been compared with conventional LUT-based implementations using standard benchmarks. The proposed technique reduces the number of LUTs in a 91% of cases and increases the speed in all cases.

A comparison of schedulability analysis methods using state and digraph models for the schedulability analysis of synchronous FSMs

Synchronous reactive models are widely used in the development of embedded software and systems. The schedulability analysis of tasks obtained as the code implementation of synchronous finite state machines (FSMs) can be performed in several ways. One possible option is to leverage the correspondence between the execution of actions in an FSM and the execution of jobs in a digraph task model, thereby applying all the analysis methods developed for these digraph task systems. Another option is to directly leverage the state information and use dynamic programming methods to compute the worst possible sequence of (state dependent) reactions for a given FSM model. In this paper we compare these analysis methods in terms of accuracy and runtime.

FSM Based VLSI Architecture for Decision Based Neighborhood Referred Asymmetrical Trimmed Variant Filter

A VLSI architecture using Finite State Machine Based for logic based vicinity inferred asymmetrically trimmed variants filter is proposed. The filter was checked on MATLAB environment and found to suppress high density salt and pepper noise. For better speed & power constraints the algorithm was implemented on VIRTEX FPGA using VHDL as part of system on chip implementation. The Proposed VLSI architecture uses one hot encoding for Finite state machine implementation of the filter. The architecture has 5 different modules and each computes the desired values using Finite state machine. There are three main computations implemented in this filter as separate module titled asymmetrical trimmed median, Midpoint, Mean of 4 Neighbors and local mean. The FSM uses one hot encoding Technique for lower power consumption. The architecture was targeted on FPGA device XCV1000-4bq560 using VHDL. The synthesis of the architecture utilizes 2744 slices of FPGA, operates at 54.630 MHz frequency and consumes 32 mw of power.

FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

The mathematical model for designing a complex digital system is a finite state machine (FSM). Applications such as digital signal processing (DSP) and built-in self-test (BIST) require specific operations to be performed only in the particular instances. Hence, the optimal synthesis of such systems requires a reconfigurable FSM. The objective of this paper is to create a framework for a reconfigurable FSM with input multiplexing and state-based input selection (Reconfigurable FSMIM-S) architecture. The Reconfigurable FSMIM-S architecture is constructed by combining the conventional FSMIM-S architecture and an optimized multiplexer bank (which defines the mode of operation). For this, the descriptions of a set of FSMs are taken for a particular application. The problem of obtaining the required optimized multiplexer bank is transformed into a weighted bipartite graph matching problem where the objective is to iteratively match the description of FSMs in the set with minimal cost. As a solution, an iterative greedy heuristic based Hungarian algorithm is proposed. The experimental results from MCNC FSM benchmarks demonstrate a significant speed improvement by 30.43% as compared with variation-based reconfigurable multiplexer bank (VRMUX) and by 9.14% in comparison with combination-based reconfigurable multiplexer bank (CRMUX) during field programmable gate array (FPGA) implementation.

Minimization of mealy finite-state machines by using the values of the output variables for state assignment

Structural models of finite-state machines (FSMs) that make it possible to use the values of the output variables for encoding the internal states are studied. To minimize the area (the parameter area is used to denote cost in the context of this paper) of FSM implementation, it is proposed to use the structural model of the class D FSM. A method for the design of the class D FSM in FPGA is proposed. This method involves two phases--splitting the internal states of the FSM (to satisfy the necessary conditions for the construction of the class D FSM) and encoding the internal states (to ensure that the codes are mutually orthogonal). It is shown that the proposed method reduces the area of FSM implementation for all families of FPGAs of various manufacturers by a factor of 1.41---1.72 on average and by a factor of two for certain families. Practical issues concerning the method and the specific features of its use are discussed, and possible directions of the elaboration of this approach are proposed.

Design of Power Aware on Chip Embedded Memory based FSM Encoding in FPGA

A new design methodology to reduce power consumption and minimization of area in FSM based system is fore fronted into FPGA using Finite State Machines (FSMs) mapping in this proposed work. This FSM is mapped into the On Chip Embedded Memory (OCEM) through clock gating technique. FSM encoding is stored using OCEM as it reduces the Flip-Flop (FF) and combinational function usage. Clock gating technique will reduce the power consumption additionally through blocking the clock while OCEMP is in idle state. The proposed design is tested and analyzed using ALTERA cyclone II FPGA for Arithmetic Logic Units (ALU), Advanced Encryption Standard core (AES), SRAM controller and Synchronous FIFO. OCEM based implementation of One- Hot encoding is performed and compared with conventional Flip-Flop based One-hot encoding and analyzed. The FSM implemented using proposed method consumes less power and fewer areas when compared with FF based FSM implementation or using binary encoding technique. The OCEM based implementation can be clocked to maximum clock frequency. Experimental results and analyses shows that OCEM based FSM consumes 4 to 26 % less power than FF based techniques.

FPGA IMPLEMENTATION OF A FUNCTIONAL MICROCONTROLLER

In any control and controller system applications, microcontroller is an important module, which provides the control, timing and status signals. A microprocessor is usually defined as “a single chip that contains control logic and data processing logic, so that it can execute instructions listed in a program to operate on some data”. Microcontrollers are nothing but microprocessors with onchip memory. This paper primarily deals with the implementation of an 8 bit microcontroller to perform arithmetic and logical operations. The modules are programmed using Very High Speed IC Hardware Description Language (VHDL). Using top-down approach, the elements of the microcontroller are identified as basic registers, instruction register, program counter, ALU, ROM, Control and timing Unit. All these modules are connected together to form a top module which is controlled by a Finite State Machine (FSM). The Finite State Machine enters each of the predefined states based on the inputs. FSM implementation also aids in changing the functionalities of the system without completely redesigning the system. Finally, in the top level module, these blocks are connected to form a functional microcontroller. In this paper, we have simulated and synthesized the various parameters of microcontroller by using VHDL on Xilinx ISE 8.2i and SPARTAN 3 FPGA board.

On the global optimization of checking sequences for finite state machine implementations

A checking sequence for a given domain of deterministic finite state machine implementations is an input sequence for which exactly the non-faulty members of the domain produce a non-faulty response. In the paper, we reconsider a popular family of methods which construct a checking sequence by performing its digraph-based global optimization. Recently, it was demonstrated that many of the methods are unsafe. As a remedy, a simple, but sufficient set of additional constraints on the structure of the employed digraph was introduced. In this paper, we show that the constraints sometimes ban also some of those originally considered checking sequence candidates which are sound. To safely restore the original power of the checking sequence construction approach, we perform its thorough re-engineering. This results in a very transparent and flexible generic method from which various methods of practical interest, both new ones and analogues of the traditional ones, can be derived simply by specialization.

Designing Run-Time Environments to Have Predefined Global Dynamics

The stability and the predictability of a computer network algorithm's performance are as important as the main functional purpose of networking software. However, asserting or deriving such properties from the finite state machine implementations of protocols is hard and, except for singular cases like TCP, is not done today. In this paper, we propose to design and study run-time environments for networking protocols which inherently enforce desirable, predictable global dynamics. To this end we merge two complementary design approaches: (i) A design-time and bottom up approach that enables us to engineer algorithms based on an analyzable (reaction) flow model. (ii) A run-time and top-down approach based on an autonomous stack composition framework, which switches among implementation alternatives to find optimal operation configurations. We demonstrate the feasibility of our self-optimizing system in both simulations and realworld Internet setups.

Implementation of finite-state machines based on programmable logic ICs with the help of the merged model of Mealy and Moore machines

The problem concerning the synthesis of finite-state machines (FSMs) based on programmable logic ICs, in which FSM’s output variables serve as the code (or part of the code) of internal states, has been examined. A solution to the problem is obtained with the help of the merged model of Mealy and Moore machines. A principal distinction between the proposed and well-known techniques is that an initial FSM undergoes no conversions related to an increase in the number of internal states and transitions thereof. The necessary conditions under which output variables can be used as the code of FSM’s internal states are presented. The method for synthesizing the merged model AC of Mealy and Moore machines is described. Basic results of investigations, as well as promising directions of further studies concerned with the development of new structural models of FSMs, are discussed.

Creating a Self-configuring Finite State Machine out of Memory Look-up Tables

A finite state machine (FSM) is one of the most used digital logic applications in today's electrical systems. An FSM can be implemented in electrical systems based on programmable logic devices (PLD) or combinatorial logic platforms. Both platforms for a FSM contain advantages and restrictions for the hardware and software design. In regards of coding, FSM can be coded in alternatives styles and programming languages. In this paper we introduce the concept of a self-configuring FSM based on coding data as memory look-up tables. The resulting FSM is then able to self-configure the combinatorial logic of this FSM required to perform the compulsory state sequence. The primary benefit of using memory based look-up table (LUT) FSM is that well established data error correction methods can be applied to protect the FSM behavior, even in the event of single error events (SEE). A high level hardware design of this FSM will be presented in comparison to a PLD FSM implementation.