Finite Impulse Response Filter Design Research Articles

A novel design algorithm for low complexity sparse 2‐D FIR filters

SummaryThe hardware implementation complexity of traditional two‐dimensional (2‐D) finite impulse response (FIR) filters with high order is very high. In this paper, a novel sparse 2‐D FIR filter design algorithm has been proposed by combining the common subexpression elimination technique and sparse filter design algorithms to reduce hardware implementation complexity. First, an initial 2‐D FIR filter with sparse coefficients that meets frequency‐domain specifications is obtained by the sparse filter design algorithm. Then, each filter coefficient is quantized in canonical signed digit, and the sensitivities of all weight‐two subexpressions and isolated non‐zero bits are calculated. Finally, the filter coefficients with low implementation cost are reconstructed via iteratively choosing subexpressions and isolated non‐zero bits in terms of their sensitivities. Simulation results show that the proposed algorithm saves about of adders compared with other low complexity filter design method, which reduces effectively the implementation cost.

Enhanced FPGA linear phase FIR filter with amalgam multiplier

ABSTRACT Designing high-performance integrated circuits that balance area, speed, and power is increasingly challenging. This study optimises hardware implementation of FIR filters using an innovative Amalgam Multiplier, minimising resource use without compromising performance. The key challenge in designing signal processing hardware is the multiplier design, which significantly affects efficiency. This study explores integrated circuit optimisation, addressing the delicate balance between area utilisation, speed, and power consumption. Focusing on hardware implementation of Finite Impulse Response (FIR) filters in signal processing, the article starts with a conventional FIR filter design using a standard array multiplier which consumed 1.790 W, with 8 s real-time completion. Then, Linear Phase FIR (LP-FIR) filter is designed using Braun and Dadda Multiplier. LP-FIR filter with Braun multiplier consumed 1.436 W power and 26 s of completion time whereas LP-FIR with Dadda multiplier consumed 1.363 W power and 23 s of completion time. Finally, the implementation of novel LP-FIR enhanced by Amalgam multiplier consumed 0.302 W power and 10.29 s of completion time, marking a significant advancement in integrated circuit design.

Design and Implementation of FIR Filters for Biomedical Applications

Abstract: Digital signal processing (DSP) greatly facilitates the continuous capture, monitoring, processing, and analysis of signals in real-world applications, particularly in biomedical or wearable devices. Within DSP systems, the design of Finite Impulse Response (FIR) filters is pivotal. In scenarios demanding intricate calculations and high precision, higher-order filters are employed. Multipliers are crucial components in filter design, consuming significant chip space and introducing extra computation overhead. Designers strive to optimize multipliers to enhance performance. In this project we are going to design pipelined based FIR filter by applying pipelining concept to the FIR filter and following the previous implementations such as the FIR filter with high accuracy compared to existing method. The proposed system architectures are known to be efficient for real signal processing, offering advantages over conventional based designs. The proposed design is anticipated to yield benefits in terms of area, power consumption, and timing performance. The synthesis and simulation of the existing and proposed designs are implemented using Cadence Virtuoso.

Area and delay efficient RNS-based FIR filter design using fast multipliers

In today's digital age, speed, and area are the primary design concerns. Increasing the rate at which multiplication and addition are performed has always been a need for developing cutting-edge technologies. Wallace multipliers, and Dadda multipliers, are one of the fastest multipliers used in many processors to accomplish fast arithmetic operations. A novel approach to design a LookUp Table (LUT) multiplier was proposed and implemented in Finite Impulse Response (FIR) filter. To improve the Residue Number System (RNS) based FIR filter's performance, several adders like Carry Look ahead (CLA) adder, Kogge Stone adder (KSA) and proposed adder architectures have been implemented. When compared with the 16 tap with 32 bit proposed adder with LUT multiplier, the hardware resource utilization (Logic Elements) is decreased by 5.97 % and in 32 tap with 16 bit combination, it decreases by 7.60 %.When compared with 32 tap with 4 bit word length, the proposed adder with LUT multiplier in the highlighted combinations, the Fmax is increased by 19.28 % and in 32 tap with 16 bit, it increases by 29.74 %. The Low-pass RNS FIR filter is designed for a cut-off frequency of 50 Hz and generated filter coefficients in MATLAB and implemented to denoising the ECG signal.

An efficient reconfigurable FIR filter design with coefficient optimization using a modified bacterial foraging optimization algorithm

ABSTRACT The digital filters play a significant role in the field of digital signal processing (DSP). The finite impulse response (FIR) filter is an attractive choice because of the ease of design and good stability. The digital filters have a wide variety of applications such as signal processing, control systems, telecommunication, etc. They are better than the analogue filters due to their performance. In recent times, software radios have achieved attention owing to requirements for integrated and reconfigurable communication systems. Hence, reconfigurations have emerged as a significant problem in the designs of FIRs. To match the frequencies of DSP applications, higher-order FIRs are required. If length of filters rises, addition and multiplication operations also increase. This paper proposes an efficient hardware design of RFIR that employs modified bacterial foraging optimizations (MBFOs) and common sub-expression eliminations (CSEs) in its executions. MBFOs output restricted counts of filter coefficients with sums of signed-power-of-two (SPT) terms while maintaining the quality of filtered responses. On obtaining coefficients, eliminations are executed by CSEs where hardware complexities are determined in terms of adders. Model sim software validated RFIRs using the Verilog code. The proposed design of RFIRs was compared with existing designs in terms of power usages, frequencies and areas.

Implementation of a Finite Impulse Response Filter using PUFs to Avoid Trojans

In the modern era of signal processing, digital filters play an important role in real-time applications such as communication, consumer electronics, digital signal processing, audio, etc. In digital filter design, Finite Impulse Response (FIR) filters are highly preferable due to their linear phase and inherent stability. These filters benefit from being time-invariant and simple to implement with minimal computational requirements. Therefore, the hardware security of FIR filters is essential for good performance and reliable results. On the other hand, there is the possibility of hardware threats, such as tampering, reverse engineering, hardware Trojans, etc., as the design of an FIR filter involves many stages. Such hardware attacks on FIR filters can cause several problems, including performance degradation, leakage of confidential information, lack of stability, etc. This study presents the design and implementation of a Trojan-aware FIR filter using Physical Unclonable Functions (PUFs). The key feature of PUFs is that they generate a unique and unpredictable response for each given challenge. In the proposed design, PUFs were used to generate the FIR filter coefficients that are unique and unpredictable by attackers/trojans to improve security. The security of FIR with PUF was tested using ML-based challenges, and the results showed approximately 30% more reliability and consistency compared to the FIR without PUFs.

Minimized Group Delay FIR Low Pass Filter Design Using Modified Differential Search Algorithm

Designing a finite impulse response (FIR) filter with minimal group delay has proven to be a difficult task. Many research studies have focused on reducing pass band and stop band ripples in FIR filter design, often overlooking the optimization of group delay. While some works have considered group delay reduction, their approaches were not optimal. Consequently, the achievement of an optimal design for a filter with a low group delay value still remains a challenge. In this work, a modified differential search optimization algorithm has been used for the purpose of designing a minimal group delay FIR filter. The results obtained have been compared with the classical techniques and they turned out to be promising.

Adaptive FIR Filter Design with Approximate Adder and Hybridized Multiplier for Efficient Noise Eradication in Sensor Nodes

Finite Impulse Response (FIR) filter contributes a major role in most of the signal processing applications. However, the Finite Impulse Response filter performance is restricted by its speed, power and area usage. To address these issues, an adaptive FIR filter design using approximate adder and Hybridizing (Radix-8 Booth and TRAM) Approximate Multiplier (DA-AFIR-leadx-hybam-AC) is proposed in this manuscript for eradicating the noise in the sensor nodes. Here, Low error together with area efficient approximate adder (leadx) is used for reducing path delay and area utilization. For approximate multiplier design, proposed Hybridizing (Radix-8 Booth and TRAM) Approximate Multiplier using 15–4 Approximate Compressors (hybam-AC) is used for decreasing power consumption and design complexity. The simulation of the proposed model is implemented in Verilog and the design is synthesized in FPGA utilizing Xilinx ISE 14.5. The proposed DA-AFIR-leadx-hybam-AC filter design attains 33.6%, 22.75%, 29.69% lower power and 43.58%, 11.3%, 33.07% lower delay than the existing approaches, like DA-AFIR-MLDA-RNS, DA-AFIR-Hyb-CSD-ABR, DA-AFIR-SOPOT-MPGBP. Finally, the proposed DA-AFIR-leadx-hybam-AC filter design is applied for noise removal application in sensor nodes. The proposed Filter is implemented in MATLAB/Simulink for reading input signal.

Low-Power Reconfigurable FIR Filter Design Based on Common Operation Sharing

This paper presents a low-power, fully reconfigurable finite impulse response (FIR) filter structure based on common operation sharing. Different from existing multiplexer(MUX)-based designs, the decoding of coefficients and compensation of negative-coefficient errors, which are the common operations for all the taps, are implemented by shared modules to reduce the overall hardware complexity. To validate the proposed structure, a proof-of-concept reconfigurable FIR filter is implemented and fabricated using 40 nm CMOS technology. Chip measurement results show that the proposed design is superior to existing methods in area-delay product and power performance, making it suitable for low-power filtering applications. The idea of sharing common operations for all taps can benefit the existing MUX-based filter techniques for further improvement of power and circuit complexity.

Fast and Arbitrary Beam Pattern Design for RIS-Assisted Terahertz Wireless Communication

Reconfigurable intelligent surface (RIS) can assist terahertz wireless communication to restore the fragile line-of-sight links and facilitate beam steering. Arbitrary reflection beam patterns are desired to meet diverse requirements in different applications. This paper establishes relationship between RIS beam pattern design with two-dimensional finite impulse response filter design and proposes a fast non-iterative algorithm to solve the problem. Simulations show that the proposed method outperforms baseline method. Hence, it represents a promising solution for fast and arbitrary beam pattern design in RIS-assisted terahertz wireless communication.

Design of Optimal Multiplierless FIR Filters With Minimal Number of Adders

This work presents two novel methods that simultaneously optimize both the design of a finite impulse response (FIR) filter and its multiplierless hardware implementation. We use integer linear programming (ILP) to minimize the number of adders used to implement a direct/transposed FIR filter adhering to a given frequency specification. The proposed algorithms work by either fixing the number of adders used to implement the products (multiplier block adders) or by bounding the adder depth (AD) used for these products. The latter can be used to design filters with minimal AD for low-power applications. In contrast to previous multiplierless FIR filter approaches, the methods introduced here ensure adder count optimality. We perform extensive numerical experiments, which demonstrate that our simultaneous filter design approach yields results that are in many cases on par or better than those in the literature.

Feature Mode Decomposition: New Decomposition Theory for Rotating Machinery Fault Diagnosis

In this article, a new decomposition theory, feature mode decomposition (FMD), is tailored for the feature extraction of machinery fault. The proposed FMD is essentially for the purpose of decomposing the different modes by the designed adaptive finite-impulse response (FIR) filters. Benefitting from the superiority of correlated Kurtosis, FMD takes the impulsiveness and periodicity of fault signal into consideration simultaneously. First, a designed FIR filter bank by Hanning window initialization is used to provide a direction for the decomposition. The period estimation and updating process are then used to lock the fault information. Finally, the redundant and mixing modes are removed in the process of mode selection. The superiority of the FMD is demonstrated to adaptively and accurately decompose the fault mode as well as robust to other interferences and noise using simulated and experimental data collected from bearing single and compound fault. Moreover, it has been demonstrated that FMD has superiority in feature extraction of machinery fault compared with the most popular variational mode decomposition.

Design and Implementation of Communication Digital FIR Filter for Audio Signals on the FPGA Platform

Digital Signal Processing (DSP) in telecommunications is widely used for its outstanding performance. Hence, optimal results would be obtained with the sophisticated design and implementation of the digital Finite Impulse Response (FIR) filter. In this paper, the design and implementation of the FIR filter for processing the audio signal are obtained through the Field-Programmable Gate Array (FPGA) platform -Altera DE1 board. The design is divided into three primary blocks, which are the S2P Adapter block, Codec initialization block, as well as FIR filter block, which were then interfaced together; then, every block was compiled and simulated in order to obtain accurate results. The whole system was built to be functional, and finally, the frequency response was obtained. 100% significant accuracy and high quality are examined for implementing the filter in FPGA platform chip board programmed in (VHDL).

Minimum phase finite impulse response filter design

The design of minimum phase finite impulse response (FIR) filters is considered. The study demonstrates that the residual errors achieved by current state-of-the-art design methods are nowhere near the smallest error possible on a finite resolution digital computer. This is shown to be due to conceptual errors in the literature pertaining to what constitutes a factorable linear phase filter. This study shows that factorisation is possible with a zero residual error (in the absence of machine finite resolution error) if the linear operator or matrix representing the linear phase filter is positive definite. Methodology is proposed able to design a minimum phase filter that is optimal—in the sense that the residual error is limited only by the finite precision of the digital computer, with no systematic error. The study presents practical application of the proposed methodology by designing two minimum phase Chebyshev FIR filters. Results are compared to state-of-the-art methods from the literature, and it is shown that the proposed methodology is able to reduce currently achievable residual errors by several orders of magnitude.

High-performance, energy-efficient, and memory-efficient FIR filter architecture utilizing 8x8 approximate multipliers for wireless sensor network in the Internet of Things

IoT uses wireless sensor networks (WSN) to deploy many sensors to track environmental and physical parameters. The WSN measurements are frequently contaminated and altered by noise. The noise in the signal increases the sensor node’s computation and energy utilization, resulting in less longevity of the sensor node. The Finite Impulse Response (FIR) filter is commonly employed in WSN to pre-process sensed signals to remove noise from the sensed signals using delay elements, multipliers, and adders. Traditional multiplier-based FIR filter designs result in hardware-intensive multipliers that consume a lot of energy, and area and have low computation speed. These drawbacks make them unsuitable for IoT-based WSN systems with stringent power efficiency necessities. Approximate computing enhances the energy efficiency of an FIR filter. Arithmetic circuits utilizing approximate computing improve the hardware performance, with some loss of accuracy to save energy utilization and boost speed. A novel approximate multiplier architecture employing a fast and straightforward approximation adder is proposed in this study. Approximate multiplier M1 using OR gate and approximate multiplier M2 using proposed approximate adders are compared. The proposed approximate adder is suited for building an adder tree to accumulate partial product (PP) because it is less complicated than traditional adders. Compared to a one-bit-full adder, the critical path delay (CPD) is reduced significantly in the proposed methods. The accuracy comparison of M1. M2 and Wallace tree using the normalized mean error distance (NMED), the mean relative error distance (MRED), the maximum error (ME), and the error rate (ER) with the number of bits utilized for reducing error. For the area (delay) optimized circuit, when the bit used is 4, the delay is 0.4 ns for M1, 0.43 ns for M2, and 1.08 ns for the Wallace tree multiplier. For the delay (area) optimized circuit, when the bit used is 4, the delay is 0.16 ns for M1, 0.16 ns for M2, and 0.40 ns for the Wallace tree multiplier. To more accurately evaluate performance at the circuit level, the PDP and ADP are computed. The NMED, MRED, ME, and ER versus PDP and ADP are computed. The proposed multipliers M1 and M2 are compared with existing approximate multipliers. When an equivalent MRED, NMED, or ER is taken into account, M1 has the smallest ADP and PDP among other multipliers. The very low likelihood of a significant ED occurring is indicated by the small values of NMED and MRED in M1 and M2. The proposed solutions effectively reduce delay, area, and power while maintaining increased accuracy and performance.

FIR digital filter design based on improved artificial bee colony algorithm

The traditional swarm intelligence optimization algorithm is prone to fall into local optimal solutions in finite impulse response (FIR) digital filter design and has slow convergence speed. In order to optimize the design of FIR filter, a FIR digital filter design method based on improved bee colony (ABC) algorithm is proposed. This improved ABC algorithm can adaptively adjust the step size of the selected neighborhood of nectar source location. At the same time, the information of the global optimal solution is used to guide the search of candidate solution, which improves the global search ability of the algorithm. The improved ABC algorithm can balance the conflict between local search ability and global search ability, so it can achieve better optimization effect. The time and space complexity of the algorithm is analyzed in detail. Then, the improved ABC algorithm is used to design three typical FIR digital filters, namely low-pass, band-pass and band-stop filter. The performance of the designed filter is tested by simulation experiments. The experimental results show that compared with other state-of-the-art optimization algorithms, the proposed FIR filter design method has achieved better effect and performance. Meanwhile, the proposed design method has shorter optimization time. The superiority of the proposed method is verified.

A Low Complexity and High Modularity Design for Continuously Variable Bandwidth Digital Filters

ABSTRACT Digital filters with variable bandwidth can be used for a variety of applications. Arbitrary change in the bandwidth of a digital Finite Impulse Response (FIR) filter can be acquired using sampling rate converters. In this paper, a sampling rate converter is proposed which is generated from Pascal structure, a fractional delay filter having low hardware complexity and high modularity. The proposed sampling rate converter requires lesser number of multipliers for implementation when compared with the sampling rate converters in the literature. A low pass filter having a single bandwidth sandwiched between two sampling rate converters can contribute multiple bandwidths in such a way that each bandwidth is an arbitrary variation of the original bandwidth. A two stage Frequency response masking approach (FRM) is used for the hardware efficient design of the original low pass filter. A low complexity and high modularity novel design for a continuously varying bandwidth of a digital FIR filter is proposed in this paper using the proposed sampling rate converter. The modularity of the Pascal structure can be used to control both pass band ripple as well as stop band attenuation of the continuously variable bandwidth FIR filter design. Different communication standards in a Software defined radio (SDR) channelizer is realized using the proposed design of continuously variable bandwidth filter.

FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier

ABSTRACT The energetic growth in portable multimedia and mobile communication system has increased the requirement of high-speed signal processing system with compact area and power consumption. Finite impulse response(FIR) filters are broadly used in image, signal, speech and video signal processing, medical electronics, noise filtering, mobile communication and many other fields. The performance of the whole signal processing system with FIR filter depends on the basic building block of multiplier and adders. Hence, the hybrid FIR filter is proposed to improve the speed of the signal processing system using hybrid adder and hybrid multiplier. In this technique, the basic hybrid adder is designed with the help of 2-bit adders, BEC and 4:1 Multiplexer. Also, the hybrid multiplier is designed based on partial products of two consecutive multiplicand bits which are added at same time using Han-Carlson, Weinberger and Ling adder. The proposed FIR filter is functionally verified and synthesised using Xilinx ISE simulator and is implemented in Spartan 6 FPGA boards. The result shows that the delay of FIR filter using the proposed multiplier is improved by 26.51%, 15.59%, 15.83% and 2.79% as compared with CLA, conventional CSA, CSA-BK-BEC and the proposed adder with array multiplier, respectively.

Design and Implementation of Hybrid Techniques and DA-based Reconfigurable FIR Filter Design for Noise Removal in EEG Signals on FPGA

Virtual Reality (VR) technology assists physically challenged personnel in their daily routine activities. The evolution of technology has enhanced the critical activities of people who use wheelchairs by extracting features through electroencephalogram (EEG) and promoting options for their choice for decision-making on their own. During extraction of EEG, signal artifacts may mislead the decision-making environment. Hence noise has to be removed with help of an FIR filter for accuracy. In this context utilization of finite impulse response (FIR) filters are so vital hence filters are incorporated with the hidden Markov model (HMM) and Gaussian mixture model (GMM) and supervised machine learning architecture of multirate support vector machine (SVM). The proposed EEG-based diagnosis system is a fully automated audio announcement system. The entire environment has been developed by Verilog HDL and MATLAB. Validated on Artix-7 FPGA development board and synthesized with Vivado Design Suite 2018.1. Obtained results exhibit an enhancement of 32% of signal-to-noise ratio (SNR),7% of mean square error (MSE), and 69% of abnormality recognition.

Design and Implementation of 6-Tap FIR Filter Using MAC for Low Power Applications

Abstract: A Significant number of mathematical operations, such as multiplication and accumulation, are often required by a digital signal processing (DSP) algorithm. Many DSP applications have latency limitations, which mean that the DSP operation must be performed within a certain amount of time for the system to function, and because DSP gives high accuracy, filters constructed in DSP have tighter control over the output accuracy. As a result, DSP applications must be fast, have a high throughput, and use little power. Filters with a finite impulse response (FIR) are commonly employed in digital signal processing (DSP) applications. A FIR filter that is efficient in terms of electricity is being built. The multiplier and accumulator (MAC) unit used a new implementation approach to develop this system. FIR filter is a type of filter. Multipliers, adders, and a variety of other components are commonly used in FIR filters. Multipliers, adders, and a series of delays are used to form the filter's output in FIR filters. The goal of this project is to design and implement a 6-tap finite impulse response (FIR) filter by replacing multipliers with an 8-bit Multiplier and Accumulator (MAC) unit within the FIR filter, where a low-power MAC unit is always a key to achieving high performance in a DSP system, and D flip-flops are used in place of delays and constructed using a latch-based design. The Wallace tree Multiplier was utilised in the construction of the MAC unit because it reduces the amount of partial products, and the adders used for accumulation are half adders and full adders. In the FIR filter, for the purpose of summing This work evaluates performance of FIR filter in terms of speed and power and synthesis are executed in Xilinx Vivado 2018.1 software environment and the implementation is done using VHDL codes. The result analysis shows that the proposed FIR filter consumes low power than conventional (standard) FIR filter. As the dynamic power results up to 11.932W and after implementation it results up to 12.029W. Keywords: MAC, Low power, latch-based design.