FinFET CMOS Research Articles

A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm

A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm

A Compact, Low-Power, and Low-Jitter Fractional-N Phase-Locked Loop with a Single-Ended Ring Voltage-Controlled Oscillator in a 12 nm CMOS FinFET

PLLs with small areas, low power consumption, and low jitter are crucial for mobile applications. Hence, achieving a balance between the area, power consumption, and noise of a PLL is a significant issue. In this work, a compact, low-power, and low-jitter fractional-N PLL using Ring-VCO is introduced. In order to reduce area and power consumption, a single-ended Ring-VCO is implemented. Additionally, novel resistance matrixes are proposed to decrease phase noise. The resistor matrix creates 13 frequency tuning curves with close VCO gain and different initial frequencies, reducing the VCO gain and thus the overall noise while maintaining high tuning linearity. The proposed PLL is fabricated based on 12 nm FinFET technology with a 0.078 mm2 area. It achieves a 2.702 ps RMS jitter at 5.76 GHz while consuming 6.4 mW. Moreover, it maintains a low power consumption and a low RMS jitter across the entire frequency range.

Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS

Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS

Analysis and design of a 0.9 V 1 GHz-BW 14.6 dBm-OIP3 broadband receiver with current-mode analog baseband in 12 nm FinFET CMOS

This study introduces a wideband LNTA-based receiver employing full current mode (FCM) signal transmission, leveraging a broadband and highly linear current-mode analog baseband (CMAB). The CMAB module comprises a shunt feedback low pass filter and a programmable gain amplifier (PGA) with wide bandwidth, utilizing a regulated CG current mirror design, enriched by gm-boosting methodology and positive feedback capacitance reutilization through an identical boost amplifier. Fabricated in 12 nm FinFET CMOS process, the FCM receiver attains notable characteristics including a baseband bandwidth of 1 GHz, a conversion gain of 30 dB, a noise figure of 5.2 dB, and an OIP3 of 14.6 dBm, while operating with a low supply voltage of merely 0.9 V. Simulation results validate the efficacy of this FCM receiver for wideband communication, effectively addressing the linearity constraints associated with low supply voltages and maximizing the advantages of FinFET technology in current-mode signal transmission. The total layout area is 0.484 mm2.

A 16-Gb/s 3-tap adaptive DFE in 12-nm FinFET CMOS technology

This paper introduces a 3-tap half-rate adaptive decision feedback equalizer (DFE) and a 2-D eye-opening monitor (EOM). A newly developed regenerating sampler (RG-sampler) with smaller setup time and ck2q time is integrated into the proposed DFE, enhancing its performance. To ensure greater robustness, the sign-sign least-mean-squares (SSLMS) algorithm with a pattern filter is employed to adapt DFE tap coefficients. The proposed 2-D EOM accurately captures the shape of the eye diagram using adjustment steps of 1.95ps and 7 mV in the horizontal and vertical directions, respectively. Additionally, by reusing analog components within the adaptive DFE and 2-D EOM modules, significant reductions in silicon area and power consumption are achieved. Implemented in 12-nm FinFET CMOS technology, the transceiver integrated with adaptive DFE and 2-D EOM operates at a data rate of 16 Gb/s over a channel with 30 dB loss at 8 GHz frequency. The proposed adaptive DFE and 2-D EOM occupy a total area of 0.00808 mm2. Measurement results demonstrate that following DFE adaptation, the eye height is 77 mV, and the eye width is 29.25ps at 16 Gb/s.

A 16 Gb/s serial link transceiver with active inductor based CTLE and 3-tap DFE in 12-nm FinFET CMOS

This paper presents a 16 Gb/s serial link transceiver implemented in 12-nm FinFET CMOS technology. The equalization scheme incorporates a 3-tap feed-forward equalizer (FFE) in the transmitter, a 5-stage continuous time linear equalizer (CTLE), and a 3-tap decision-feedback equalizer (DFE) in the receiver. The proposed FFE structure offers small step size and flexible configuration. The CTLE's high-frequency boost is augmented by integrating an active inductor. A high-accuracy clock and data recovery (CDR) circuit, featuring a cascaded two-step analog phase interpolator (PI) structure, is developed for data retiming. Occupying a footprint of 0.26 mm × 0.63 mm per lane, the transceiver test chip is packaged in a flip chip ball grid array (FC-BGA) module. Measurement results demonstrate a horizontal eye opening of 38 % at a bit error rate (BER) of 10−12 over a channel with 28 dB loss at 8 GHz. Moreover, the power consumption is 68.85 mW per lane at 16 Gb/s.

High-density via RRAM cell with multi-level setting by current compliance circuits

In this work, multi-level storage in the via RRAM has been first time reported and demonstrated with the standard FinFET CMOS logic process. Multi-level states in via RRAM are achieved by controlling the current compliance during set operations. The new current compliance setting circuits are proposed to ensure stable resistance control when one considers cells under the process variation effect. The improved stability and tightened distributions on its multi-level states on via RRAM have been successfully demonstrated.

Design of synchronous frequency dividers in 5‐nm FinFET CMOS technology

AbstractA method is presented for the design of high‐speed frequency dividers in which the divided output signals are phase aligned by means of a scheme based on cascaded retiming. The objective of the design method proposed is to break the accumulation of propagation delay occurring in a divider chain that may limit the speed of the phase synchronization. Compared to alternative approaches where the phase synchronization is achieved with additional logical gates applied to the divider outputs, the authors’ approach only uses latches that are identical to those already employed in the divider chain itself without any additional synchronization logic. Hence, a better uniformity and homogeneity of the layout can be achieved, which helps improve the phase balancing. The method proposed to design synchronous dividers has been implemented in 5‐nm FinFET CMOS technology by means of a synchronous 8b‐counter providing the division factors 1/2 through 1/256. Its output phase synchronization has been verified in measurements at 10 GHz. The measured power consumption is 720 μW and the silicon area of the divider implemented is 79 μm2.

On-Chip Quantization- and Correlation-Robust Jitter Measurement for Low Phase Noise and High Frequency Oscillators

For on-chip oscillator phase noise characterization and monitoring a common technique is the measurement of the equivalent cycle-to-cycle jitter. In this letter we show that the quantization introduced to the recorded jitter by the measurement with a time-to-digital converter can be prohibitive for calculating the phase noise, especially at high oscillation frequencies and for spectrally pure oscillators. A second drawback of this method is that supply voltage noise can mask the phase noise due to intrinsic device noise. To avoid these limitations, we investigate an approach where the oscillator under test is compared to an identical replica. The resulting time difference measurements are introduced as delta jitter. The validity of the method is proven in simulation and measurement of an on-chip jitter measurement macro designed in 16 nm FinFET CMOS technology. The measurement results indicate both robustness against quantization error and a self-canceling of correlated influences on phase noise in delta jitter measurements.

A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS

This paper presents a 208-MHz, 0.75-mW selfcalibrated reference frequency quadrupler (RFQ), which provides a 4x higher reference clock with minimal deterministic frequency error. The digital-assisted calibration technique is exploited to compensate wide range of frequency and duty cycle errors and to reduce the noise degradation of analog calibration loop. Also, instead of utilizing a duty cycle corrector for 2x clock, reusing a delay cell reduces the power consumption by 50%. The fractional-N ring-PLL with the proposed RFQ was implemented in a 4nm FinFET CMOS process. The active area of the RFQ is 0.0175mm2 while the whole PLL occupies the area of 0.109mm2. By using the RFQ, the measured RMS-jitter of the PLL is definitely improved from 6.6ps to 3.35ps at 1.92GHz output frequency.

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

This article details the design and measurement of a digital-to-analog converter (DAC)-based source-series terminated (SST) transmitter (TX) for wireline applications in 4-nm FinFET CMOS technology. The DAC achieves 8-bit resolution and high analog output bandwidth by using a segmented architecture along with a single-ended LSB. Strength adjustment of the lower four DAC LSBs relative to the upper four DAC MSBs is accomplished with a hybrid analog/digital tuning approach, which overcomes minimum device-size limitations that can limit the effectiveness of pure digital tuning for SST drivers. The resulting DAC design achieves well-matched MSB/LSB segments with −0.63/0.67 LSB integral nonlinearity (INL) and −0.16/0.43 LSB differential nonlinearity (DNL). Time-domain modulation of 216-Gb/s PAM8 and frequency-domain modulation of 212-Gb/s orthogonal frequency-division multiplexing (OFDM) are reported, demonstrating the capability of CMOS DACs to support frequency-domain modulation for wireline applications. The TX consumes 288 mW from a 0.95-V power supply.

Effective Channel Mobility Extraction and Modeling of 10-nm Bulk CMOS FinFETs in Cryogenic Temperature Operation for Quantum Computing Applications

This article presents an extensive experimental investigation of transport properties in 10-nm CMOS Bulk FinFETs at cryogenic temperatures. The split-CV technique is employed to analyze the effective electron and hole mobilities from 300 to 10 K. Temperature and length dependence of effective mobilities is explored taking into account different scattering mechanisms. Hole mobilities were found to be dominated by temperature-independent neutral defects and surface scattering events for short-channel devices at low temperatures; while for electron mobilities, degeneracy effects at the cryo-temperature result in mobility enhancement at high fields. The short-channel devices show significant mobility degradation and weaker temperature dependence which could limit their utility for high-speed cryogenic-CMOS-based circuits. Variation of electrical parameters, such as subthreshold swing (SS), equivalent oxide thickness (EOT), threshold voltage, and effective length with temperature is also discussed. For accurately capturing the effective mobility trends in the specified temperature range along with the threshold voltage and SS trends, the existing BSIM-CMG 110.0.0 compact model equations are modified. The proposed model is validated across different device geometries of the short-channel bulk FinFETs fabricated with industry-standard 10-nm layout rules.

A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process

This paper presents a 2 × VDD mixed-voltage digital output buffer where its slew rate (SR) is automatically adjusted based on PVT (process, voltage, and temperature) detection. The developed buffer is the first to be fabricated using TSMC 16-nm CMOS Logic FinFET Compact (Shrink) LL ELK Cu 1P13 M process. Since slew rate is one of the major required parameters in many interfacing protocols, it is really hard to meet if the mixed-voltage output buffer is needed in FinFET processes. The major reason is the low VDD in these advanced processes. However, our buffer's SR is improved by implementing low threshold voltage (Vth) type of device for always-on driving transistors in the Output Stage, thereby increasing the output current. Moreover, since FinFET devices were used in the buffer, the stability of the gate drives of the said driving transistors must be ensured so that noise interference will be avoided. Lastly, the buffer's Timing Shifters used non-overlapping signaling control directly implemented at the transistor level to eliminate the errors caused by delay variations. Based on silicon measurement results, at a load capacitance of 20 pF, the said circuit can be operated at a maximum data rate of 250 MHz for both supply voltages of 0.8 and 1.6 V (namely external VDD or VDDIO), respectively. When the SR auto-adjustment is activated, the SR improvement is at least 49.2% and 37.5% for 0.8 and 1.6 V, respectively.

Experimental study on real-time measurement of single-event effects of 14 nm FinFET and 28 nm planar CMOS SRAMs based on Qinghai-Tibet Plateau

Based on the Yangbajing International Cosmic Ray Observatory in Lhasa with an altitude of 4300 m, a long-term real-time experiment is carried out in order to measure the atmospheric radiation induced soft errors in 14 nm FinFET and 28 nm planar CMOS SRAM array. The underlying mechanisms are also revealed. Five boards are used in the test, four of which are equipped with 28-nm process devices, and one board is equipped with 14-nm process devices. After removing the unstable bad bits, the actual effective test capacity is 7.1 Gb. During the test, the on-board FPGA reads the stored contents of all the tested devices in real time, reports the error information (occurrence time, board number, column number, device number, error address, error data) and corrects the error. The duration of the test is 6651 h. A total of 56 single event upset (SEU) events are observed, they being 24 single bit upset (SBU) events and 32 Multiple Cell Upset (MCU) events. Based on previous results of 65-nm SRAM, the study finds that SER continues to decrease with the reduction of process size, but the proportion of MCU in 28-nm process devices (57%) exceeds SBU, which is a process “maximum point” of MCU sensitivity, and the maximum size of MCU is 16 bits. Although the Fin spacing of the 14-nm FinFET device is only about 35 nm, and the critical charge decreases to sub-fC, the introduction of the FinFET structure leads to the change of charge collection and the sensitive volume sharing mechanism , and the shallow trench isolation leads to the narrowing of the charge diffusion channel. On the other hand, the surface area of the sensitive volume decreases to 0.0024 μm<sup>2</sup>, resulting in a significant decrease in the soft error rate of both SBU and MCU in the 14-nm process.

Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications

This article presents a high throughput and low routing complexity multiframe pipelined low-density parity check (LDPC) decoder design based on a novel pseudo marginalized min-sum (PMMS) message passing approach. The proposed PMMS approach reduces the required number of interconnections in the routing network allowing the design to be implemented with reduced hardware complexity, low power consumption and high throughput capability while supporting multiple coding rates with short and long codewords as defined in many application standards. Implementation results for IEEE802.11ad/ay standards show that the proposed design satisfies a target bit error rate (BER) requirement of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3 \times 10^{-7}$ </tex-math></inline-formula> with 64 quadrature amp mod (QAM) targeting high throughput applications. Furthermore, the proposed design is able to achieve a throughput of 62 and 101.8 Gb/s with two pipelining stages under 28-nm CMOS and 16-nm FinFET CMOS process, respectively. As compared to the existing NMS algorithm, the proposed design based on the PMMS approach reduces the number of wires in the routing network by 45.5%, and the wirelength of the overall decoder by 17%. The area and power consumption are also reduced by 9.4% and 12%, respectively, as compared to the conventional normalized min-sum (NMS) algorithm.

3-D Monolithic Stacking of Complementary-FET on CMOS for Next Generation Compute-In-Memory SRAM

Monolithic 3D stacking of complementary FET (CFET) SRAM arrays increases integration density multi-fold while supporting the inherent SRAM advantages of low write power and near-infinite endurance. We propose stacking multiple 8-transistor CFET-SRAM layers on regular CMOS periphery to achieve an ultra-high-density array for computing-in-memory (CIM). CFET and regular CMOS (FinFET) devices are measured and calibrated with BSIM-CMG compact model. SPICE simulations are performed to evaluate the delay of CIM operation, power consumption, and analog computational error due to device non-linearity. The impact of device non-linearity on neural network inference accuracy is evaluated using the CIMulator simulation platform. Lower CFET current drive due to amorphous (deposited) silicon channel is shown to have negligible impact on CIM operational delay in many cases, as the maximum allowable current is limited by wiring resistance, not transistor drive strength while maintaining accurate weighted sum. Compared to regular 2D CMOS FinFET array. CFET SRAM cells show an improvement up to 57.19% in TOPS/W. Furthermore, the performance in TOPS/W mm 2 is improved up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$19\times $ </tex-math></inline-formula> . A factor proportional to the number of stacked layers for monolithically stacked CFET SRAM cells, makes it highly promising for future edge intelligence.

A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET

The world’s first 5-carrier aggregation (CA) supporting digital-intermediate frequency (IF) receiver (RX) to support 5G sub-6 GHz new radio (NR) and CA/E-UTRA NR dual connectivity (CA/EN-DC) maintaining 2G and 3G in 14-nm FinFET CMOS technology is presented. Three digital-IF RXs with a shared local oscillator-phase-locked loop (LO-PLL) are integrated for supporting inter-/intra-band 5-CA to reduce power consumption and area of the massive number of RX paths. The RX features nine single-ended low-noise amplifiers (LNAs) with low/mid/high band (L/M/HB) characteristics. It achieves noise figure (NF) of 1.5 dB with 18 dB external LNA gain and +7.6-dBm out-of-band (OOB) input intercept point 3 (IIP3), and input intercept point 2 (IIP2) calibration is not required thanks to IF planning. The RX achieves an error vector magnitude (EVM) of 2.5% by intra-4CA for B1 LTE10MHz and LTE20MHz in one single RX path, as well as inter-3CA for B3, B5, and B7 long-term evolution (LTE) 20 MHz with a shared LO-PLL. The estimated power saving by sharing a single LO-PLL is 17% compared to 3-CA RXs with three separate LO-PLLs.

Benchmarking Power Delivery Network Designs at the 5-nm Technology Node

We evaluate a total of 96 different power delivery designs for a 5-nm node FinFET CMOS technology using eight levels of interconnect wiring. Our methodology considers the impact of a given design on the gate delay of an inverter as a figure of merit, while highlighting the tradeoff between power grid density and signal track density. Our design space includes designs with variable power line pitch at multiple levels of interconnect wiring as well as designs with continuous power rails replaced with power staples, covering both low-power and high-performance design points. We also evaluate the impact of the proposed technology features, such as skip-level vias and wafer front-side power rail removal. This work demonstrates the importance of power delivery design in advanced technology nodes and proposes a useful methodology for benchmarking designs as well as technology elements early on in a technology development cycle, ahead of more involved analysis such as plane-and-route.

A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC

This article presents an 8-bit time-domain analog-to-digital converter (ADC) achieving ten-GS/s conversion speed with only two time-interleaved (TI) channels. A successive approximation register (SAR) time-to-digital converter (TDC) is implemented for the subpicosecond resolution time quantization with high power/area efficiency and low jitter. The throughput of the SAR TDC is enhanced by a unique delay-tracking pipelining technique to enable a 5-GS/s single-channel conversion. On the circuit level, the reference time generation for the SAR TDC is realized by the proposed selective delay tuning (SDT) cell for high efficiency and small reference time variation. Fabricated in the 14-nm FinFet CMOS technology, this ADC achieves a 37.2-dB signal-to-noise and distortion ratio (SNDR) and a 50.6-dB spurious-free dynamic range (SFDR) at the Nyquist input frequency, leading to a 24.8-fJ/conv-step Walden figure of merit with an active area of only 2850 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}^{2}$ </tex-math></inline-formula> .

Perspectives on How the "Sige, Ge, & Related Compounds: Materials, Processing, and Devices" Field Has Changed over the Last 20 Years

The field of electronic devices and materials has seen major changes over the last ~20 years. The SiGe, Ge, & Related Compounds: Material Processing, and Devices symposium has documented much of this change. In 2004 the meeting grew out of a desire for the ECS to have a special ongoing symposium on SiGe & Ge as a materials system with increasing importance in silicon semiconductor technology. In 2008 the symposium was expanded to include Ge and Related compounds including SiC and III-Vs on Silicon to recognize the important work in these areas. In 2010 the symposium was expanded to include work in nano-wires, nano-membranes, and light emitting structures with SiGe and/or Ge. In 2012 the symposium explored finfet devices and expanded to include the area of GeSn. In 2014 the symposium explored the use SiGe and related compounds in more complex and advanced structures. In 2016 the conference had a theme around SOI and the FDSOI technology in particular. In 2018 the themes were the ever expanding device structures and role epitaxy has played in it.Each year the plenary talks were selected to give a view of the industry and the conference. These talks give us insight into the symposium and how the field has changed over time.In 2004 the first symposium “SiGe 1: Materials, Processing, and Devices” focused on the SiGe HBT transistor performance and SiGe epitaxial technology. But CMOS scaling was also presented. These trends were reflected in the plenary talks were given by John Cressler on “Using SiGe HBTs for Mixed-Signal Circuits and Systems: Opportunities and Challenges” and Judy Hoyt on “Enhanced Mobility CMOS.” This was the first symposium and we set the conference organization with multiple topical committees and published the first proceedings.In 2006 the “SiGe and Ge 2” symposium continued the themes of SiGe and Ge Epitaxy, SiGe HBT, CMOS scalling, and added silicon photonics. The Plenary talks were given by Dimitris Antoniadis on “Channel Material Innovations for Continuing the Historical MOSFET Performance Increase with Scaling” and Cary Gunn on “CMOS Photonics for High Speed Interconnects.”In 2008 the “SiGe, Ge, & Related Compounds 3” symposium changed in composition bringing IIIV and other compounds into the symposium. The Plenary papers were by Krishna Saraswat on “Germanium for High-Performance MOSFETS and Optical Interconnects,” and Wiebe B. de Boer on “Si and SiGe Epitaxy in Perspective.” Krishna focused on the role of Ge in modern devices and Wiebe focused on the history of SiGe epitaxy at ASM.In 2010 the “SiGe, Ge, & Related Compounds 4” greatly expanded topics while maintaining the core of SiGe HBT and CMOS scaling. The plenary papers were given by K. Kuhn on “Past, Present, and Future: SiGe and CMOS Transistor Scaling” and L. Kimmerling on “Scaling Energy and Form Factor with Germanium Microphotonics.” The conference emphasis continued on SiGe epitaxy, CMOS scaling, and HBT performance with a new optoelectronics focus area.In 2012 the “SiGe, Ge, & Related Compounds 5” focused on the finfet and GeSn. The plenary papers were given by E. Nowak “Advanced CMOS scaling and FinFET Technology” and C. Hu on “FinFET and UTB – How to make very short channel MOSFETs.” There were 4 sessions containing papers with GeSn.In 2014 the “SiGe, Ge, & Related Compounds 6” returned to CMOS scaling and the SiGe HBT. The plenary papers were given by K. Uchida and T. Takahashi on “Extending the FETs: Challenges and Opportunities for New Materials and Structures” and L. Zimmermann (IHP) on “High-Performance Photonic BiCMOS – Next Generation More-than-Moore Technology for the Large Bandwidth Era.”In 2016 the “SiGe, Ge, & Related Compounds 7” focused on FDSOI. The plenary papers were given by Bruce Doris “FDSOI Past, Present and Future” and Carlos Mazure and S. Cristoloveanu “ FD-SOI: The History from Early Transistors to Today.”In 2018 the “SiGe, Ge, & Related Compounds 8” focused on CMOS scaling and SiGe as an enabling material. The plenary papers were given by Maszara, Witold on “Contemporary and Future Logic Devices” and by Tsu-Jae Liu on “ Silicon-Germanium: Enabler of Moore's Law.”In 2020 the “SiGe, Ge, & Related Compounds 9” symposium focused on III-Vs and Silicon Photonic Sensors. The plenary papers were given by N. Collaert on “The revival of compound semiconductors and how they will change the world in the 5G/6G era,” and Ben Miller on “Creating the Interface Universe between the Universe and Data with Integrated Photonic Sensors."Highlights from these plenary talks and symposium topics will be presented.