Fine-pitch Solder Bumps Research Articles

Electrochemical Express Analysis of Organic Additives in Lead-Free Wafer Level Packaging Plating Baths

Semiconductor packaging migrated from wire bond to flip chip level interconnect to meet size, weight and electrical performance requirements. Lead-free alloys for flip chip attachment has become a common material in electronics. Alloys containing Sn and Ag as well as pure Sn are the most common ones. The mechanical strength, wetting, and fatigue resistance of these alloys and pure Sn is either comparable or surpass lead contained alloys. Electroplating with lead-free alloys is the most desirable technique due to its low cost and usefulness in building fine pitch solder bumps [1].The new generation of lead free plating systems targeting faster deposition rates, better uniformity with-in die and longer bath life. The co-deposition of elements may be complicated by the large difference in the electrode potentials of tin and alloying metals (e.g. silver, bismuth). To produce uniform and dense deposits, these plating baths include organic additives that are typically separated for two groups with different functions: polarizers that significantly affect the plating rate and control the uniformity of deposit; and grain refiners [2]. For desired properties of deposit, the bath components must be kept within specific concentration ranges. In some cases, the analytical results for bath components should be available more frequently in order to provide feedback to dosing system [3]. To develop most accurate and repeatable analytical methods, the interactions between lead free plating bath components were previously investigated and understood [2]. That allowed to develop efficient analytical techniques for analysis of lead free plating bath components. However, faster analytical methods are required for control of high speed plating baths. The effect of changes in the concentration of organic components on the structure of deposit were studied more recently and will be reported in this work.When the speed of analyses increases, it is critical to keep reproducible state of all electrodes. Therefore, new regeneration method for electrodes was developed. For development of new express analytical methods, we utilized an electrochemical cell with three electrodes connected to a potentiostat/galvanostat. RDE working and counter platinum electrodes were used as well as Ag/AgCl double junction reference electrode. It has been found that multiple factors can reduce the speed of electrochemical analysis. One of the most potent parameters that affect speed of analysis was a scan rate. Fig. 1 shows the electrochemical responses of polarizer at different scan rates.Other parameters and steps of analysis were also evaluated for potential reduction the analysis time. This presentation will provide more information related to the electrochemical behavior of organic additives at specific conditions when the analysis is performed with different speed. Results for other bath components will be also presented. The concentration of inorganic components and silver complexing agent can be determined via non-reagent and virtually real time spectroscopic analytical methods. The presentation will be concluded with a discussion of analytical results for several organic additives at different concentration levels.

Study of Intermetallic Growth and Kinetics in Fine-Pitch Lead-Free Solder Bumps for Next-Generation Flip-Chip Assemblies

With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 μm to 150 μm. With this reduction in pitch size, and thus in bump height and diameter, the interaction between die pad metallurgy and substrate pad metallurgy becomes more critical due to the shorter diffusion path and greater stress. Existing literature has not addressed such metallurgical interaction in actual fine-pitch flip-chip assemblies. This work studies intermetallic growth and kinetics in fine-pitch lead-free solder bumps through thermal aging of flip-chip assemblies. Based on this study, it is seen that Ni from the die pad diffuses to the substrate pad region and Cu from the substrate pad diffuses to the die pad region, thus the resulting intermetallic compounds at the die and substrate pad regions are influenced by the other pad as well. Such cross-pad interaction is much stronger in fine-pitch solder bumps with smaller standoff height. It is seen that the die pad region contains Ni3P and (Cu,Ni)6Sn5 after thermal aging, while the substrate pad region contains Cu3Sn and (Cu,Ni)6Sn5. By digitally measuring the thickness of the interfacial phases, the kinetics parameters and the activation energy were calculated for the growth of (Cu,Ni)6Sn5 on the substrate side. The Cu diffusion coefficient through the intermetallic compound (IMC) layer was found to be 0.03370 μm2/h, 0.1423 μm2/h, and 0.4463 μm2/h at 100°C, 125°C, and 150°C, respectively, and the apparent activation energy for the growth of compound layers was 67.89 kJ/mol.

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

The effect of solder bump pitch on the underfill flow

An underfill encapsulant was used to fill the gap between the chip and substrate around solder joints to improve the long-term reliability of flip chip interconnect systems. The underfill encapsulant was filled by the capillary effect. In this study, the filling time and pattern of the underfill flow in the process with different bumping pitch, bump diameter, and gap size were investigated. A modified Hele-Shaw flow model, that considered the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. This model estimated the flow resistance induced by the chip and substrate as well as the solder bumps, and provided a reasonable flow front prediction. A modified model that considered the effect of fine pitch solder bumps was also proposed to estimate the capillary force in fine pitch arrangements. It was found that, on a full array solder bump pattern, the filling flow was actually faster for fine pitch bumps in some arrangements. The filling time of the underfill process depends on the parameters of bumping pitch, bump diameter, and gap size. A proposed capillary force parameter can provide information on bump pattern design for facilitating the underfilling process.

Aspects of Indium Solder Bumping and Indium Bump Bonding Useful for Assembling Cooled Mosaic Sensors

Indium solders are frequently used for interconnections in cooled systems because of their high ductility down to very low temperatures. Very fine contact pitches are required for hybrid mosaic radiation sensors compared with those for conventional flip‐chip technology. This paper presents solutions for bumping and bonding indium bumps based on the measured properties of indium solders in relation to the requirements of, and possibilities for, manufacture of fine pitch solder bump features.