Fine Pitch Flip Chip Packages Research Articles

Effects of Commercial No-Clean Flux on Reliability of Fine Pitch Flip-Chip Package With Solder Bumps and Copper Pillars

In this work, two commercial no clean fluxes, namely, extremely low residue no-clean flux (NCF) (NC-1) and ordinary NCF (NC-2), were used for the preparation of a fine pitch flip-chip package with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.6\,\times \,7.6$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Si die on a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$17\,\times \,17$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> organic substrate. One water-soluble (WS) flux was also used for comparison. Moisture sensitivity of the package was evaluated using JESD22-A113D (30 °C/60% relative humidity (RH), 192 h, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> reflow at 260 °C). Thermal cycling tests were performed following JESD22-A104D (−65 °C to 150 °C). The high-temperature storage life (HTSL) of the packages was investigated using JESD22-A103C (175 °C). Underfill delamination or voids in the package were investigated by confocal scanning acoustic microscopy (C-SAM). Failure characteristics of the packages were also studied using scanning electron microscopy (SEM). After moisture sensitivity level (MSL) test, vehicles prepared by NC-1 and NC-2 showed failure. SEM images revealed severe delamination between underfill and solder mask in the presence of amine/amide and carboxylic acid-based NCF residue. Solder bump crack were found at < 500 cycles for samples prepared with NC-1 which contains tertiary amine and long carbon chain (C8:C10:C12) carboxylic acid-based. However, failure occurred at < 1500 cycles for NC-2 containing secondary amide and shorter carbon chain length (C3) carboxylic acid. Samples prepared using WS did not show any failure for up to 2000 cycles. Thus, NCF-treated assemblies performed poorly in moisture sensitivity and temperature cycling tests.

Investigation Into Chemistry and Performance of No-Clean Flux in Fine Pitch Flip-Chip Package

This study investigates the chemistry and performance of two commercial no-clean fluxes (NCFs) ii.e., NC-1 and NC-2. One water-soluble (WS) flux was also studied for comparison. Chemistry of these fluxes and their residues was studied using the Fourier transmission infrared (FTIR) spectroscopy. Thermal behavior of the flux was evaluated using differential scanning calorimetry (DSC) and thermogravimetric analysis (TGA). Hygroscopicity of the residue was determined using water contact angle on residue-contaminated substrates. These fluxes were used to prepare fine pitch (<inline-formula> <tex-math notation="LaTeX">$150~\mu \text{m}$ </tex-math></inline-formula>) flip-chip package (<inline-formula> <tex-math notation="LaTeX">$17\times17$ </tex-math></inline-formula> mm²) containing solder bump and copper pillar. Performance of each flux was evaluated using wettability of preprinted SAC-305 solder on copper substrate. Die pull strength of solder bump was evaluated and failure mode was analyzed using scanning electron microscopy (SEM). FTIR results showed that carboxylic acids, tertiary amine, and ether were present in NC-1. Carboxylic acid, secondary amide, and ether were observed in NC-2. WS showed the presence of carboxylic acid, secondary amine, ether, and alcohol. Residue showed the presence of carboxylic acid and amine in NC-1 and only amide in NC-2. Evaporation of certain monocarboxylic acids and ether solvent in NCF led to minimal residue compared to WS. Residue of WS was highly hygroscopic compared to N CF. Wetting of solder bump prepared by using NC-1 and NC-2 was better than WS, which is related to flux chemistry. Consequently, higher die pull strength was observed for N CF.

Effects of cooling rate and joint size on Sn grain features in Cu/Sn–3.5Ag/Cu solder joints

In Sn-based micro solder joints for fine pitch flip chip or 3D packaging technologies, the number of Sn grains is always limited and sometimes only one Sn grain exists in a joint, which inevitably causes anisotropy in the performance and reliability of micro interconnection. It is known that the parameters of solder joint structure and reflow process, especially cooling stage, have a great significance for regulating the features of Sn grains after soldering. Hence, in the present paper, the Sn grain features of Cu/Sn–3.5Ag/Cu solder joints with different joint sizes (300 μm, 100 μm and 50 μm) solidified under different cooling rates (1.5 °C/s, 0.5 °C/s and 0.1 °C/s) were studied. Generally, the number of Sn grains decreased as the joint size decreased. When the joint size was 50 μm, the solder joints tended to contain only one or two Sn grains irrespective of the cooling rate. Furthermore, cooling rates greatly affected the number and orientation of Sn grains as well as the growth of large Ag3Sn intermetallic plates to varying degrees. The formation of Sn grains and Ag3Sn plates was discussed from the viewpoint of nucleation under different conditions.

A Study of Low-Cost Sequential Electroplating Bumping Process and its Metallurgical Behavior

Studies were conducted to validate from a metallurgical point of view whether a lower cost sequential plating approach to SnAg and SnAgCu (SAC) solder bumping is a suitable alternative to the conventional alloy plating process. A range of Ag content corresponding to typical bump applications was explored with respect to Ag diffusion and intermetallic compound (IMC) formation. Variables that can affect such IMC formation were further explored as a function of underbump metallization (UBM) structure and cooling rate during bump solidification. By comparing the results to those previously reported on SnAg-based alloys, it is demonstrated that the proposed sequential plating process produces very similar microstructures and Ag3Sn IMC morphologies, due to the rapid diffusion and distribution of Ag through the liquid Sn. Known means to mitigate the less desirable large Ag3Sn platelets, that is by changing the top UBM layer from Cu to Ni or by employing an ultrarapid cooling rate, are shown to be equally effective for sequential plating. These observations, in conjunction with the simplicity and flexibility of plating multiple single metals, propose adoption of the sequential plating process as a cost-effective and robust Pb-free bumping solution for fine pitch flip-chip packaging.

Effects of Cooling Rate and Joint Size on Sn Grain Features in Cu/Sn-3.5ag/Cu Solder Joints

In Sn-based micro solder joint s for fine pitch flip chip or 3D packaging technologies , the number of Sn grains is always limited and sometimes only one Sn grain exists in a joint, which inevitably causes anisotropy in the performance of micro interconnection. It is known that the parameters and reliability of solder joint structure and reflow process, especially cooling stage, have a great significance for regulating the features of Sn grain s after soldering. Hence, in the present paper, the Sn grain features of Cu/Sn-3.5Ag/Cu solder joints with different joint size s (300 μm, 100 μm and 50 μm) solidified under different cooling rate s (1.5 °C /s, 0.5 °C /s and 0.1 °C /s) were studied. Generally, the number of Sn grains decrease d as the joint size decrease d . When the joint size was 50 μm, the solder joints tended to contain only one or two Sn grains irrespective of the cooling rate. Furthermore, cooling rates greatly affected the number and orientation of Sn grains as well as the growth of large Ag3Sn intermetallic plates to varying degrees. The formation of Sn grains and Ag 3 Sn plates was discussed from the viewpoint of nucleation under different conditions.

Development and optimization of the laser-assisted bonding process for a flip chip package

In a fine pitch flip chip package, a laser-assisted bonding (LAB) technology has recently been developed to overcome several reliability and throughput issues in the conventional mass reflow (MR) and thermal compression bonding technology. This study investigated the LAB process for a flip chip package with a copper (Cu) pillar bump using numerical heat transfer and thermo-mechanical analysis. During the LAB process, the temperature of the silicon die was uniform across the entire surface and increased to 280 °C within a few seconds; this was high enough to melt the solder. The heat in the die was quickly conducted to the substrate through the Cu pillar bumps. Meanwhile, the substrate temperature was low and remained constant. Therefore, a stable solder interconnection was quickly achieved with minimal stress and thermal damage to the package. The substrate thickness, the number of Cu bumps, and the bonding stage temperature were found to be important factors affecting the heat transfer behavior of the package. The temperature of the die decreased when a thinner substrate, a higher number of Cu bumps, and a lower bonding stage temperature were used. If the temperature of the die was not sufficiently high, insufficient heat was transferred to the solder to melt it, resulting in incomplete solder joint formation. Thermo-mechanical analysis also showed that the LAB process produced lower warpage and thermo-mechanical strain than the conventional MR process. These results indicated that a LAB process using a selective local heating method would be beneficial in reducing thermo-mechanical stress and increasing throughput for the fine pitch flip chip packages.

Invar Electroplating for Controlled Expansion Interconnects

The current trends in convergent systems are to pack as many functions – digital, RF, optical, MEMS, LEDs, and other IoT devices – into a single package or module and current methods of metallizing the ever-shrinking components are rapidly becoming insufficient. A new set of metallization material technologies is necessary to meet these increasing expectations, methods that not only work with the substrates and materials of yesterday but are also ready for the future. The copper that is currently the workhorse of interconnect materials has a coefficient of thermal expansion (CTE) of 17 ppm/K while chip substrates’ CTE ranges from 2 to 7 ppm/K. The thermo-mechanical stresses induced in the package from the CTE mismatch between the die, the substrate and the buildup materials result in solder joint failure, die cracking, copper extrusion, delamination of the solder bumps and cracking of the build-up layers, leading to failure of the assemblies. Matching the CTEs of the chips and the substrates is required for future fine-pitch flip chip and wafer level package assembly in order to improve the solder joint reliability and fabricate stress-free 3D multichip systems. NANO3D Systems has developed an electroplating technique to produce uniform, low-internal-stress and controlled-expansion nickel iron alloy (INVAR) films deposited on different substrates, fabricating redistribution layers (RDL), through silicon vias (TSV), pillars, and free standing foils. INVAR electroplating was performed using a proprietary plating solution containing stabilizers that prevent the oxidation of iron, stress-reducers to reduce internal stress, and wetting agents to improve the surface morphology and eliminate pinholes. The thermal (thermal conductivity, linear thermal expansion, specific heat capacity) and mechanical (Young’s modulus, yield strength, tensile strength and internal stress) properties of the INVAR have been studied and demonstrated superior performance compared to currently available similar products. The composition of the INVAR (36 % of Nickel and 64% of Iron) electroplated films has been confirmed by utilizing SEM/EDX and SIMS. Linear thermal expansion of the films was tested using a technique based on bending of bonded layers due to thermal stress. Internal stress was studied using bent strip techniques. The linear thermal expansion down to 0.4±0.1 (x10-6, K-1) has been obtained for the INVAR plated films plated within a process window that corresponded to the lowest internal stress (30±2 (MPa)) and uniform morphology (Ra ~ 2 nm). The mechanical properties of the INVAR foils have been investigated by use of the Instron technique. The tensile strength of 500 ± 60 (MPa), yield strength of 280 ± 50 (MPa) and the ductility of 40 ± 10% have been measured for the pinhole-free INVAR films. The specific heat capacity of 0.45 ± 0.05 (J/gK)was measured by using differential scanning calorimetry (DSC) at 573 K, while thermal conductivity of as-plated INVAR was 43 ± 5 (W/mK). Smooth, uniform and flat RDL & pillars were fabricated by using through resist INVAR plating on silicon wafers. Optical profilometry studies of the morphology and thickness of plated INVAR on the silicon wafers show Ra ~ 2 nm and high thickness uniformity (of about 5 % & 3s). TSV fill of high aspect ratio features (>10:1) was also demonstrated. After being annealed at 300 0C for 2hr, SIMS studies showed no inter-diffusion in copper/Invar bi-layer foils. Trace impurities were <100 ppm in electroplated INVAR films. Analytical methods have been developed for plating solution analysis. UV-VIS and titration are the two main techniques employed for analysis of metals, organic acids, and buffers in solution. Standard curves were created by analyzing solutions with known concentrations of each analyte. Solutions of varying concentrations were prepared for analysis; low control limit (low), target, and upper control limit (high) concentrations. Blank solutions contained all components except for the one of interest. There was also a blank prepared with no metals at all to be used as the reference in UV-VIS analysis. Multiple analyses were collected for the standard solutions in order to perform a statistical analysis and confirm p/t <0.3. Using the standard curves concentrations of unknowns (active bath solutions) were calculated. The plating additives in INVAR electroplating bath such as stress-reducer, stabilizer and wetting agents were monitored by using cyclic voltammetric stripping (CVS) and FTIR techniques.

Thermal modeling approach for enhancing TCNCP process for manufacturing fine pitch copper pillar flip chip packages

Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being primary drivers for devices like smart-phones and tablets. Today solder interconnect pitches, for both low-end and high-end flip chip applications, approximately range from 200μm to 90μm in area array. Advanced silicon nodes create challenges to fine pitch flip chip interconnects and corresponding substrate technology. Fine pitch (&amp;lt;60μm pitch) flip chip (FPFC) packaging is an emerging technology that meets the demand for both smaller form factors and lower cost products. Copper pillar bumps are best suited for fine pitch applications because they allow low standoff height and robust package reliability. Previous feasibility studies show that thermo-compression bonding process with non-conductive paste (NCP) is well suited for manufacturing copper pillar based FPFC packages because the NCP paste encapsulates the bumps and protects the vulnerable die interconnects. TCNCP process can be described as (1) NCP paste is pre-dispensed on a substrate (2) bumped die is picked up by the heater tool (3) proper heating profile and compression load is applied and (4) heater tool detaches and die is allowed to cool. This process requires precise control of temperature and force to get robust flip chip interconnect shape and void-free NCP coverage. TCNCP process has very small heating times usually ranging between 2 to 4 seconds per die. Within such short time, the heater temperature is quickly ramped up to 3 times its initial temperature to melt the solder at the tip of the copper bumps and cure the NCP. Small package layers make it very difficult for the heat to spread quickly. Therefore any temperature gradients within the heater are propagated into the die. Large temperature gradients within the die can potentially introduce manufacturing related challenges like solder “non-wet” and “de-wet”. In this paper these issues are briefly discussed. An experimentally validated thermal model is presented to develop an understanding of rapid heat flow patterns during a typical TCNCP process. Detailed parametric computational study is performed on different die sizes, heating temperature and time to propose a broad guideline on achieving optimal temperature distribution during the TCNCP process.

Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages

Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance. Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.

Under bump metallurgy study on copper/low-k dielectrics for fine pitch flip chip packaging

Because the semiconductor speed increases continuously, more usage of low-k dielectric materials to enhance the performance in Cu chips has taken place over the past few years. The implementation of copper (Cu) as an interconnect, in conjunction with the ultra-low-k materials as interlevel dielectrics or intermetal dielectrics in the fabrication of ultra-large-scale integrated circuits, has been used in the semiconductor community worldwide, especially for high-speed devices. The objective of this study is to investigate the under bump metallurgy (UBM) characterization with low-k dielectric material used in damascene Cu-integrated circuits. This paper focuses on electroless Ni/Au, Cu/Ta/Cu, and Ti/ Ni(V)/Cu/Au UBM fabrication on 8-in. damascene Cu wafers and flip chip package reliability with Pb-bearing and Pb-free solders. The interfacial diffusion study and bump shear test were carried out to evaluate the bump bonding, and the failure was analyzed with optical microscopy, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). In order to investigate the thermal stability of the UBM system with Pb-free solder, high-temperature aging (above the melting temperature) was performed and each interface between the solder and UBM was observed with optical microscopy, SEM, and TEM, respectively. The failures observed and the modes are reported in the paper.

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.