Fine Pitch Assembly Research Articles

Nanoporous Cu-Sn Intermetallic Material for Interconnects in Electronic Packaging

Nanostructured and nanoparticulate Cu-based materialshave emerged as viable replacements of conventional solder materials for realizing high-performing and reliable interconnection in today's 2.5D/3D electronic packaging. Unlike the traditional interconnects, those materials offer better compliance during the overall packaging routines. Owing to their highly developed surface area resulting of their uniform interconnected porosity, said nanomaterials also enable joint formation by sintering by thermal compression realized at high pressure and at much lower temperatures compared to bulk counterparts. Recently, sintering of nanoporous (np) Cu was demonstrated under high pressure and temperature after initial pre-treatment in acid for surface oxide removal. Separately, other studies have been focused on the attachment of Cu pillars to pads by using nanoparticulate Cu pastes as sintering material. The ultimate goal is to develop materials that facilitate a highly effective and durable chip-to-substrate interconnection.In this report, we discuss the development and use of nanoporous uniform and continuous CuSn films for low-temperature joint formation. The novelty of this work is realized through the introduction of tin (Sn) to work along with the np-Cu structure for ensuring lower sintering temperatures with a goal of producing packaging interconnects based on CuSn intermetallic compound (IMC). The addition of Sn to the np-Cu system is performed using a bottom-up, all-electrochemical synthetic approach (see Figure 1). The method is founded on the initial synthesis of thin films of np-Cu by dealloying of Cu-Zn alloys, followed by a conformal coating with a thin layer of Sn. The main goal of the proposed approach is to form a np-CuSn composite that upon sintering at high temperature and pressure, transitions into a densely compressed Cu3Sn IMC bonding material. Realized accordingly as interconnect layer, said material ensures good stability at high current densities (greater than 1×105 A ⋅ cm2 ) and low electrical resistivity (equal or less than 8.5 µΩ ⋅ cm).The synthetic details and then the applicability of the Cu-Sn nanomaterials obtained using the approach for synthesis of a low-temperature joint formation material are also discussed. The Sn-coating process was administered by galvanic pulse plating, which was optimized to provide a conformal Sn coating and thus, to retain the initial np-Cu overall porous structure. Another optimization effort was made for ensuring a Sn atomic fraction that allows for the formation of Cu6Sn5 IMC. After the optimization process for determining the necessary plating conditions for reaching mostly Cu6Sn5 composition ratio, the material was subjected to sintering at temperatures in the range from 300ºC to 200oC, and at a pressure of 20 MPa. We found that the joints formed were heavily densified and consisted mainly of Cu3Sn IMC. The report presents the new approach as a facile and cost-effective method for synthesizing nanostructured Cu-Sn films as viable candidates for a new-generation of interconnect materials together with the demonstration of assembly processes that optimize robustness and reliability. The discussion also shows the proposed approach’s applicability by realization of low-temperature sintering of nanostructured CuSn films in pre-designed fine pitch assemblies. Figure 1: Schematic representation demonstrating key steps of the approach for synthesis of np-CuSn composites. Figure 1

Effects of Flux Activator Addition in Nanofiber/Solder Anisotropic Conductive Films (ACFs) on the Solder Wettability of Flex-on-Flex (FOF) Assembly

The advanced electronic packaging trends are changing to be more light weighted and miniaturized. Demands for flexible packaging are rapidly growing due to the rapid growth of wearable electronic industries, and advanced flexible interconnection methods are required. In order to satisfy these needs, fine pitch flex-on-flex (FOF) assembly has been introduced. FOF assembly can provide smaller package size, lower contact resistance, higher power handling capability, and flexibility. Anisotropic conductive films (ACFs) are interconnection materials, which have been widely used for the FOF assembly due to their simple and low-temperature processes. Previously, nanofiber ACFs were introduced by our research group, which showed remarkable capability of enhancing the conductive ball capture rate and preventing short circuit in the fine pitch assembly by suppressing the movement of conductive particles during the bonding process. Conventionally, an ultrasonic bonding method was used for a solder ACF bonding, because native solder oxide layer around solder balls can be physically broken by applying vertical ultrasonic vibrations, resulting in excellent solder metallurgical joints between electrodes. However, there are potential misalignment and damage issues generated by vertical ultrasonic vibrations. Therefore, the alternative bonding method is needed that can remove solder oxide layer to obtain excellent solder wetting without misalignment and damage issues by the ultrasonic bonding method. In this paper, thermocompression (TC) bonding and nanofiber/solder ACFs with addition of flux activators were used to chemically eliminate solder oxide. For the formation of stable intermetallic compounds, the contents of flux activators in nanofiber/solder ACFs were optimized. To investigate the flux effect during the TC bonding process, cross-sectional transmission electron microscopy was performed to analyze whether solder oxide layer is certainly removed by the flux. With the TC bonding and nanofiber/solder ACFs with addition of flux activators, stable solder wetting and excellent alignment were demonstrated for the fine pitch FOF assembly.

Far Back End of Line Aluminum Stress Reduction Methods for Two-Dimensional/2.5D Fine Pitch Assemblies

Fine pitch interconnects when used with two-dimensional (2D)/2.5D packaging technology offer enormous potential toward decreasing signal latency and by making it possible to package increased electrical functionality within a given area. However, fine pitch interconnects present their own set of challenges not seen in packages with coarse pitch interconnects. Increased level of stresses within the far back end of line (FBEOL) layers of the chip is the primary concern. Seven different types of 2D and 2.5D test vehicles with fine pitch and coarse pitch interconnects were built and tested for mechanical integrity by subjecting them to accelerated thermal cycling between −55 °C and 125 °C. Finite element based mechanical modeling was done to determine the stress level within the FBEOL layers of these test vehicles. For all the tested assemblies, experimental data and modeling results showed a strong correlation between reduced pitch and increased level of stresses and increased incidence of failures within the FBEOL region. These failures were observed exclusively at the passivation layer and aluminum pad interface. Experimental data in conjunction with mechanical modeling were used to determine a safe level of stress at the aluminum to passivation layer interface. Global and local design changes were explored to determine their effect on the stresses at this interface. Several guidelines have been provided to reduce these stresses for a 2D/2.5D package assembly with fine pitch interconnects. Finally, a reliable low stress configuration, which takes into account all the design changes, has been proposed, which is expected to be robust with very low risk of failure within the FBEOL region.

Moisture Effects on NCF Adhesion and Solder Joint Reliability of Chip-on-Board Assembly Using Cu Pillar/Sn–Ag Microbump

Electronic devices as well as electronic packaging technology have required higher speed, I/O capability, and density. To meet these requirements, flip-chip solder bumps interconnection combined with reflow assembly process has been a widely used. In spite of the many advantages of flip-chip solder bump joints, there is a limitation for less than 100 $\mu \text{m}$ fine pitch interconnection due to the solder bump bridging during the assembly process. Therefore, nonconductive films (NCFs) and Cu pillar/Sn–Ag microbump interconnection become a promising interconnection solution for fine pitch assembly. However, NCFs technology has some problems for flip-chip assembly. Epoxy-based NCF can easily absorb moisture, causing delamination reliability problem at moisture environment. In order to solve the interconnection, the NCF adhesion should be enhanced. Silane coupling agent (SCA) was added to NCFs to secure the microbump joint reliability for chip-on-board assembly by increasing the adhesion strength in the pressure cooker test. After the humidity test, the NCFs’ modulus and Tg were increased by adding SCA content. Moreover, the measured adhesion strength and energy showed similar results after the humidity test that higher SCA content showed high adhesion strength and energy than lower SCA content and unmodified NCF at the interface between NCF and solder resist of the printed circuit board substrate. The bump joint lifetime of 5wt% SCA NCF was longer than 1wt% SCA and unmodified NCF after the humidity test. In this paper, we report results of our investigations on effects of employing SCA in NCF composition for improved moisture resistance.

Effect of Nanofiber Orientation on Nanofiber Solder Anisotropic Conductive Films Joint Properties and Bending Reliability of Flex-on-Flex Assembly

Anisotropic conductive films (ACFs) have been widely used as an interconnection adhesive material due to its light weight and simple and low-temperature assembly processes. However, because of the higher demands for further miniaturization, short-circuit problem of ACFs interconnection has been a major issue, when it comes to very fine pitch assembly. Also, due to the fast development of wearable devices, demands for flexible packaging as well as flexible interconnection methods such as flex-on-flex (FOF) are growing more, where the bending characteristics are important. Nanofiber incorporated ACFs were previously introduced by our research group. The nanofiber incorporated ACFs showed excellent conductive particle movement suppression capability that not only prevents short circuit but also improves the conductive ball capture rate, which eventually improves the joint reliability of fine pitch FOF assembly. In order to maximize the conductive particle movement suppression capability of the nanofiber, nanofiber was oriented using a drum-type receiver. In addition, the bending reliability of FOF assembly using nanofiber/solder ACFs with different nanofiber orientations has been also investigated. As a result, parallel nanofiber/solder ACFs showed excellent joint properties as well as bending reliability due to the stable metallurgical solder joint formation and high conductive particle movement suppression capability, and this new type of ACF technology will provide a promising solution for future flexible electronic packaging.

TCB Process Options to Achieve the Lowest Cost

Thermocompression bonding enables the next generation fine pitch, 2.5D and 3D assembly technologies using Cu pillar interconnects, but to achieve widespread adoption the cost of TCB must become competitive with mass reflow processes. Stacked memory products drive the commercial volume today using TSV structures and TCB since it is the only technology able to achieve the desired stacked die construction and improved performance, but reducing the cost of assembly is still a key goal for those suppliers. In non-memory applications the choice of TCB can be driven by the bump pitch of the device or the requirement to control warpage of large die on laminate during assembly, but cost is still a key factor in the decision. The cost of a TCB process is largely driven by the UPH of the process where cost calculations are based on the cost per unit of material produced. As the UPH of a TCB process approaches 1400, the differential cost of the TCB process as compared to mass reflow becomes negligible. In the choice of a potential TCB process, special attention must be given to those processes that enable the highest UPH and the lowest cost. Processes used for TCB today can be grouped into two main categories; processes that use a pre-applied underfill and those that apply underfill after the bonding process. Underfills applied prior to bonding can be in the form of a non-conductive paste (TC-NCP) applied to a substrate or a non-conductive film applied to the wafer before dicing (TC-NCF). If underfill is applied after the bonding process, it is done as a Capillary Underfill (TC-CUF). In this case the die is underfilled in much the same way as in standard flip chip processes, but the process can be more challenging because of flux cleaning requirements and the narrower bondline of a typical TCB device. UPH is primarily driven by two factors; the range of temperature required by the bond head and the temperature ramp rate of the bond head. A process with less temperature range will have higher UPH and bond heads designed for the fastest cooling and heating rates will provide higher UPH processes. Two process options have been developed to minimize the temperature excursions required by the bond head and maximize the throughput. TC- NCF processes targeting stacked die and interposer products have been developed with throughputs approaching 2000 UPH. Substrate flux TC-CUF processes targeting assembly on laminate have been developed with throughputs that approach 2500 UPH. These two processes are expected to dominate TCB volume production moving forward as TCB enters mainstream production. This presentation will describe the methods used to achieve high throughput for both processes and the product application space appropriate for each one.

Characterization of nano-enhanced interconnect materials for fine pitch assembly

Purpose – Multiple fillers are adopted to study the filler influences on electrical and mechanical properties of the conductive adhesives. The performances of the developed nano-enhanced interconnect materials in printing process are also evaluated. The paper aims to discuss these issues. Design/methodology/approach – Micron-sized silver flakes are used as the basic fillers, and submicro- and nano-sized silver spheres and carbon nanotubes (CNTs) are adopted to obtain conductive adhesives with multiple fillers. Differential scanning calorimetry measurement is carried out to characterize the curing behavior of the samples with different fillers, four-probe method is used to obtain the bulk resistivity, shear test is conducted for adhesive strength, and environmental loading test is also involved. Furthermore, printing trials with different patterns have been carried out. Findings – The electrical resistivity of the adhesives with submicro-sized silver spheres does not monotonically change with the increasing sphere proportion, and there exists an optimized value for the ratio of silver flakes to spheres. Samples with relatively small amount of CNT additives show improved electrical properties, while their mechanical strengths tend to decrease. For the printing application, the adhesives with 18.3 volume% filler content behave much better than those with lower filler content of 6 percent. The presence of the nano-particles makes a slight improvement in the printing results. Research limitations/implications – More detailed printing performance and reliability test of the samples need to be carried out in the future. Originality/value – The conductive adhesives as interconnect materials exhibit some improved properties with optimized bimodal or trimodal fillers. The additive of the nano-fillers affects slightly on the printing quality of the bimodal conductive adhesives.

Advancing Electronic Packaging Using Microsolder Balls: Making 25-nm Pitch Interconnection Possible

Electronic packaging technology has advanced in the direction of integrating diverse components into one package to satisfy market demands for multifunctionality as well as portability. For this reason, various packaging structures have been introduced, such as multichip modules, package on package, package in package, and eventually three-dimensional (3-D)-chip stacks. All of these approaches require increased input/output (I/O) counts, resulting in fine-pitch assembly. Therefore, the most critical issue in current electronic packaging is how to assemble fine-pitch components while avoiding an electrical short circuit in the x-y direction. Much research has been done on fine-pitch interconnecting technology using microsolder balls smaller than 200 nm, but the problems of solder-ball handling and low yield remain. In addition, there have been few reports so far about the fine-pitch interconnection below 25-nm pitch using microsolder balls. Three-dimensional-chip stacks require an additional microsolder and copper hybrid bumping and patterning processes on through silicon via (TSV), which increases the processing cost.

Advanced Microelectronics Packaging Solutions for Miniaturized Medical Devices

The wide range of applications for medical electronics drives unique requirements that can differ significantly from commercial & military electronics. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present report, key enablers for achieving reduction in size, weight, and power (SWaP) in electronic packaging for a variety of medical applications are discussed. Advanced microelectronics packaging solutions with embedded passives are enabling SWaP reductions. Implementation of these solutions has realized up to 27X reduction in physical size for existing PWB assemblies, with significant reductions in weight. Shorter interconnects can also reduce or eliminate the need for termination resistors for some net topologies. Successful miniaturized products integrate the following design techniques and technologies: component footprint reduction, thin high density interconnects substrate technologies, I/O miniaturization and IC assembly capabilities. This paper presents fabrication and electrical characterization of embedded actives and passives on organic multilayered substrates. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on embedded chips, resistors, and capacitors. Embedded passive technology further enhances miniaturization by enabling components to be moved from the surface of the substrate to its internal layers. The use of thin film resistor material allows creating individual miniaturized buried resistors. These resistors provide additional length and width reduction with negligible increases to the overall substrate and module (SiP) height. Resistor values can vary from 5 ohm to 50 Kohm with tolerances from 5 to 20% and areas as small as 0.2 mm2. The embedded resistors can be laser trimmed to a tolerance of <5% for applications that require tighter tolerance. The electrical properties of embedded capacitors fabricated from polymer-ceramic nanocomposites showed a stable capacitance and low loss over a wide frequency and temperature range. A few test vehicles were assembled to do system level analysis. Manufacturing methods and materials for producing advanced organic substrates and flex along with ultra fine pitch assemblies are discussed. A case study detailing the fabrication of a flexible substrate for use in an intravascular ultrasound (IVUS) catheter demonstrates how the challenges of miniaturization are met. These challenges include use of ultra-thin polymer films, extreme fine-feature circuitization, and assembly processes to accommodate die having reduced die pad pitch. In addition, new technologies for embedding a variety of active chips are being developed. A variety of active chips, including a chip having dimensions of one millimeter square, have been embedded and electrically connected to develop high performance packages.

Miniaturization of Electronic Substrates for Medical Device Applications

The medical industry is clearly and urgently in need of development of advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility for handheld, portable, in vivo, and implantable devices. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present report, key enablers for achieving reduction in size, weight, and power (SWaP) in electronic packaging for a variety of medical applications are discussed. These enablers include materials selection, embedded passives and active devices, System-in-Package (SiP) designs, and flex circuits. Manufacturing methods and materials for producing advanced organic substrates and flex along with ultra fine pitch assemblies are discussed. A case study detailing the fabrication of a flexible substrate for use in an intravascular ultrasound (IVUS) catheter demonstrates how the challenges of miniaturization are met. These challenges include use of ultra-thin polymer films, extreme fine-feature circuitization, and assembly processes to accommodate die having reduced die pad pitch.

Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking

Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages

Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance. Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.

Fundamental Limits of Organic Packages and Boards and the Need for Novel Ceramic Boards for Next Generation Electronic Packaging

The system-on-a-package (SOP) paradigm proposes a package level integration of digital, RF/analog and opto-electronic functions to address future convergent microsystems. Two major components of SOP fabrication are sequential build-up of multiple layers (4–8) of conducting copper patterns with interlayer dielectrics on a board and multiple ICs flip-chip bonded on the top layer. A wide range of passives, wave-guides and other RF and opto-electronic components buried within the dielectric layers provide the multiple functions on a single microminiaturized platform. The routing of future nanoscale ICs with 10,000+ I/Os require multiple build-up layers of ultra fine board feature sizes of 10 μm lines/space widths and 40 μm pad diameters. Current FR4 boards cannot achieve this build-up technology because of dimensional instability during processing. These boards also undergo high warpage during the sequential build-up process which limits the fine-line lithography and also causes misalignment between the vias and their corresponding landing pads. In addition, the CTE mismatch between the silicon die and the board leads to IC-package interconnect reliability concerns, particularly in future fine-pitch assemblies where underfilling becomes complicated and expensive. This work reports experimental and analytical work comparing the performance of organic and novel ceramic boards for SOP requirements. The property requirements as deduced from these results indicate that a high stiffness and tailorable CTE from 2–4 ppm/∘C is required to enable SOP microminiaturized board fabrication and assembly without underfill. A novel ceramic board technology is proposed to address these requirements.

Immersion tin as a high performance solderable finish for fine pitch PWBs

A new high performance immersion tin incorporating a co‐deposited organic provides a highly solderable PWB surface finish. The process is described and includes solderability data after accelerated aging and extended processing. Studies of SIR, metallic dendritic growth and ionic contamination are included. A final section shows the benefits for fine pitch assembly, including the yield improvements seen at reflow, ICT and final inspection. The reliability questions are answered and conclude that the flat solderable tin process provides a cost‐effective and yield‐enhancing planar alternative to Nickel‐Gold, HASL and OSPs.

Improvements to X-ray laminography for automated inspection of solder joints

With the increased usage of fine-pitch assemblies and ball grid array (BGA) packages, there is a dramatic increase in demand for automated defect detection techniques such as X-ray laminography. However, the limitations of this imaging medium are not well understood by the industry. This article addresses the need for improving the imaging resolution of X-ray laminography, particularly for accurate three-dimensional (3-D) measurement of solder joint structures. The authors have developed a new method for reconstruction of the laminographs which improves the signal-to-noise ratio (SNR) of the laminographs significantly and enables better 3-D visualization of solder shape. Application of automated solder joint defect classification using neural networks has also been studied. Components with BGA, gull-wing and J-lead joints were imaged and several neural network methods were used to identify different classes of defects particularly significant to each type of joint. A novel probabilistic neural network approach for two-dimensional (2-D) image classification has been developed which performs as well as or better than a conventional backpropagation network.

Non‐precious Metal Finishes for Fine Pitch Assembly

The industry trend towards higher density interconnect on PWBs has caused board fabricators to explore alternatives to the traditional hot air solder levelling (HASL) technology. Problems with pad planarity in the assembly of fine pitch devices with high I/O counts are well documented. Organic finishes based on substituted imidazoles address some of the assembly requirements, as do precious metal finishes such as gold and palladium. However, both types of solderable finish have limitations or undesirable characteristics. This paper discusses and compares other non‐precious metal systems as alternative solderable finishes. Immersion plating processes based upon bismuth and silver have been developed, and the data presented demonstrate that the solderability of these systems is superior to that of organic and palladium finishes. Test results on hole‐fill, solder‐spread and meniscograph (wetting balance) are extensively discussed in this study. Potential concerns over joint reliability and diffusion are addressed. The chemistry of these non‐precious metal systems also affords benefits to the PWB fabricator. These include increased yields, reduced costs and the elimination of soldermask compatibility issues. Considering possible future industry trends, a significant advantage of these materials is their full compatibility with lead‐free solders. Data on compatibility with solder replacements and wire‐bonding technology are also presented.

Wire bond loop profile development for fine pitch-long wire assembly

Die size reductions can be achieved through optical shrinks, compaction of existing layouts, or redesigns to finer fab geometries. For some die the limiting factors for die size reduction are bond pitch and bond size. In these pad limited designs, the circuitry is concentrated in the center of the die. Precious empty space exists between the bond pads in the periphery of the die and the circuitry in the die core. The only hope for die size reductions in these designs lies in advances in assembly technology that allow for reductions in bond pitches and bond size. Fine pitch assembly poses a number of challenges for conventional wire bond technology. Reducing bond pitch increases the probability of ball shorting, bond wire shorting, and bond wire damage. On the other hand, decreasing the die size by reducing the bond pitch results in longer wire lengths thus limiting some assembly options such as moving to smaller diameter bonding wires. Wire loop profile becomes a critical factor for control in fine pitch assembly. In this paper a statistical design of experiment is used in developing a wire bond loop profile control. The effect of major bonding parameters, such as kink-height, reverse loop, loop factor, wire tension, and their impact on loop profile are analyzed. The results obtained define the bond parameter requirements that must be met in order to control the wire loop profile to optimize fine pitch wire bond assembly yields. >