Fine-grained Power Management Research Articles

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Conventional power delivery networks (PDNs) and power management techniques using off-chip power converters with bulky passive components cannot meet the ever-evolving power delivery requirements of high-performance modern system-on-chips (SoCs). In SoCs, heterogeneous components, including multi-core processors and mixed-signals peripheral circuits, require state-of-the-art PDNs to provide high-quality power-on-demand with minimum latency, simultaneously achieving the small-factor, high conversion efficiency, and minimum current consumption. To satisfy these power delivery requirements, various PDNs have been developed over the past decades, such as the conventional architectures using off-chip power converters, architectures using in-package power converters and fully-integrated power converters, and heterogeneous architectures (off-chip power converters and on-chip regulators). This paper reviews these architectural advancements of the PDNs and their advantages and limitations, which leads us to discuss a heterogeneous PDN structure consisting of a highly efficient off-chip switching-mode power converter and multiple highly precise small linear regulators integrated on chip at point-of-load locations. The heterogeneous PDN has been proved one of the most suitable architectures to achieve high-quality fine-grained on-chip power delivery and management in SoCs. This paper also discusses unified voltage and frequency regulators (UVFRs), which support dynamic-variation-aware dynamic voltage and frequency scaling (DVFS) for fine-grained power management in multi-core processors. Based on the UVFR, we propose a modified heterogeneous PDN using frequency-referenced digital low-dropout regulators (FR-DLDOs) for more efficient DVFS, eliminating the need for band-gap circuits to provide reference voltages. As an exemplary implementation of FR-DLDO for this PDN, we present an FR-DLDO with a transient-boost control, which accelerates the transient response. The transient-boost control is activated dynamically only when an abrupt change happens out of the steady state. The implemented FR-DLDO fabricated in a 40-nm CMOS process outperforms other FR-DLDOs in the figure-of-merit and peak power efficiency while driving 40 mA of load current.

A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI

This work demonstrates a dual-core RISC-V system-on-chip (SoC) with integrated fine-grain power management. The 28-nm fully depleted silicon-on-insulator (FD-SOI) SoC integrates switched-capacitor voltage converters and 4-Gb/s off-chip serial links. The SoC runs applications with operating system support on dual RISC-V Rocket cores with vector accelerators. Runtime monitoring of microarchitectural counters allows prediction of future compute intensity, enabling the voltage state of the managed core to be adjusted quickly to optimize energy efficiency without sacrificing overall performance.

Architectural Advancement of Digital Low-Dropout Regulators

Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient fine-grained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, event-driven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).

A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors

Fully integrated voltage regulators (FIVRs) offer many advantages, such as fine-grained power management, fast transient response, and reduced form factor. This article addresses light-load efficiency in FIVRs with nH-scale air-core inductors. The challenges of implementing efficient discontinuous conduction mode (DCM) operation at high switching frequencies are discussed, which include zero current detection, inductor ac-loss effects, and power delivery network (PDN) resonances. A prototype in 14-nm CMOS is presented, which shows the DCM operation at up to 70 MHz with a peak efficiency of 88% for 1.6–1.2-V conversion.

Switched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital Load Circuits

Switched-mode-control (SMC) is a control methodology that allows instantaneous switching between controllers to extend the dynamic range of feedback circuits. A hybrid low dropout voltage regulator utilizing SMC is designed in 130 nm CMOS for fine-grain power management, fast droop recovery, and accurate voltage regulation of digital load circuits. The design provides an optimal tradeoff between performance and accuracy by switching between a digital and an analog control loop. Measurements from the test-chip show near-threshold-voltage operation, peak transient response of 0.71 ns/mA, and a peak current efficiency of 98.64%.

Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators

Low-dropout (LDO) regulators are becoming a part of modern processor architectures for fine-grain power management and higher energy efficiency. This paper shows that these integrated LDOs can also be leveraged to enhance side-channel analysis resistance of encryption engines to power side-channel analysis (PSCA) attacks. The current transformation induced by integrated LDOs coupled with limited bandwidth of the feedback loop help suppress the side-channel leakage. The impact of both analog LDO (ALDO) and all-digital LDO (ADLDO) on the load currents is studied with correlation analysis between the load and the LDO input current. The effectiveness of integrated LDOs as countermeasure to PSCA is further explored with Correlation Power Analysis (CPA) and Test Vector Leakage Assessment (TVLA) performed on both simulated as well as measured load currents for a 128-bit Advanced Encryption Standard (AES) implemented in GF-130-nm process technology. We show that integrated LDOs can enhance PSCA resistance; however, the trade-off between integrated LDO performance and side-channel security is essential. We design integrated LDOs optimized for low-power/compact encryption engines and show that LDO-based protection can increase power attack resistance by >800× with minimal power, area, and performance overheads.

Traleika Glacier: A hardware-software co-designed approach to exascale computing

The Traleika Glacier architecture, targeted at exascale hardware, is proposed.A task-based runtime system, the Open Community Runtime is presented.The experience of co-designing hardware and software for exascale is described. The move from current petascale machines to future exascale machines will need both hardware improvements and software changes. Hardware will need to evolve to focus primarily on features that lower energy consumption: near-threshold voltage operation, fine-grained power and clock management and heterogeneity. Software will also need to evolve and be able to express more parallelism, become more dynamic and adaptable in order to be able to operate on a much more variable hardware.In this paper, we present Traleika Glacier, an effort that seeks to evaluate radical design changes to meet the constraints, both in terms of power and cost, of exascale computing. The salient features of the hardware design presented in the work include a) a use of heterogeneous cores, b) a redesign of the memory system that centers around hierarchical scratchpads and a global address space, c) the hardware acceleration of certain memory and network operations through specialized engines and, d) very fine-grained control and monitoring capabilities. On the software side, we describe a task-based runtime system, the Open Community Runtime (OCR) which aims to express a wide range of higher-level programming models with a very limited set of core concepts: event-driven tasks for computation, events for synchronization and relocatable data-blocks for data management.

Electrochemical Innovation in Electronics: Is Success Sustainable?

Electrochemistry and electrochemical engineering have evolved into important disciplines enabling unprecedented progress in electronics. Because of the complexity of electronic devices the path to innovation requires a thorough understanding of materials and device characteristics, integration of materials and processes and process scale up, and control based on sound electrochemical engineering practices. Four case studies will be examined and common elements in product innovation, themes for success and shortcomings will be indentified. Because of globalization and new economic drivers of growth in developed economies, future success stories have to bring in differentiating solutions to the market place. The electrochemical fabrication of flip-chip solder technology is an extremely selective and efficient process which is extendible to larger wafer sizes, to finer dimensions and to higher C4 density. Modeling, experimental matrices, process control and equipment were developed to enable great manufacturability and scalability of the flip-chip process.1 CIGS solar cells are one the most promising of the thin film solar cell technologies. For the electrodeposition of CIGS different processing approaches have been tried such as electrodeposition of Cu/In/Ga/Se thin films or alloy deposition of CuInGaSe2. 2 Key challenges are the deposition of uniform nm scale thin films on meter large resistive substrates, controlling nucleation and growth and tailoring the microstructure of the thin film in order to control the composition and microstructure of the final chalcopyrite layer.3,4 Electrodeposition of a Cu–In–Ga mixed oxide/hydroxide layer from an aqueous solution has been demonstrated.5 Monolithically integrated power converters are enabling technologies for the fine-grain power management of future microprocessors. A high magnetic inductor Q is required for the buck converter to achieve >90% power efficiency.6 A high Q magnetic inductor poses challenging requirements for the magnetic materials: low coercivity, high permeability, high resistivity in order to minimize eddy current losses and a small damping coefficient in order to have reduce magnetic losses at high frequency.7 We developed selection criterial for the materials based on permeability measurements and the estimation of the magnetic loss tangent. It has been a long journey of materials selection.8 Wearables will be transformed into Thinkables offering cognitive real-time analytics of biological data at the point of sensing. Real-time analytics will require continuous streaming of large data sets. Neuromorphic platforms will play a key role in connecting on-body sensors directly with deep-learning technology creating a closed-loop interface back to the wearer. IBM’s recently introduced neuromorphic TrueNorth chip constitutes the means to transform a Wearable into a Thinkable. By linking TrueNorth technology to advances in electrochemical bio-sensing and deep-learning, we aim to create a first generation of Thinkables in the field of applied neuroscience.9, 10 A big future need is real-time handling of large data sets. Acknowledgement The author gratefully acknowledges Luby T. Romankiw, who introduced electrochemical technology at IBM; M. Datta who had a key role in the R&D of the electrochemically fabricated C4s; D. Lincot, P.-P. Grand for introducing the key challenges in solar cells and collaborating; N. Wang, E. O’Sullivan, B. Doris for collaboration on the magnetic inductor; S. Harrer and the IBM Australia team for discussions and collaboration on bioelectronics, biosensors and cognitive computing. REFERENCES M. Datta, R. V. Shenoy, C. Jahnes, P. C. Andricacos, J. Horkans, J. O. Dukovic, L. T. Romankiw, J. Roeder, H. Deligianni, H. Nye, B. Agarwala, H. M. Tong, P. Totta, J. Electrochem. Soc., 142(11), J. Electrochem. Soc., 142(11), 3778- 3785 (1995).H. Deligianni, S. Ahmed, L.T. Romankiw, Interface, 20, 47 (2011)Q. Huang, et al., JECS, 158(2), D57-D61 (2011).S. Ahmed, et al., JECS, 159(2), D129-D134 (2012).A. Duchatelet, T. Sidali, N. Loones, G. Savidand, E. Chassaing, D. Lincot, S olar Energy Materials & Solar Cells , 119 , 241–245, (2013). N. Wang, D. Goren, E. O’Sullivan, X. Zhang, W. J. Gallagher, P. Herget, et al., IEDM, pp. 307-310, 2014. H. Deligianni, N. Wang, O. Jinka, J. Yoon, E. J. O'Sullivan, L. Romankiw, W. J. Gallagher, No. 905, 228th ECS Meeting in Phoenix, AZ, October 13, 2015. E. O’Sullivan, N. Wang, H. Deligianni, B. Doris, A. Bahgat Shehata, B. C. Webb, L T. Romankiw, W. J. Gallagher, 230th ECS Meeting in Honolulu, HI, October 7-11, 2016. S. Harrer, I. Kiral-Kornek, R. Kerr, B. Mashford, J. Tang, A. Jimeno Yepes, H. Deligianni., “From Wearables to Thinkables-Deep Learning, Nano-biosensors and the Next Generation of Mobile Devices,” White Paper, ICONN 2016, Canberra, AU.10. E. Nurse, B. Mashford, A. Jimeno Yepes, I. Kiral-Kornek, J. Tang, P. Karoly, L. Deligianni, S. Harrer, D. Freestone, “Decoding EEG and LFP signals using deep learning: heading TrueNorth,” accepted ACM Computing Frontiers, 2016.

Energy-Efficient Power Delivery System Paradigms for Many-Core Processors

The design of power delivery system plays a crucial role in guaranteeing the proper functionality of many-core processor systems. The power loss suffered on power delivery has become a salient part of total power consumption, and the energy efficiency of a highly dynamic system has been significantly challenged. Being able to achieve a fast response time and multiple voltage domain control, on-chip voltage regulators (VRs) have become popular choices to enable fine-grain power management, which also enlarge the design space of power delivery systems. This paper analytically studies different power delivery system paradigms and power management schemes in terms of energy efficiency, area overhead, and power pin occupation. The analysis shows that compared to the conventional paradigm with off-chip VRs, hybrid paradigms with both on-chip and off-chip VRs are able to maintain high efficiency in a larger range of workloads, though they suffer from low efficiency at light workload. Employed with the quantized power management scheme, the hybrid paradigm can improve the system energy efficiency at light workload by a maximum of 136% compared to the traditional load balanced scheme. Besides this, the in-package (iP) hybrid paradigm further shows its advantage in reducing the physical overheads. The results reveal that at 120 W workload, it occupies only a 10.94% total footprint area or 39.07% power pins of that of the off-chip paradigm. We conclude that the iP hybrid paradigm achieves the best tradeoffs between efficiency, physical overhead, and realization of fine-grain power management.

Design and implementation of low power Android mobile sink based on load prediction

To reduce the power consumption of mobile sink node, a new state PER_NOTIFICATION is added to the standard Android system. Therefore, USB devices can be added to or removed from the system by the sys file interface according to users' specific demand, realising a more fine-grained power management. In addition, an improved CPU load prediction algorithm SAWDLP is proposed to replace the default one in on-demand governor. With SAWDLP, a more accurate CPU load prediction can be done and then a more appropriate frequency can be chosen to reduce the CPU power consumption. Experimental results show that the PER_NOTIFICATION works well in managing the USB devices. The SAWDLP algorithm gets 85.20% higher accuracy in CPU load prediction and 0.40% lower power consumption in comparison to the PAST algorithm, accomplishing the goal of low power design and run time extension.

Advanced features in IBM POWER8 systems

The IBM POWER8™ processor includes many innovative features that enable efficient and flexible computing, along with enhancements in virtualization, security, and serviceability. These features benefit application performance, and big data and analytics computing, as well as the cloud environment. Notable features include the capabilities to dynamically and efficiently change the number of threads active on a processor, enhancing application performance via integer vector operations, encryption accelerations, and reference history arrays. Also notable is improved virtual machine density (supporting multiple simultaneous partitions per core and providing fine-grain power management), allowing continuous monitoring of system performance as well as significantly enhanced system RAS (reliability, availability, and serviceability) and security. Each of these features is technologically complex and advanced. This paper provides an in-depth description of some of these features and their exploitation through systems software and middleware. These features will continue to bring value to the system-of-record workloads in the enterprise. They also make POWER8 systems well-suited for serving the needs of newer workloads such as big data and analytics, while efficiently supporting deployment in cloud environments.

A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits

The need for fine-grained power management in digital ICs has led to the design and implementation of compact, scalable low-drop out regulators (LDOs) embedded deep within logic blocks. While analog LDOs have traditionally been used in digital ICs, the need for digitally implementable LDOs embedded in digital functional units for ultrafine grained power management is paramount. This paper presents a fully-digital, phase locked LDO implemented in 32 nm CMOS. The control model of the proposed design has been provided and limits of stability have been shown. Measurement results with a resistive load as well as a digital load exhibit peak current efficiency of 98%.

An Integrated Approach for Fine-Grained Power and Peak Temperature Management During High-Level Synthesis

Power and temperature has become the major design challenges in the development of today's complex low power digital integrated circuits due to the adverse effect of these parameters on performance, reliability, cooling and packing costs, as well as increase in leakage power as we gradually move towards deep submicron technology. The increasing adoption of fine-grained power management strategies in design synthesis flow has motivated us to build power and temperature conscious designs using such design architectures at the behavioral level. The stringent power budget of fine grained power managed digital integrated circuits have driven chip designers to optimize power at the cost of area and delay. We study the design space defined due to this trade-off and present a branch-and-bound (B/B) algorithm to explore this state space and report the pareto-optimal front with respect to area and power. We also explore the scope of parallelism within the branch-and bound (B/B) algorithm for control and data-flow intensive circuits in order to address the scalability issue. In this paper, we propose power and temperature aware multi-objective scheduling and binding algorithms during behavioral synthesis stage using fine-grained dynamic voltage scaling enabled functional units to alleviate the problem of localized heating, which often leads to hotspot zones in chips.

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

This paper presents an all-digital phase-locked loop (ADPLL) clock generator for globally asynchronous locally synchronous (GALS) multiprocessor systems-on-chip (MPSoCs). With its low power consumption of 2.7 mW and ultra small chip area of 0.0078 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> it can be instantiated per core for fine-grained power management like DVFS. It is based on an ADPLL providing a multiphase clock signal from which core frequencies from 83 to 666 MHz with 50% duty cycle are generated by phase rotation and frequency division. The clock meets the specification for DDR2/DDR3 memory interfaces. Additionally, it provides a dedicated high-speed clock up to 4 GHz for serial network-on-chip data links. Core frequencies can be changed arbitrarily within one clock cycle for fast dynamic frequency scaling applications. The performance including statistical analysis of mismatch has been verified by a prototype in 65-nm CMOS technology.

Virtual machine power measuring technique with bounded error in cloud environments

In virtualized datacenters, accurately measuring the power consumption of virtual machines (VMs) is the prerequisite to achieve the goal of fine-grained power management. However, existing VM power models can only provide power measurements with empirical accuracy and unbounded error. In this paper, we firstly formulize the co-relation between utilization and accuracy of power model, and compare two classes of VM power models; then we propose a novel VM power model which is based on a conception named relative performance monitoring counter (PMC); finally, based on the relative PMC power model, we propose a novel VM scheduling algorithm which uses the information of relative PMC to compensate the recursive power consumption. Theoretical analysis indicates that the proposed algorithm can provide bounded error when measuring per-VM power consumption. Extensive experiments are conducted by using various benchmarks on different platforms, and the results show that the error of per-VM power measurement can be significantly reduced. In addition, the proposed algorithm is effective to improve the power efficiency of a server when its virtualization ratio is high.

Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems

Electronic systems on a chip increasingly suffer from component variation, voltage noise, thermal hotspots, and other subtle physical phenomena. Systems with reconfigurability have unique opportunities for adapting to such effects. Required, however, are low-cost, fine-grained methods for sensing physical parameters. This article presents powerful, novel approaches to online sensing, including methods for designing compact reconfigurable sensors, low-cost threshold detection, and several enhanced measurement procedures. Together, the approaches help enable systems to autonomously uncover a wealth of physical information. A highly efficient counter and improved ring oscillator are introduced, enabling an entire sensor node in just 8 Virtex-5 LUTs. We describe how variations can be measured in delay, temperature, switching-induced IR drop, and leakage-induced IR drop. We demonstrate the proposed approach with an experimental system based on a Virtex-5, instrumented with over 100 sensors at an overhead of only 1.3%. Results from thermally controlled experiments provide some surprising insights and illustrate the utility of the approach. Online sensing can help open the door to physically adaptive computing, including fine-grained power, reliability, and health management schemes for systems on a chip.

Fine-grained power management using process-level profiling

Low-power hardware design itself is not enough to solve the power problem of computer systems. Operating system level power saving strategies have been proved as effective complement to hardware methods. However, most of these strategies work on system level, and some of them may severely influence performance. In order to balance between performance and energy consumption, fine-grained methods, such as process-level power management, were proposed. These methods usually require realtime power information to make critical power-saving decisions, but most power profiling tools only supply component level power information. In this paper, we first propose a process-level power profiling tool called pTopW, which runs on Windows platform. pTopW supplies a group of APIs for power-aware system modules to acquire realtime power profiles and make power-aware decisions based on these information. In addition, we introduce a power-aware system module called EnergyGuard, which can eliminate energy wasted by abnormal-behavior applications. Through experiments, we found that the energy model we proposed have very good responsiveness. In addition, EnergyGuard is helpful to distinguish applications’ abnormal power behaviors.

A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS

On-chip DC-DC converters have the potential to offer fine-grain power management in modern chip-multiprocessors. This paper presents a fully integrated 3-level DC-DC converter, a hybrid of buck and switched-capacitor converters, implemented in 130 nm CMOS technology. The 3-level converter enables smaller inductors (1 nH) than a buck, while generating a wide range of output voltages compared to a 1/2 mode switched-capacitor converter. The test-chip prototype delivers up to 0.85 A load current while generating output voltages from 0.4 to 1.4 V from a 2.4 V input supply. It achieves 77% peak efficiency at power density of 0.1 W/mm2 and 63% efficiency at maximum power density of 0.3 W/mm2. The converter scales output voltage from 0.4 V to 1.4 V (or vice-versa) within 20 ns at a constant 450 mA load current. A shunt regulator reduces peak-to-peak voltage noise from 0.27 V to 0.19 V under pseudo-randomly fluctuating load currents. Using simulations across a wide range of design parameters, the paper compares conversion efficiencies of the 3-level, buck and switched-capacitor converters.

Integrated CPU and l2 cache voltage scaling using machine learning

Embedded systems serve an emerging and diverse set of applications. As a result, more computational and storage capabilities are added to accommodate ever more demanding applications. Unfortunately, adding more resources typically comes on the expense of higher energy costs. New chip design with Multiple Clock Domains (MCD) opens the opportunity for fine-grain power management within theprocessor chip. When used with dynamic voltage scaling (DVS), we can control the voltage and power of each domain independently. A significant power and energy improvement has been shown when using MCD design in comparison to managing a single voltage domain for the whole chip, as in traditional chips with global DVS. In this paper, we propose PACSL a Power-Aware Compiler-based approach using Supervised Learning. PACSL automatically derives an integrated CPU-core and on-chip L2 cache DVS policy tailored to a specific system and workload. Our approach uses supervised machine learning to discover a policy, which relies on monitoring a few performance counters. We present our approach detailing the role of a compiler in constructing a custom power management policy. We also discuss some implementation issues associated with our technique. We show that PACSL improves on traditional power management techniques that are used in general MCD chips. Our technique saves 22% on average (up to 46%) in energy-delay product over a DVS technique that applies independent DVS decisions in each domain. Compared to no-power management, our technique improves energy-delay product by 26% on average (up to 64%).