Abstract
Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient fine-grained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, event-driven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).
Highlights
Low-Dropout (LDO) Regulators have been extensively used to achieve fine-grained power delivery and power management in system-on-chip (SoC) platforms having multiple voltage domains and various load circuits [1]–[5]. Their power delivery networks commonly have hierarchical structures as shown in Fig. 1, where power-efficient switchingmode (DC-DC) regulators serve as pre-regulator and multiple LDOs integrated at point-of-load locations serve as postregulators to provide dynamic scaling of voltages and currents to various load circuits [6], [7]
Digital Low-dropout (DLDO) are typically inferior in steady-state voltage ripples (VRIPP) and power-supply rejection (PSR)
As CMOS processes are downscaled to deep submicron, analog LDOs suffer severely from low supply voltages, which are often at near-threshold voltage (NTV) levels
Summary
Low-Dropout (LDO) Regulators have been extensively used to achieve fine-grained power delivery and power management in system-on-chip (SoC) platforms having multiple voltage domains and various load circuits [1]–[5]. As CMOS technologies and their supply voltage levels (VDD) are downscaled, the performance of analog LDOs has degraded severely due to their insufficient gain of error-amplifiers under low-voltage levels To address this major challenge, digital designs of LDOs have been investigated extensively because digital LDOs (DLDOs) typically can achieve better performances under low voltage conditions like near-threshold voltage (NTV) levels. DLDOs are typically inferior in steady-state voltage ripples (VRIPP) and power-supply rejection (PSR). To address these challenges, various DLDO architectures and techniques have been proposed to date. Many of the fully integrated analog LDOs can offer fast loadtransient response, high PSR, large bandwidth [13]–[15] with low IQ [16], [17] and/or small-sized integrated output capacitor (COUT ) [18]–[20]
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