FIFO Architecture Research Articles

Area Efficient Reconfigurable Buffer for NoC Router

In the current research, FPGA-based architecture of the Noc device reconfigurable router is suggested. Proposed router specification entry is done with the Verilog Hardware Description Language. The latest research has a five-channel router and a crossbar switch (east, west, north, south and local). Each channel has buffers and multiplexers. FIFO buffer stores data, and multiplexer monitors the input and output of data. The channel contains FIFO architecture and multiplexers. The crossbar switch is then planned and five other channels. Reducing the number of LUTs in the proposed work decreased the router area. A report is given for the number of LUTs used in a router. Results obtained indicate the area efficiency of the proposed router over existing method.

Host managed contention avoidance storage solutions for Big Data

The performance gap between compute and storage is fairly considerable. This results in a mismatch between the application needs from storage and what storage can deliver. The full potential of storage devices cannot be harnessed till all layers of I/O hierarchy function efficiently. Despite advanced optimizations applied across various layers along the odyssey of data access, the I/O stack still remains volatile. The problems associated due to the inefficiencies in data management get amplified in Big Data shared resource environments. The Linux OS (host) block layer is the most critical part of the I/O hierarchy, as it orchestrates the I/O requests from different applications to the underlying storage. Unfortunately, despite it’s significance, the block layer, essentially the block I/O scheduler, hasn’t evolved to meet the needs of Big Data. We have designed and developed two contention avoidance storage solutions, collectively known as “BID: Bulk I/O Dispatch” in the Linux block layer specifically to suit multi-tenant, multi-tasking shared Big Data environments. Hard disk drives (HDDs) form the backbone of data center storage. The data access time in HDDs is majorly governed by disk arm movements, which usually occurs when data is not accessed sequentially. Big Data applications exhibit evident sequentiality but due to the contentions amongst other I/O submitting applications, the I/O accesses get multiplexed which leads to higher disk arm movements. BID schemes aim to exploit the inherent I/O sequentiality of Big Data applications to improve the overall I/O completion time by reducing the avoidable disk arm movements. In the first part, we propose a dynamically adaptable block I/O scheduling scheme BID-HDD for disk based storage. BID-HDD tries to recreate the sequentiality in I/O access in order to provide performance isolation to each I/O submitting process. Through trace driven simulation based experiments with cloud emulating MapReduce benchmarks, we show the effectiveness of BID-HDD which results in 28–52% lesser time for all I/O requests than the best performing Linux disk schedulers. In the second part, we propose a hybrid scheme BID-Hybrid to exploit SCM’s (SSDs) superior random performance to further avoid contentions at disk based storage. BID-Hybrid is able to efficiently offload non-bulky interruptions from HDD request queue to SSD queue using BID-HDD for disk request processing and multi-q FIFO architecture for SSD. This results in performance gain of 6–23% for MapReduce workloads when compared to BID-HDD and 33–54% over best performing Linux scheduling scheme. BID schemes as a whole is aimed to avoid contentions for disk based storage I/Os following system constraints without compromising SLAs.

English

The FIFO buffer used in high speed data links plays an important role in data transfer and depending upon the application the size of FIFO is variable in nature which known as buffer adoption. There are different buffer adoption schemes for FIFO buffer, some of which are based on goodput, throughput, speed, network natures etc. This paper presents the study of those current various FIFO buffer adoption schemes which employs in current best effort data networks. Also the some proposed works are hereby studied and the conclusion have made by this study. This study work have done in three phase. Firstly the different types of FIFO architecture have studied and present the basic architecture of it. Second the problem identification has been done by literature review of different network architecture proposed. Finally the few best FIFO buffer adoption techniques are studied followed by literature review as extension of it. The RADA scheme is concluded the best buffer adoption scheme among all the papers studied during study.

An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS

This paper presents an energy-efficient feature extraction accelerator design aimed at visual navigation. The hardware-oriented algorithmic modifications such as a circular-shaped sampling region and unified description are proposed to minimize area and energy consumption while maintaining feature extraction quality. A matched-throughput accelerator employs fully-unrolled filters and single-stream descriptor enabled by algorithm-architecture co-optimization, which requires lower clock frequency for the given throughput requirement and reduces hardware cost of description processing elements. Due to the large number of FIFO blocks, a robust low-power FIFO architecture for the ultra-low voltage (ULV) regime is also proposed. This approach leverages shift-latch delay elements and balanced-leakage readout technique to achieve 62% energy savings and 37% delay reduction. We apply these techniques to a feature extraction accelerator that can process 30 fps VGA video in real time and is fabricated in 28 nm LP CMOS technology. The design consumes 2.7 mW with a clock frequency of 27 MHz at Vdd = 470 mV, providing 3.5× better energy efficiency than previous state-of-the-art while extracting features from entire image.

Efficient Multicast Support in High-Speed Packet Switches

The tremendous growth of the Internet coupled with newly emerging applications has created a vital need for multicast traffic support by backbone routers and ATM switches. Considerable research work has been done on Input Queued (IQ) switches to handle multicast traffic flows. Unfortunately, all previously proposed solutions were of no practical value because they either lack performance or were simply too complex to implement. Internally Buffered Crossbar (IBC) switches, where a limited small amount of memory is added in each crosspoint of the crossbar fabric, on the other hand, have been considered as a robust alternative to buffer-less crossbar switches to improve the switching performance. However, very little has been done on multicasting in IBC switches. In this paper, we fill this gap and study the multicasting problem in IBC switches. In particular, we propose a novel IBC based multicast architecture along with a simple scheduling scheme named Multicast cross-point Round Robin (MXRR). Our scheme was shown to handle multicast traffic more efficiently and far better than all previous schemes for both the multicast FIFO architecture as well as the multicast k FIFO queues architecture. Yet, MXRR is both practical and achieves high performance.

An efficient per-VC accounting-based buffer management scheme for GFR services in TCP/IP networks

An efficient per-virtual connection (per-VC) accounting-based scheme with steepest decent weight updating (PASD) algorithm is proposed for buffer management in TCP/IP networks supporting guaranteed frame rate (GFR) services. It can achieve good fairness, high utilization and low delay. Also it can be implemented by a genuine FIFO architecture and thus easily support up to 10 Gbps STM-64 rate.

A display processor conforming to all DTV formats with 188-tap FIR filters and 284 Kb FIFO memories

To achieve a single chip solution for a display processor conforming to all DTV formats, various hardwired approaches such as the write end toggle signal (WETS) based design technique and dynamic voltage sensing FIFO architecture have been developed. As a result, all functions including macroblock-to-raster conversion, frame/filed rate conversion, scan format conversion, and ordinary picture making functions such as color interpolation, enhancement, inverse matrix, on screen display, and D/A conversion have been successfully integrated into a single chip. The display processor has a total memory capacity of 284 Kb and filters with a total of 188 taps in an area of 14.9 mm/spl times/14.9 mm. It was fabricated in 0.5 um CMOS technology with 2-metal.