FPGA Research Articles

Reconfigurable Image Confusion Scheme Using Large Period Pseudorandom Bit Generator Based on Coupled-Variable Input LCG and Clock Divider

This paper presents a reconfigurable image confusion scheme, which uses Linear Congruential Generators (LCGs)-based Pseudorandom Bits Generator (PRBG). The PRBG is based on the variable input-coupled LCG with a reconfigurable clock divider. The proposed algorithm encrypts the input image up to four times successively using different random sequences in every attempt. This new scheme aims to efficiently extract statistically strong pseudorandom sequences from a proposed PRBG with a large keyspace and simultaneously increase the security level of the encrypted image. This PRBG was initially designed on Virtex-5 (XC5VLX110T), Virtex-7 (XC7VX330T) and Artix-7 (XC7A100T) Field Programmable Gate Arrays (FPGAs). The statistical properties of the proposed PRBG for four different configurations are verified by the National Institute of Standards and Technology (NIST) tests. Thereafter, a reconfigurable encryption/decryption algorithm that uses the proposed PRBG is developed for secure image encryption. The encryption process was accomplished using the MATLAB tool after obtaining the PRBG keys from the FPGA. To show the quality and strength of the encryption process, security analysis [correlations and Number of Pixels Change Rate (NPCR)] is performed. Security analysis results are compared with the conventional encryption algorithm to show that the developed reconfigurable encryption scheme provides better results in security tests.

Field-programmable gate array implementation of efficient deep neural network architecture

Deep neural network (DNN) comprises multiple stages of data processing sub-systems with one of the primary sub-systems is a fully connected neural network (FCNN) model. This fully connected neural network model has multiple layers of neurons that need to be implemented using arithmetic units with suitable number representation to optimize area, power, and speed. In this work, the network parameters are analyzed, and redundancy in weights is eliminated. A pipelined and parallel structure is designed for the fully connected network information. The proposed FCNN structure has 16 inputs, 3 hidden layers, and an output layer. Each hidden layer consists of 4 neurons and describes how the inputs are connected to hidden layer neurons to process the raw data. A hardware description language (HDL) model is developed for the proposed structure and the verified model is implemented on Xilinx field-programmable gate array (FPGA). The modified structure comprises registers, demultiplexers, weight registers, multipliers, adders, and read-only memory lookup table (ROM/LUT). The modified architecture implemented on FPGA is estimated to reduce area by 87.5% and improve timing by 3x compared with direct implementation methods.

A triangular-trapezoidal dual-channel shaping algorithm for resistive anode readout systems and its FPGA implementation.

This paper introduces a novel digital triangular-trapezoidal double-channel shaping algorithm to enhance the counting rate of resistive anode detectors. The algorithm is based on the trapezoidal shaping algorithm and improves it. At the extreme counting rate, the trapezoidal shaping algorithm cannot alleviate the pulse pileup, so the counting rate cannot meet the requirements of a high performance detector. The triangular-trapezoidal double-channel shaping algorithm is introduced in the resistance anode detector, which can replace the trapezoidal shaping filtering algorithm to process the output signal of the resistance anode detector and obtain the single photon position information. This improvement improves the counting rate of the resistor anode detector and reduces the resolution degradation caused by pulse pileup. The algorithm is simulated by System Generator software and implemented on FPGA (field programmable gate array). The triangular-trapezoidal double-channel shaping algorithm presented in this paper plays an important role in reducing electronic noise and pulse pileup. The algorithm is subjected to simulation testing, and it can recognize signals with a minimum pulse interval of 1 µs and counting rate up to 1000 kcps.

Efficient turbo product code decoder with Build‐In SRAM‐based transpose memory

AbstractTurbo product codes (TPCs) have been widely used for bit error correction in high‐speed applications such as data storage. This letter introduces an efficient hard‐input hard‐output iterating TPC decoder module. A transpose memory utilizing static random access memory (SRAM) is integrated into the decoder to achieve a low hardware overhead. The transpose memory, based on an 8T SRAM bit‐cell, supports both horizontal (row‐wise), and vertical (column‐wise) read/write operations. It is prototyped under a 28nm high‐k/metal gate stack process with bit‐cell size of 0.582 µm2. This specialized SRAM significantly reduces the hardware overhead when compared with a register‐array‐based transpose memory without significant throughput loss. A field programmable gate array (FPGA) evaluation platform is utilized to emulate the TPC decoder module, and the maximum decoder throughput is up to 6.49 Gbps at 250 MHz.

A pragmatic data processing system for large resistive sensor arrays.

Large resistive sensor arrays (RSAs) show great potential in tactile perception. However, the large number of sensors can result in great hardware overhead and bring difficulties for acquiring and processing mass data timely in transient measurement applications. This paper implements a field programmable gate array (FPGA)-based data processing system for a large RSA of 96 × 96, which shows good power consumption and high-speed wireless data update. For crosstalk-free measure, the zero potential method is improved with bus switches, leading to fewer operational amplifiers required and less negative power consumption. A real-time embedded data processing system is realized by FPGA for excellent parallel processing ability. A high-speed wireless transfer scheme with automatic regulated transfer size is proposed and realized by a wireless fidelity module, which allows timely data analysis at the remote end. Moreover, fault identification of RSAs fabricated by micro-electromechanical system technology is achieved. Tests carried out on a 32 × 32 RSA show that the total power consumption is 2209 mW, including 1261 mW of processors and 948 mW of readout circuits, corresponding to 2.15 mW/pixel. The total negative power consumption of 549 mW has been reduced by 50% compared with the zero potential method. The scanning speed is 400fps, and the wireless transfer speed is up to 120fps when the transceiver and receiver are 5m apart.

A Standard-Cell-Based Neuro-Inspired Integrate-and-Fire Analog-to-Time Converter for Biological and Low-Frequency Signals - Comparison With Analog Version.

Continuous-time asynchronous data converters namely, analog-to-digital converters and analog-to-time converters, can be beneficial for certain types of applications, such as, processing of biological signals with sparse information. A particular case of these converters is the integrate-and-fire converter (IFC) that is inspired by the neural system. If it is possible to develop a standard-cell-based (SCB) IFC circuit to perform well in advanced technology nodes, it will benefit from the simplicity of SCB circuit designs and can be implemented in widely available field-programmable gate arrays (FPGAs). This way, this paper proposes two IFC circuits designed and prototyped in a 130 nm CMOS standard process. The first is a novel SCB open-loop dynamic IFC. The latter, is a closed-loop analog IFC with conventional blocks. This paper presents a through comparison between the two IFC circuits. They have a power dissipation of 59 μW and 53 μW, and an energy per pulse of 18 pJ and 1060 pJ, SCB and analog IFC, respectively. The SCB IFC has one of the lowest energy per pulse consumption reported for IFC circuits. The analog IFC, being fully differential, is to our knowledge the first of its kind. Moreover, they do not require an external clock. They can convert signals with a peak-to-peak amplitude from 1.6 mV to 28 mV and 0.6 mV to 2.4 mV, and a frequency range of 2 Hz to 42 kHz and 10 Hz to 4 kHz, SCB and analog IFC, respectively. Presenting low normalized RMS conversion plus reconstruction errors, below 5.2%. The maximum pulse density (average firing-rate) is 3300 kHz, for the SCB and 50 kHz, for the analog IFC.

Design and Implementation of a Reconfigurable Corrective Control System Subject to Permanent Faults in the Controller.

This article presents a reconfiguration strategy for the corrective controller achieving model matching control of an input/state asynchronous sequential machine (ASM). The considered controller is vulnerable to permanent faults that degenerate a subset of the controller's states. If the controller has a certain amount of redundancy in terms of its states, one can build a reconfiguration scheme in which the functionality of degenerated states is taken over by supplementary states. The proposed reconfiguration scheme is superior to conventional methods of fault tolerance with hardware redundancy since the required number of redundant states is much smaller. Hardware experiments on field-programmable gate array (FPGA) circuits are provided to validate the applicability of the proposed scheme. The present study serves as the first research report on the reconfigurable corrective controller.

Embedded FPGA developments in 130 nm and 28 nm CMOS for machine learning in particle detector readout

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called “FABulous” was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Further development of the eFPGA technology and its application to collider detector readout is discussed.

Robust control of a wind energy conversion system: FPGA real-time implementation

This study employs an FPGA board to implement a robust control technique for wind energy conversion systems (WECS). This approach facilitates extensive testing and validation of the control system across diverse wind conditions, utilizing the FPGA's parallel processing capabilities and advanced control algorithms. This method ensures robustness against nonlinearities and system uncertainties. FPGA-in-the-loop (FIL) testing provides precise and effective simulation results, enabling rapid prototyping and iterative modifications of control algorithms. The effectiveness of the robust control strategy is confirmed by FIL findings, demonstrating significant improvements in WECS stability and efficiency. Furthermore, the study highlights the strategy's potential to enhance WECS reliability and efficiency in real-world applications.

Design of a real-time image processing system based on FPGA

To enhance the real-time performance of image processing, effectively reduce video transmission bandwidth and storage space, and improve transmission efficiency, a real-time image processing system was designed using a Field Programmable Gate Array (FPGA). The system is mainly divided into image acquisition, image processing, and image display subsystems. Images are captured using a camera module and transmitted to the image processing module for processing, and finally displayed via an HDMI monitor. Measurements indicate that the system has strong real-time performance, low power consumption, and high portability, making it valuable in fields such as surveillance and security, medical imaging, and industrial automation.

Survey on Advances in Broadband Signal Generation and Processing of ASIC Semiconductors for Defense Satellites

To replace the field-programmable gate array semiconductors used in the defense satellite industry, we conducted a technical investigation of application-specific integrated circuit (ASIC) semiconductors. The analysis results show that ASIC semiconductors have the heat dissipation, reliability, and radiation resistance capabilities required in a space environment and excellent performance indicators related to the resolution of synthetic aperture radar payloads, such as operating frequency. Research and development of mission-customized ASIC semiconductors that fit the requirements for NSP(new-space paradigm) should be preceded to expanse bases of the space industry, national security capabilities for next-generation space deveolpment also to secure competitiveness of technology and domestic supply chain as space parts itselfs.

Development of Power-Delay Product Optimized ASIC-Based Computational Unit for Medical Image Compression

The proliferation of battery-operated end-user electronic devices due to technological advancements, especially in medical image processing applications, demands low power consumption, high-speed operation, and efficient coding. The design of these devices is centered on the Application-Specific Integrated Circuits (ASIC), General Purpose Processors (GPP), and Field Programmable Gate Array (FPGA) frameworks. The need for low-power functional blocks arises from the growing demand for high-performance computational units that are part of high-speed processors operating at high clock frequencies. The operational speed of the processor is determined by the computational unit, which is the workhorse of high-speed processors. A novel approach to integrating Very Large-Scale Integration (VLSI) ASIC design and the concepts of low-power VLSI compatible with medical image compression was embraced in this research. The focus of this study was the design, development, and implementation of a Power Delay Product (PDP) optimized computational unit targeted for medical image compression using ASIC design flow. This stimulates the research community’s quest to develop an ideal architecture, emphasizing on minimizing power consumption and enhancing device performance for medical image processing applications. The study uses area, delay, power, PDP, and Peak Signal-to-Noise Ratio (PSNR) as performance metrics. The research work takes inspiration from this and aims to enhance the efficiency of the computational unit through minor design modifications that significantly impact performance. This research proposes to explore the trade-off of high-performance adder and multiplier designs to design an ASIC-based computational unit using low-power techniques to enhance the efficiency in power and delay. The computational unit utilized for the digital image compression process was synthesized and implemented using gpdk 45 nm standard libraries with the Genus tool of Cadence. A reduced PDP of 46.87% was observed when the image compression was performed on a medical image, along with an improved PSNR of 5.89% for the reconstructed image.

Convolutional neural network model compression method

In the field of deep learning, Convolutional Neural Networks (CNN) has become a focal point due to its multi-layered structure and wide application. The success of deep learning is due to the model has more layers and more parameters, which gives it a stronger nonlinear fitting ability. Traditionally, CNNs are primarily run on Central Processing Units (CPUs) and Graphics Processing Units (GPUs). However, CPUs have lower computational power, and GPUs consume a lot of energy. In contrast, Field-Programmable Gate Arrays (FPGAs) offer high parallelism, low power consumption, flexible programming, and rapid development cycles. These combined advantages make FPGAs more suitable for the forward inference processes of deep learning compared to other platforms. However, CNNs has the characteristics of parameter redundancy, the storage cost of deploying it on FPGA is too high. In order to apply CNNs to FPGA, we need to optimize CNNs for compression. Because after compression, This paper analyzes several specific cases of model compression for convolutional neural networks, and summarizes and compares the efficient methods of model compression. The results show that the model compression methods are mainly divided into the structure change of convolutional neural network and the quantization of parameters. The two compression methods can be cascaded at the same time to achieve a better optimization effect.

Integrating reliability analysis into MBSE for FPGA-based safety critical I&C system design in nuclear power plants

Abstract With the widespread application of Field Programmable Gate Array (FPGA) technology in the instrumentation and control (I&C) systems of nuclear power plants (NPPs), its design reliability has become the key to ensuring the subsequent safe operation of NPPs. However, the traditional document-based design method is no longer sufficient to meet the current design needs of complex systems, and there is a lack of research related to the reliability and security analysis of FPGA-based systems. Therefore, the overall goal of this study is to integrate reliability analysis into the model-based systems engineering (MBSE)-based design of FPGA-based I&C systems. Based on the typical application characteristics of the FPGA, a digital design framework for FPGA-based systems is proposed to realize a traceable design process from requirements to implementation. Subsequently, a model-based forward comprehensive reliability analysis method is proposed, which uses a SysML-based mapping mechanism to integrate Failure Mode and Effects Analysis (FMEA) and Fault Tree Analysis (FTA) methods into the design process, so as to comprehensively identify and analyze failure modes from systems to components and optimize and improve system design. Finally, the proposed method is applied to the analog output design of FPGA-based systems. The proposed method can provide guidance for improving the reliability of FPGA-based DI&C systems and provide theoretical basis for the further engineering application.

Multichannel information transmission via a dual-frequency point space-time coding metasurface

Space-time coding (STC) digital metasurfaces enable dynamic control of nonlinear harmonics. To achieve efficient frequency tuning and harmonic control, we propose a one-bit column-controlled temporal coding dual-frequency point STC digital metasurface. Using a field-programmable gate array (FPGA) to control diode switching, the metasurface is encoded to generate multiple target reflected harmonics as independent information transmission channels. The amplitude intensities of these harmonics are defined as independent binary symbols for transmission. The proposed space-time coding digital metasurface can achieve a phase shift of 180° in its unit structure, with reflectivities above 90% at both operating frequencies. We fabricated the designed metasurface and tested its far-field scattering experimentally. When the incident electromagnetic wave frequency is 4.63 GHz, the predicted results are essentially consistent with the experimental findings.

Electro-optical logics by three-terminal quantum-well-light-emitting transistors integration

The three-terminal quantum-well-light-emitting transistors (QW-LETs) possess appealing characteristics, including multipath bidirectional electrical and optical inputs/outputs, transistor functionalities, and picosecond recombination lifetimes. This article presents the inaugural demonstration of electro-optical sequential logic circuits—first implementations of set-reset (SR) latches. These two latches feature both electrical and optical connectivities through a three-terminal QW-LET platform. Universal gates, such as NOR and NAND logic gates, have been manufactured and showcased, exhibiting accurate logic functionalities. Additionally, we propose two electro-optical SR latches based on NOR and NAND logic gates—the electro-optical registers, serving as fundamental building blocks for more intricate optoelectronic field-programmable gate arrays. The monolithically integrated QW-LET platform holds the potential to offer a comprehensive range of potent building blocks for optoelectronic chips and high-performance optoelectronic computing.

Novel machine learning-driven optimizing decoding solutions for FPGA-based time-to-digital converters

Calibration of models and data structures is recurring in a large number of cross-cutting applications from finance to engineering. Even though there are numerous and well-established specific calibration techniques for each application sector, using Neural Networks (NNs) can improve performance. For instance, Tapped Delay-Line Time-to-Digital Converters (TDL-TDCs) implemented in Field Programmable Gate Arrays (FPGAs) are increasingly being used in a variety of research applications, such in the time-resolved spectroscopy or in medical imaging mainly for their high-precision and flexibility. Specific decoding on the sampled information from the TDL, together with calibration to compensate for non-idealities, (i.e., Bubble Errors, BEs, and Process–Voltage–Temperature fluctuations, PVTs) are carried out for generating the conversion of digital codes to time units. In this fundamental process, the impact of Machine Learning (ML) usage has not yet been investigated. In this paper, focusing on advanced FPGA devices (i.e., 28-nm, 20-nm, and 16-nm), we propose an approach based on NNs running in Python on a standalone PC to identify the optimal conversion from digital codes to timestamps, comparing it with the classical fully FPGA-based solution c literature. The experimental validations are performed on Artix-7 (XC7A100TFG256-2) and Kintex UltraScale (XCKU040-FFVA1156-2-E) in 28-nm and 20-nm technology nodes, achieving precision of 12.9 ps r.m.s. and 4.85 ps r.m.s., respectively. These results are in line with the state-of-the-art, demonstrating that in 28-nm technology, the bubble compression algorithm is sufficient to achieve high-precision, while reordering mechanism is crucial to compensate for BEs within the 16/20-nm technology node.

A Human-Computer Interaction Strategy for An FPGA Platform Boosted Integrated "Perception-Memory" System Based on Electronic Tattoos and Memristors.

The integrated "perception-memory" system is receiving increasing attention due to its crucial applications in humanoid robots, as well as in the simulation of the human retina and brain. Here, a Field Programmable Gate Array (FPGA) platform-boosted system that enables the sensing, recognition, and memory for human-computer interaction is reported by the combination of ultra-thin Ag/Al/Paster-based electronic tattoos (AAP) and Tantalum Oxide/Indium Gallium Zinc Oxide (Ta2O5/IGZO)-based memristors. Notably, the AAP demonstrates exceptional capabilities in accommodating the strain caused by skin deformation, thanks to its unique structural design, which ensures a secure fit to the skin and enables the prolonged monitoring of physiological signals. By utilizing Ta2O5/IGZO as the functional layer, a high switching ratio is conferred to the memristor, and an integrated system for sensing, distinguishing, storing, and controlling the machine hand of multiple human physiological signals is constructed together with the AAP. Further, the proposed system implements emergency calls and smart homes using facial electromyogram signals and utilizing logical entailment to realize the control of the music interface. This innovative "perception-memory" integrated system not only serves the disabled, enhancing human-computer interaction but also provides an alternative avenue to enhance the quality of life and autonomy of individuals with disabilities.

Coexisting phenomena and antimonotonic evolution in a memristive Shinriki circuit

This paper is aimed at investigating the dynamical behaviors of the Shinriki circuit with a grounded asymmetric diode-bridge-based memristor through the implicit mapping method, including coexisting phenomena and antimonotonicity. To elucidate these behaviors, the basic properties, including equilibrium points and symmetry, of a Shinriki circuit incorporating a grounded asymmetric diode-bridge-based memristor are first illustrated. The discretization scheme for the circuit is established through the implicit mapping method, and the relatively complete bifurcation trees of each periodic motion by tuning a variable resistor can be analyzed through the Newton-Raphson algorithm. The unique unstable periodic bifurcation routes are also revealed. The evolution of antimonotonicity triggered by period-doubling or saddle-node bifurcations, along with the formed unstable motions, are comprehensively discussed. Furthermore, the simulation results are verified via a Field Programmable Gate Array (FPGA), by which both the asymmetric stable and unstable coexisting periodic attractors can be captured. The results will contribute to explaining the dynamical behaviors of numerous memristive circuits from a novel semi-analytical way, thus opening the possibility of analyzing some phenomena, such as unstable bifurcation routes, that cannot be directly observed via the numerical method.

Solar powered high gain DC-DC converter with FPGA controller for portable devices

A solar-powered converter design is necessary for portable devices with increased gain and reduced ripple in overall operation. This research presents a photovoltaic-powered Field Programmable Gate Array (FPGA) based on increased gain multiple output converter design and analysis. The dynamic panel input makes it difficult to operate the load. To control and make the input static to satisfy the demand, perturb and observe with a load balancing algorithm technique are used. The converter gained output is high, and batteries are used to balance the loads when solar irradiance is low. Simulation results were carried out with the presented converter circuit that can be operated with a 12 V supply as input from a renewable power source. The output gain ratio of 14 to a minimum of 40 % duty cycle operating at a switching frequency of 20 kHz has been achieved. The proposed methodology is transferred to hardware by connecting with the reconfigurable FPGA Spartan-6 development board to manage the dynamic load control system's complex logic and high processing ability. The overall performance is compared with various pre-existing systems, tabulations are made with the analysis, and experimental results are also illustrated at the end.