FPGA Research Articles

Performance Analysis of Approximate Parallel Prefix Adders Realized with Field-programmable Gate Array Technology

Introduction: Parallel prefix adders are widely used in high-speed arithmetic circuits due to their ability to perform additions in logarithmic time. However, the high area and delay of exact parallel prefix adders prompted the development of approximate parallel prefix adders. These adders are a promising solution for high-speed arithmetic circuits because they sacrifice accuracy for reduced area and delay. Methods: This paper presents a performance analysis of five approximate parallel prefix adders realized with field programmable gate array technology. The five approximate parallel prefix adders are the Kogge-Stone adder, the Sklansky adder, the Brent-Kung adder, the Han-Carlson adder, and the Ladner-Fisher. Each adder is implemented in a Xilinx Artix-7 FPGA. The area and delay of five approximate parallel prefix adders are evaluated. The Kogge-Stone approximate parallel prefix adder, out of five approximate parallel prefix adders, consumes the least delay, irrespective of the number of bits. Results: The Sklansky approximate parallel prefix adder out of five approximate parallel prefix adders consumes the least area irrespective of the number of bits in addition. Overall, our research sheds light on the trade-offs between area, power delay, and power delay products of five approximate parallel prefix adders implemented with FPGA technology. Conclusion: This analysis can help choose the best approximate parallel prefix adder for specific high-speed arithmetic applications. In the case of 16- and 32-bit five approximate parallel prefix adders, Ladner-fisher shows the best power delay product, whereas 64- and 128-bit five approximate parallel prefix adders, Sklansky adder shows the best power delay product.

A brain machine interface framework for exploring proactive control of smart environments

Brain machine interfaces (BMIs) can substantially improve the quality of life of elderly or disabled people. However, performing complex action sequences with a BMI system is onerous because it requires issuing commands sequentially. Fundamentally different from this, we have designed a BMI system that reads out mental planning activity and issues commands in a proactive manner. To demonstrate this, we recorded brain activity from freely-moving monkeys performing an instructed task and decoded it with an energy-efficient, small and mobile field-programmable gate array hardware decoder triggering real-time action execution on smart devices. Core of this is an adaptive decoding algorithm that can compensate for the day-by-day neuronal signal fluctuations with minimal re-calibration effort. We show that open-loop planning-ahead control is possible using signals from primary and pre-motor areas leading to significant time-gain in the execution of action sequences. This novel approach provides, thus, a stepping stone towards improved and more humane control of different smart environments with mobile brain machine interfaces.

Exploring memory synchronization and performance considerations for FPGA platform using the high-abstracted OpenCL framework: Benchmarks development and analysis.

A key benefit of the Open Computing Language (OpenCL) software framework is its capability to operate across diverse architectures. Field programmable gate arrays (FPGAs) are a high-speed computing architecture used for computation acceleration. This study investigates the impact of memory access time on overall performance in general FPGA computing environments through the creation of eight benchmarks within the OpenCL framework. The developed benchmarks capture a range of memory access behaviors, and they play a crucial role in assessing the performance of spinning and sleeping on FPGA-based architectures. The results obtained guide the formulation of new implementations and contribute to defining an abstraction of FPGAs. This abstraction is then utilized to create tailored implementations of primitives that are well-suited for this platform. While other research endeavors concentrate on creating benchmarks with the Compute Unified Device Architecture (CUDA) to scrutinize the memory systems across diverse GPU architectures and propose recommendations for future generations of GPU computation platforms, this study delves into the memory system analysis for the broader FPGA computing platform. It achieves this by employing the highly abstracted OpenCL framework, exploring various data workload characteristics, and experimentally delineating the appropriate implementation of primitives that can seamlessly integrate into a design tailored for the FPGA computing platform. Additionally, the results underscore the efficacy of employing a task-parallel model to mitigate the need for high-cost synchronization mechanisms in designs constructed on general FPGA computing platforms.

FPGA-enhanced IoT methods for disease pre-screening and prediction: An energy optimization approach

The research paper has introduced a system based on the Internet of Things (IoT) that has the potential to contribute to the creation of a Consumer Electronics (CE) product. In the event that any health-related measure deviates from the normal range, this system, which is based on IoT technology, will send a notification to the user. The data collected by this system is sent to an analysis system based on a Field Programmable Gate Array (FPGA) through a mobile application, and then transferred to the cloud for storage. To display this raw data, a wearable IoT device can be utilized, and the system will process the data accordingly. The major innovation of this proposed project lies in the development of a fuzzy classifier that can accurately predict the pathological condition of an illness. By implementing a fuzzy classifier using FPGA, the execution time is greatly reduced i.e. 57.7μs compared to other algorithms. Ans also the accuracy of the proposed model is 98.8 %, which higher then other machine learning model such as 97 %, 96.5 %, 93.2 % respectively for SVM, KNN and DT models.previous models like KNN, DT, SVM, and NB (Naive Bayes).

An Edge Computing System with AMD Xilinx FPGA AI Customer Platform for Advanced Driver Assistance System.

The convergence of edge computing systems with Field-Programmable Gate Array (FPGA) technology has shown considerable promise in enhancing real-time applications across various domains. This paper presents an innovative edge computing system design specifically tailored for pavement defect detection within the Advanced Driver-Assistance Systems (ADASs) domain. The system seamlessly integrates the AMD Xilinx AI platform into a customized circuit configuration, capitalizing on its capabilities. Utilizing cameras as input sensors to capture road scenes, the system employs a Deep Learning Processing Unit (DPU) to execute the YOLOv3 model, enabling the identification of three distinct types of pavement defects with high accuracy and efficiency. Following defect detection, the system efficiently transmits detailed information about the type and location of detected defects via the Controller Area Network (CAN) interface. This integration of FPGA-based edge computing not only enhances the speed and accuracy of defect detection, but also facilitates real-time communication between the vehicle's onboard controller and external systems. Moreover, the successful integration of the proposed system transforms ADAS into a sophisticated edge computing device, empowering the vehicle's onboard controller to make informed decisions in real time. These decisions are aimed at enhancing the overall driving experience by improving safety and performance metrics. The synergy between edge computing and FPGA technology not only advances ADAS capabilities, but also paves the way for future innovations in automotive safety and assistance systems.

Design and Simulation of Clock Divider using VHDL

This paper presents the diesign and simulation of clock divider circuit using VHDL(VHSIC Hardware Description Language) on an FPGA(Field Programmable Gate Array). The clock divider circuit is a fundamental component in digital system for generating lower frequency clocks from a higher frequency reference clock. The paper starts up with simple divider where the clock is divided by even numbers, odd numbers and then later expands it into non- integer dividers. Keywords:- clock divider, D flipflop, FPGA

Reg-Tune: A Regression-Focused Fine-Tuning Approach for Profiling Low Energy Consumption and Latency

Fine-tuning deep neural networks is pivotal for creating inference modules that can be suitably imported to edge or field-programmable gate array (FPGA) platforms. Traditionally, exploration of different parameters throughout the layers of deep neural networks has been done using grid search and other brute force techniques. Although these methods lead to the optimal choice of network parameters, the search process can be very time consuming and may not consider deployment constraints across different target platforms. This work addresses this problem by proposing Reg-Tune, a regression-based profiling approach to quickly determine the trend of different metrics in relation to hardware deployment of neural networks on tinyML platforms like FPGAs and edge devices. We start by training a handful of configurations belonging to different combinations of \(\mathcal {NN}\scriptstyle \langle q (quantization),\,s (scaling)\rangle \displaystyle\) or \(\mathcal {NN}\scriptstyle \langle r (resolution),\,s\rangle \displaystyle\) workloads to generate the accuracy values respectively for their corresponding application. Next, we deploy these configurations on the target device to generate energy/latency values. According to our hypothesis, the most energy-efficient configuration suitable for deployment on the target device is a function of the variables q , r , and s . Finally, these trained and deployed configurations and their related results are used as data points for polynomial regression with the variables q , r , and s to realize the trend for accuracy/energy/latency on the target device. Our setup allows us to choose the near-optimal energy-consuming or latency-driven configuration for the desired accuracy from the contour profiles of energy/latency across different tinyML device platforms. To this extent, we demonstrate the profiling process for three different case studies and across two platforms for energy and latency fine-tuning. Our approach results in at least 5.7 \(\times\) better energy efficiency when compared to recent implementations for human activity recognition on FPGA and 74.6% reduction in latency for semantic segmentation of aerial imagery on edge devices compared to baseline deployments.

MS-LW-TI: Primitive-Based First-Order Threshold Implementation for 4 × 4 S-boxes

Threshold implementation (TI) is a lightweight countermeasure against side-channel attacks when glitches happen. As to masking schemes, an S-box is the key part to protection. In this paper, we propose a general first-order lightweight TI scheme for 4 × 4 S-boxes and name it as MiniSat-lightweight-threshold implementation (MS-LW-TI). First, we use MiniSat to optimally decompose an S-box into the least number of three different logic gate operations, AND, OR, and XOR. Among these operations, we define two primitives and the extension of two primitives for TI design. Furthermore, we prove that the primitives and their extensions strictly comply with the security properties. Finally, we implement MS-LW-TI on Xilinx Spartan-6 Field Programmable Gate Array (FPGA) to show that the S-boxes of PRESENT, GIFT, and PICCOLO consume only 17, 15, and 13 look-up-tables (LUTs), 16, 9, and 16 flip-flops (FFs), 6, 5, and 6 slices, respectively. Compared with the existing lightweight TI design, our TI for PRESENT S-box has a 22%, 38%, and 25% reduction of LUTs, FFs, and slices to the design by Shahmirzadi and Moradi at IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES) 2021, and our TI for GIFT S-box has a 6%, 25%, and 28% reduction of LUTs, FFs, and slices to the design by Jati et al., which is the smallest.

Dual-Frequency, Dual-Mode Reconfigurable Digital Atmospheric Radar Receiver Design

A new dual-frequency, dual-mode reconfigurable digital receiver based on Field-Programmable Gate Array (FPGA) dynamic reconfiguration is proposed, which is based on a common hardware platform of high-bandwidth RF front-end, high-speed data acquisition, and real-time signal processing. The receiver adopts the design of dynamically reconfigurable down-conversion, filter extraction, and matched filtering in the digital domain. In this study, we completed the design and development of the digital receiver, experimental platform construction, and field detection test with hardware and software cooperation. The experimental results show that the receiver achieves full digital reception and signal processing for 53.8 MHz stratosphere–troposphere (ST) detection and 35.0 MHz meteor detection and successfully acquired the number of meteors versus time, the meteor trail, and low-altitude atmospheric radial winds. This dual-frequency, dual-mode reconfigurable digital receiver can be applied to new-generation multifunction integrated radar systems such as dual-frequency ST/meteor radars.

Rapid Prototyping and Hardware-In-the-Loop Verification of Enhanced Sliding Mode Control of an Asynchronous Machine Using a Xilinx System Generator and an FPGA-Zynq Board

This article describes rapid prototyping using the Xilinx system generator (XSG) of a direct field oriented control (DFOC) strategy based on improved super twisting sliding mode controllers (ISTSMCs) of an asynchronous machine to succeed a hardware implementation on a field programmable gate array (FPGA) board. The main goal is to enhance regulation loops governing rotor speed, rotor flux, and stator current components within the classical DFOC structure. These ISTSMCs replace integral proportional controllers, resulting in improved system dynamics, faster speed and torque responses, and heightened robustness against load and rotor resistance variations, surpassing other control methods. Additionally, the article aims to implement this DFOC-ISTSMC method on an FPGA board to reduce control system sampling time and loop delays, leveraging the FPGA’s parallel processing capabilities. The hardware architecture is designed using XSG in the MATLAB/Simulink environment, enabling effective simulation, testing, discrete algorithm creation, and VHDL code generation for FPGA implementation via the hardware-in-the-loop (HIL) process. Assessment involves digital simulation studies and HIL processes using XSG with a Xilinx FPGA Zynq 7000 under MATLAB/Simulink, demonstrating improved system performance, reduced time delays, and efficient FPGA utilization. This approach validates the effectiveness of the proposed DFOC-ISTSMC algorithm in enhancing control strategy for asynchronous machines.

Adaptive neuro fuzzy technology to enhance PID performances within VCA for grid-connected wind system under nonlinear behaviors: FPGA hardware implementation

Wind Energy Conversion Systems (WECSs) exhibit nonlinear behavior due to internal and external disturbances, which can significantly impact the control performance. Firstly, this paper proposes a Vector Control Approach (VCA) based on Adaptive Neuro Fuzzy (ANF) of Proportional Integral Derivative (PID) controllers for a variable speed Permanent Magnet Synchronous Generator (PMSG)-based WECS connected to the grid to address these issues. The proposed ANF-PID controller combines the robustness of the fuzzy logic with the neural network's performance to ensure high accuracy, excellent tracking, and robustness against the WECS's nonlinear behavior. The neural network automates the placement of fuzzy logic membership functions. Secondly, this paper suggests a real-time hardware implementation of the VCA based on ANF-PID using a Field Programmable Gate Array (FPGA) to reduce the processing time and the WECS's sampling period. The effectiveness of the VCA based on ANF-PID controllers is validated by conducting a numerical simulation within the Matlab-Simulink using the Xilinx System Generator tool, alongside an experimental in-the-loop hardware implementation using FPGA board. Different scenarios are conducted to validate the robustness and stability of the proposed VCA based on ANF-PID control schemes, which is compared to Conventional Fuzzy PID (C-FPID) and PID controllers. The results exhibit that the VCA based on ANF-PID controllers outperforms VCA-C-FPID and VCA-PID controllers in terms of precision, tracking accuracy, and robustness against the WECS's nonlinear behavior and the PMSG parameter variations. The performances of the proposed controllers are tested under some criteria. In fact, the proposed ANF-PID controller provides a Mean Absolute Error (MAE), a Mean Squared Error (MSE) and a Root Mean Squared Error (RMSE) of 8.1911 × 10−04, 8.4181 × 10−05 and 0.0092, respectively. Compared to the C-FPID controller, the proposed controller offers an improvement gain of 98.96 %, 99.61 %, and 93.79 % of MAE, MSE, and RMSE, respectively. When compared to the PID controller, its improvement is even more significant, with a reduction of 99.9919 %, 99.9999 %, and 99.9288 % of MAE, MSE, and RMSE, respectively. In addition, the ANF-PID-based VCA utilizes hardware resources on the FPGA efficiently, requiring only 65.60 % slices LUT, 0.28 % LUTRAM, and 22.99 % FF. This makes it a more cost-effective option compared to the VCA-C-FPID controller for diverse control systems.

GLRM: Geometric Layout-Based Resource Management Method on Multiple Field Programmable Gate Array Systems

Multiple field programmable gate array (Multi-FPGA) systems are capable of forming larger and more powerful computing units through high-speed interconnections between chips and are beginning to be widely used by various computing service providers. However, the new computing architecture brings new challenges to the system’s task resource management. Existing resource management methods do not fully exploit resources in Multi-FPGA systems, and it is difficult to support fast resource request and release. In this regard, we propose a geometric layout-based resource management (GLRM) method for Multi-FPGA systems. First, a geometric layout-based task combination algorithm (TCA) was proposed to ensure that the final system can use the available FPGA resources more efficiently. Then, we optimised two resource management algorithms using TCA. Compared with state-of-the-art resource management methods, TCA increases resource flexibility by an average of 6% and resource utilisation by an average of 7%, and the two optimised resource management methods are effective in improving resource management performance.

Controlling chaos using edge computing hardware

Machine learning provides a data-driven approach for creating a digital twin of a system – a digital model used to predict the system behavior. Having an accurate digital twin can drive many applications, such as controlling autonomous systems. Often, the size, weight, and power consumption of the digital twin or related controller must be minimized, ideally realized on embedded computing hardware that can operate without a cloud-computing connection. Here, we show that a nonlinear controller based on next-generation reservoir computing can tackle a difficult control problem: controlling a chaotic system to an arbitrary time-dependent state. The model is accurate, yet it is small enough to be evaluated on a field-programmable gate array typically found in embedded devices. Furthermore, the model only requires 25.0 ±7.0\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\pm 7.0$$\\end{document} nJ per evaluation, well below other algorithms, even without systematic power optimization. Our work represents the first step in deploying efficient machine learning algorithms to the computing “edge.”

Distilling particle knowledge for fast reconstruction at high-energy physics experiments

Knowledge distillation is a form of model compression that allows artificial neural networks of different sizes to learn from one another. Its main application is the compactification of large deep neural networks to free up computational resources, in particular on edge devices. In this article, we consider proton-proton collisions at the High-Luminosity Large Hadron Collider (HL-LHC) and demonstrate a successful knowledge transfer from an event-level graph neural network (GNN) to a particle-level small deep neural network (DNN). Our algorithm, DistillNet, is a DNN that is trained to learn about the provenance of particles, as provided by the soft labels that are the GNN outputs, to predict whether or not a particle originates from the primary interaction vertex. The results indicate that for this problem, which is one of the main challenges at the HL-LHC, there is minimal loss during the transfer of knowledge to the small student network, while improving significantly the computational resource needs compared to the teacher. This is demonstrated for the distilled student network on a CPU, as well as for a quantized and pruned student network deployed on an field programmable gate array. Our study proves that knowledge transfer between networks of different complexity can be used for fast artificial intelligence (AI) in high-energy physics that improves the expressiveness of observables over non-AI-based reconstruction algorithms. Such an approach can become essential at the HL-LHC experiments, e.g. to comply with the resource budget of their trigger stages.

Enhancing Blockchain Security and Efficiency through FPGA-Based Consensus Mechanisms and Post-Quantum Cryptography

Introduction: Blockchain technology has revolutionized data management and transaction recording, extending its application beyond cryptocurrencies to various sectors, including Central Bank Digital Currencies (CBDCs) Method: This distributed ledger technology offers a transparent, immutable, and secure transaction platform, reducing the risk of data tampering and increasing resistance to attacks. However, challenges such as performance, scalability, and security continue to exist; these challenges are particularly concerning consensus mechanisms like Proof of Work (PoW). Field-Programmable Gate Arrays (FPGAs) present a promising solution to enhance the efficiency and security of blockchain consensus mechanisms. Result: This study explores the implementation of blockchain in embedded systems using FPGAs and discusses the post-quantum cryptographic algorithms to ensure long-term protection. Conclusion: The research highlights the potential of FPGA-based implementations to revolutionize blockchain applications, emphasizing the need for continuous adaptation and vigilance to address evolving security threats, particularly those posed by quantum computing.

Software and hardware realizations for different designs of chaos-based secret image sharing systems

Secret image sharing (SIS) conveys a secret image to mutually suspicious receivers by sending meaningless shares to the participants, and all shares must be present to recover the secret. This paper proposes and compares three systems for secret sharing, where a visual cryptography system is designed with a fast recovery scheme as the backbone for all systems. Then, an SIS system is introduced for sharing any type of image, where it improves security using the Lorenz chaotic system as the source of randomness and the generalized Arnold transform as a permutation module. The second SIS system further enhances security and robustness by utilizing SHA-256 and RSA cryptosystem. The presented architectures are implemented on a field programmable gate array (FPGA) to enhance computational efficiency and facilitate real-time processing. Detailed experimental results and comparisons between the software and hardware realizations are presented. Security analysis and comparisons with related literature are also introduced with good results, including statistical tests, differential attack measures, robustness tests against noise and crop attacks, key sensitivity tests, and performance analysis.

Dual threshold input receiver FPGA-only signal digitization method for time-of-flight positron emission tomography

As silicon photomultiplier (SiPM)-based time-of-flight (TOF) positron emission tomography (PET) becomes popular, the need for sophisticated PET data acquisition (DAQ) systems is increasing. One promising solution to this challenge is the adoption of a field-programmable gate array (FPGA)-only signal digitization method. In this paper, we propose a new approach to efficiently implement an FPGA-only digitizer. We configured the input/output (IO) port of the FPGA to function as a dual-threshold voltage comparator through the use of simple passive circuitry and heterogeneous IO standards. This configuration overcomes the limitations of existing methods by allowing different threshold voltages for adjacent IO pins, effectively reducing routing complexity and lowering manufacturing costs. An FPGA-only digitizer was implemented by integrating the dual-threshold voltage comparator and FPGA-based time-to-digital converter. By combining the dual-threshold time-over-threshold (TOT) method and curve fitting, precise energy information could be obtained. The performance of the FPGA-only digitizer was assessed using a detector setup comprising a 3 × 3 × 20 mm3 LYSO scintillation crystal and a single pixel SiPM. Using the configured evaluation setup, an energy resolution of 12.5% and a time resolution of 146 ± 9 ps were achieved for a 20 mm scintillation crystal. The dual-threshold TOT implemented using the proposed method showed consistent linearity across an energy range of 100 keV to 600 keV. The proposed method is well-suited for the development of cost-effective DAQ systems in highly integrated TOF PET systems.

A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs

In the digital era, the prevalence of low-quality images contrasts with the widespread use of high-definition displays, primarily due to low-resolution cameras and compression technologies. Image super-resolution (SR) techniques, particularly those leveraging deep learning, aim to enhance these images for high-definition presentation. However, real-time execution of deep neural network (DNN)-based SR methods at the edge poses challenges due to their high computational and storage requirements. To address this, field-programmable gate arrays (FPGAs) have emerged as a promising platform, offering flexibility, programmability, and adaptability to evolving models. Previous FPGA-based SR solutions have focused on reducing computational and memory costs through aggressive simplification techniques, often sacrificing the quality of the reconstructed images. This paper introduces a novel SR network specifically designed for edge applications, which maintains reconstruction performance while managing computation costs effectively. Additionally, we propose an architectural design that enables the real-time and end-to-end inference of the proposed SR network on embedded FPGAs. Our key contributions include a tailored SR algorithm optimized for embedded FPGAs, a DSP-enhanced design that achieves a significant four-fold speedup, a novel scalable cache strategy for handling large feature maps, optimization of DSP cascade consumption, and a constraint optimization approach for resource allocation. Experimental results demonstrate that our FPGA-specific accelerator surpasses existing solutions, delivering superior throughput, energy efficiency, and image quality.

Day–Night architecture: Development of an ultra-low power RISC-V processor for wearable anomaly detection

In healthcare, anomaly detection has emerged as a central application. This study presents an ultra-low power processor tailored for wearable devices dedicated to anomaly detection. Introducing a unique Day–Night architecture, the processor is bifurcated into two distinct segments: The Day segment and the Night segment, both of which function autonomously. The Day segment, catering to generic wearable applications, is designed to remain largely inactive, awakening only for specific tasks. This approach leads to considerable power savings by incorporating the Main-CPU and system interconnect, both major power consumers. Conversely, the Night segment is dedicated to real-time anomaly detection using sensor data analytics. It comprises a Sub-CPU and a minimal set of IPs, operating continuously but with minimized power consumption. To further enhance this architecture, the paper presents an ultra-lightweight RISC-V core, All-Night core, specialized for anomaly detection applications, replacing the traditional Sub-CPU. To validate the Day–Night architecture, we developed a prototype processor and implemented it on an FPGA board. An anomaly detection application, optimized for this prototype, was also developed to showcase its functional prowess. Finally, when we synthesized the processor prototype using 45 nm process technology, it affirmed our assertion of achieving an energy reduction of up to 57%.

A low-latency graph computer to identify metastable particles at the Large Hadron Collider for real-time analysis of potential dark matter signatures

Image recognition is a pervasive task in many information-processing environments. We present a solution to a difficult pattern recognition problem that lies at the heart of experimental particle physics. Future experiments with very high-intensity beams will produce a spray of thousands of particles in each beam-target or beam-beam collision. Recognizing the trajectories of these particles as they traverse layers of electronic sensors is a massive image recognition task that has never been accomplished in real time. We present a real-time processing solution that is implemented in a commercial field-programmable gate array using high-level synthesis. It is an unsupervised learning algorithm that uses techniques of graph computing. A prime application is the low-latency analysis of dark-matter signatures involving metastable charged particles that manifest as disappearing tracks.