Field Programmable Gate Array System Research Articles

SoC-FPGA Based Concept of Hardware Aided Quantum Simulation

Contemporary industry and science expectations towards technological solutions set the bar high. Current approaches to increasing the computing power of standard systems are reaching the limits of physics known to humankind. Fast, programmable systems with relatively low power consumption are a different concept for performing complex calculations. Highly parallel processing opens up a number of possibilities in the context of accelerating calculations. Application of SoC (System On Chip) with FPGA (Field-Programmable Gate Array) enables to delegate of a part of computations to the gates matrix, thereby expediting processing by using parallelization of hardware operations. This paper presents the general concept of using SoC FPGA systems to support CPU (Central Processing Unit) in many modern tasks. While some tasks might be really hard to implement on an FPGA in a reasonable time, the SoC FPGA platform allows for easy low-level interconnections, and with such virtualized access to the hardware computing resources, it is seen as making FPGAs, or hardware in general, more accessible to engineers accustomed to high-level solutions. The concept presented in the article takes into account the limited resources of cheaper educational platforms, which, however, still provide an interesting and alternative hybrid solution to the problem of parallelization and acceleration of data processing. This allows to overcome encountered limitations and maintain the flexibility known from high-level solutions and high performance achieved with low-level programming, without the need for a high financial background.

An Energy-Efficient Field-Programmable Gate Array Rapid Implementation of a Structural Health Monitoring System

System health monitoring (SHM) of a ball screw laboratory system using an embedded real-time platform based on Field-Programmable Gate Array (FPGA) technology was developed. The ball screw condition assessment algorithms based on machine learning approaches implemented on multiple platforms were compared and evaluated. Studies on electric power consumption during the processing of the proposed structure of a neural network, implementing SHM, were carried out for three hardware platforms: computer, Raspberry Pi 4B, and Kria KV260. It was found that the average electrical power consumed during calculations is the lowest for the Kria platform using the FPGA system. However, the best ratio of the average power consumption to the accuracy of the neural network was obtained for the Raspberry Pi 4B. The concept of an efficient and energy-saving hardware platform that enables monitoring and analysis of the operation of the selected dynamic system was proposed. It allows for easy integration of many software environments (e.g., MATLAB and Python) with the System-on-a-Chip (SoC) platform containing an FPGA and a CPU.

Development and Implementation of an FPGA-Embedded Multimedia Remote Monitoring System for Information Technology Server Room Management

Conventional data acquisition systems face challenges in achieving high acquisition speeds and rapid storage of large data volumes using microcontrollers. In contrast, field-programmable gate arrays (FPGAs) offer numerous advantages, including high clock frequencies, minimal internal delays, fast operational speeds, abundant internal RAM resources, and simplified control of complex peripheral circuits. This study presents the design of an FPGA-based multimedia remote monitoring system for information technology server rooms. The proposed system utilizes an FPGA as the primary controller and incorporates environmental sensors, electrical energy sensors, carbon monoxide sensors, smoke sensors, and A/D converter modules to monitor multiple locations within the server room. Simultaneously, the FPGA transmits the collected data from each monitoring point via a serial port to an LCD serial screen for display. An alarm is triggered if any environmental anomalies are detected, indicating abnormal statuses. Additionally, the system employs the fast Fourier transform algorithm and butterfly operations to derive voltage and current AC quantities, while utilizing relative temperature differences to identify equipment faults within the server room. The system is evaluated in terms of functionality, user-friendliness, and reliability. Experimental results demonstrate that all performance measures align with expectations, fulfilling the initial design objectives and highlighting the potential applicability and relevance of FPGA technology in the monitoring field. In addition, a comparison between FPGA and traditional microcontroller systems is performed, showcasing the superior processing speed and performance of the FPGA-based system. This comparative analysis further validates the advantages of using FPGA technology in high-speed data acquisition and monitoring applications.

Acceleration of convolutional neural network based diabetic retinopathy diagnosis system on field programmable gate array

Diabetic retinopathy (DR) is one of the most common causes of blindness. The necessity for a robust and automated DR screening system for regular examination has long been recognized in order to identify DR at an early stage. In this paper, an embedded DR diagnosis system based on convolutional neural networks (CNNs) has been proposed to assess the proper stage of DR. We coupled the power of CNN with transfer learning to design our model based on state-of-the-art architecture. We preprocessed the input data, which is color fundus photography, to reduce undesirable noise in the image. After training many models on the dataset, we chose the adopted ResNet50 because it produced the best results, with a 92.90% accuracy. Extensive experiments and comparisons with other research work show that the proposed method is effective. Furthermore, the CNN model has been implemented on an embedded target to be a part of a medical instrument diagnostic system. We have accelerated our model inference on a field programmable gate array (FPGA) using Xilinx tools. Results have confirmed that a customized FPGA system on chip (SoC) with hardware accelerators is a promising target for our DR detection model with high performance and low power consumption.

Data-driven model for process evaluation in wire EDM

To digitalize the wire EDM process, data-driven models are necessary for evaluating its performance. This presents a challenge due to the high volume of data and the stochastic nature of the process. In this paper, electrical parameters are measured and processed by an FPGA (field programmable gate array) system to recognize and characterize temporally and spatially resolved single discharges as either normal or abnormal. Supervised machine learning methods such as artificial neural networks (ANN) are used and models are trained with different data sets to predict the machined geometrical accuracy and cutting speed based on recorded process data.

A field-programmable gate array (FPGA)-based data acquisition system for closed-loop experiments.

We describe a custom and open source field-programmable gate array (FPGA)-based data acquisition (DAQ) system developed for electrophysiology and generally useful for closed-loop feedback experiments. FPGA acquisition and processing are combined with high-speed analog and digital converters to enable real-time feedback. The digital approach eases experimental setup and repeatability by allowing for system identification and in situ tuning of filter bandwidths. The FPGA system includes I2C and serial peripheral interface controllers, 1 GiB dynamic RAM for data buffering, and a USB3 interface to Python software. The DAQ system uses common HDMI connectors to support daughtercards that can be customized for a given experiment to make the system modular and expandable. The FPGA-based digital signal processing (DSP) is used to generate fourth-order digital infinite impulse response filters and feedback with microsecond latency. The FPGA-based DSP and an analog inner-loop are demonstrated via an experiment that rapidly steps the voltage of a capacitor isolated from the system by a considerable resistance using a feedback approach that adjusts the driving voltage based on the digitized capacitor current.

Detecting Discontinuities From In Situ Space Measurements: Method and FPGA Implementation

AbstractThe analysis in real time of space data variability is essential for scientists and space mission controllers. Automated tools designed to extract key descriptors of variability are needed and solutions to adapt such algorithms for on‐board computers are rare. This paper describes the design of an automated system for detecting directional discontinuities of a physical quantity and its implementation in Field‐Programmable Gate Array (FPGA). The system is currently adapted for solar wind or terrestrial magnetosheath magnetic field directional discontinuities, that is, sharp changes of the magnetic field directionality. Our detection algorithm uses analysis windows of adjustable width and averaging procedures in order to reduce the effects of random fluctuations. A sliding‐window approach is designed for continuous monitoring and detection of magnetic directional discontinuities. A software implementation of the algorithm was tested using in‐situ magnetic field measurements, and emphasized improvements of performance when using analysis windows of adjustable width. The FPGA implementation of the detection algorithm is built on DILIGENT Nexys 4 DDR featuring a commercial Xilinx Artix‐7 device and is designed to be ported to space qualified infrastructure. The FPGA system was tested with synthetic and laboratory signals, and provides results in very good agreement with the software implementation. The FPGA system provides an efficient real‐time monitoring solution using minimal computational and energy resources, and reducing the main on‐board computer utilization.

Constrained Optimization of FPGA Design for Spaceborne InSAR Processing

With the development of spaceborne processing technologies, the demand for on-board processing has risen sharply. Against this background, spaceborne Interferometric Synthetic Aperture Radar (InSAR) processing has become an important research area. In many cases, high processing capacity is required during on-board InSAR processing, yet Field-Programmable Gate Array (FPGA) resources on the satellites are limited. To improve the performance of spaceborne remote sensing processing, this paper designs a high-performing FPGA system for the coarse registration and interferogram generation process of InSAR. Moreover, to address this dual-constraint problem of resource and processing capacity, the paper proposes an FPGA design method based on the gradient descent theory, which can identify the optimum trade-off scheme between two such constraints. Finally, the proposed system design and method are implemented in FPGA. Experiments showed that the FPGA system outperformed the NVIDIA (Santa Clara, CA, USA) GTX Titan Black Graphics Processing Unit (GPU), and the optimum trade-off scheme only increases the entire time by 1.1% but reduces the FPGA BRAM usage by 8.7%. The experimental results proved the effectiveness and validity of the proposed system and method.

New artificial neural network design for Chua chaotic system prediction using FPGA hardware co-simulation

<p>This study aims to design a new architecture of the artificial neural networks (ANNs) using the Xilinx system generator (XSG) and its hardware co-simulation equivalent model using field programmable gate array (FPGA) to predict the behavior of Chua’s chaotic system and use it in hiding information. The work proposed consists of two main sections. In the first section, MATLAB R2016a was used to build a 3×4×3 feed forward neural network (FFNN). The training results demonstrate that FFNN training in the Bayesian regulation algorithm is sufficiently accurate to directly implement. The second section demonstrates the hardware implementation of the network with the XSG on the Xilinx artix7 xc7a100t-1csg324 chip. Finally, the message was first encrypted using a dynamic Chua system and then decrypted using ANN’s chaotic dynamics. ANN models were developed to implement hardware in the FPGA system using the IEEE 754 Single precision floating-point format. The ANN design method illustrated can be extended to other chaotic systems in general.</p>

Design of ASIC and FPGA system with Supervised Machine Learning Algorithms for Solar Particle Event Hourly Prediction

The magnitude of soft error rate (SER) of integrated circuits (ICs) utilized in space missions is jeopardized due to the inconsistent intensity of radiation exposure. To protect critical electronic elements and ensure desired system performance, it is necessary to establish the real-time detection of space particle events (SPE). This research study assesses eight supervised machine learning algorithms by varying history data length (3 to 24 hours) to predict the occurrence of SPE one hour ahead. Customized SPE hourly predictor based on logistic regression is chosen for hardware implementation owing to high prediction accuracy (96.35%) as well as simplicity. After that, the optimal prototype design of the logistic regression algorithm is implemented on Field Programmable Gate Array (FPGA) with affordable hardware footprint. Finally, the digital design tested on FPGA is simulated to generate an application-specific integrated circuit (ASIC) chip layout (industrial 130 nm) integrated with SPE hourly predictor.

Prediction of Geometrical Accuracy in Wire EDM by Analyzing Process Data

In order to digitalize the wire EDM process, data-driven models for the evaluation of the process performance have to be developed. The challenge is the huge amount of data and the stochastically process behavior. Such a model could be used to predict the geometrical accuracy of machined workpieces as well as for development of new machining technologies. In this paper, the produced geometrical accuracy is predicted by continuously recorded process data. For this purpose, electrical parameters are measured and processed by using a FPGA (Field Programmable Gate Array) system to detect spatially resolved single discharges during the process characterized as normal or abnormal discharges. Afterwards, the recorded data are systematically reduced by averaging the process data over defined time intervals. For this purpose, unsupervised machine learning methods are used to ensure that no relevant information is lost. Finally, the processed data is analyzed and statistical parameters are correlated with the machined geometrical accuracy.

FPGA Implementation for Rapid Prototyping of High Performance Voltage Source Inverters

Field-programmable gate array (FPGA) is a powerful platform that can play an essential role in high-performance digital control of power electronics systems. However, the FPGA system’s design is quite different from that of a traditional microprocessor or a digital signal processor (DSP). Instead of sequential programming using high-level languages, such as C/C++, FPGA controller implementation requires a hardware description language (HDL) such as Verilog and VHDL, which requires extensive verification and optimization during the design process. This paper proposes a systematic FPGA design methodology with optimum resource utilization for rapid prototyping of high-performance power electronics applications to facilitate the widespread adoption of FPGA technology in power electronics. The FPGA controller design is concurrent with the power stage and utilizes high-level synthesis (HLS) tools and Simulink code generation toolbox. This paper covers the detailed design, implementation, and experimental validation of two specific applications, i.e., an active power filter (APF) and a motor emulator (ME), demonstrating the generalized features of the methodology. Employing fundamentally different control structures, both application examples achieve ultra-high current control bandwidth leveraging SiC MOSFETs switching at no less than 100 kHz.

Design and verification of multiple SEU mitigated circuits on SRAM-based FPGA system

This paper addresses the issue of soft error mitigation for Static Random-Access Memory (SRAM)-based Field Programmable Gate Arrays (FPGAs) system in radiation environment to reduce their malfunction and system failure rates in space missions. Seven representative circuits are designed by using the logical resources of SRAM-based FPGA. The accelerator tests investigate that the clock distribution of the Triple Modular Redundancy (TMR) circuits is vital to achieve a high Single Event Upset (SEU) tolerance. The separated DTMR_NEW circuits are proposed to overcome the weakness of the conventional TMR circuits, and a 25× improvement of SEU tolerance for the separated DTMR_NEW circuits are verified. The statistical estimations are desirable for engineers to assess and enhance the SEU tolerance of their designed systems at earlier stages to reduce the time and development costs.

Accessing register spaces in FPGAs within the ATLAS DAQ scheme via the SCA eXtension

The foreseen upgrades of the Large Hadron Collider (LHC) are expected to increase the required throughput of the front-end and back-end electronics that support the readout of the LHC detectors. Therefore, the complexity of the electronics systems will be increased as well. An example of this is the electronics system of the New Small Wheel (NSW) upgrade of the ATLAS detector, which will be comprised of a number of Field-Programmable Gate Arrays (FPGAs), and Application-Specific Integrated Circuits (ASICs). These ASICs will be configured and monitored by the Slow Control Adapter (SCA), another ASIC designed for this purpose. The Slow Control Adapter eXtension (SCAX) on the other hand, is an FPGA module designed to support FPGA systems that are part of the ATLAS electronics scheme by reading and writing their configuration parameters and status indicators. SCAX emulates both the I2C interface of the SCA used to access the NSW ASICs, as well as the communication protocol implemented between the SCA and the back-end infrastructure. It thereby enables using the same OPC-UA server and back-end software suite that support the ASICs, to also interface with the FPGAs that are part of the same system. This work describes the context of the SCAX's implementation, alongside architectural considerations of the module, features, and techniques to validate its hardware implementation across a variety of FPGA devices.

RETRACTED: Energy-saving design of civil engineering buildings based on FPGA and embedded system

Civil engineers design, construct, operate, and manage public roads, buildings, airports, tunnels, dams, bridges, water supply and sewage treatment systems engineering construction, and maintenance, including the private sectors. The energy civil engineering building design is one of the most catalysts for wealth creation, economic growth, and social change in all countries. Buildings have a significant share of the total energy consumption worldwide; therefore, they profoundly impact the environment (Selects the construction area of these stages, architectural design , architecture and material selection, Construction, maintenance, disassembly, reuse, recycling, and waste disposal). The power building's life cycle has been used at all stages based on Field Programmable Gate Array (FPGA) and Embedded system. Embedded system is a civil design engineering that is often optimal for maximum compute output, no timelines, or business drivers. Energy consumption in buildings can be significantly reduced at every stage of the building lifecycle. The energy-saving method of construction lifecycle. Information about the building's life cycle, energy-saving, and explains the guiding principles in civil engineering buildings' life cycle design.

RETRACTED: Campus football application based on FPGA system and GPS wearable electronic equipment

Campus football application is a Wearable innovation in sports area disassembling wearable innovation functionality for different clients and why there is such a need for these gadgets in everyday existence. It shows how persuasive the various sensors are in conveying an assortment of readings, which can help from many angles, in the existing method, deep learning and machine learning-based campus football application monitoring system. In this current system, data monitoring, data sharing are significantly less accurate in the football application monitoring system. So in the proposed system Global Positioning System (GPS) and FPGA (Field Programmable Gate Array) for Campus Football Application. Wearable sensors are expanding at work, and by coordinating innovations, clients are gathering more information about themselves. The scale of the wearable design is vast, each with its function to perform in different organizations. Sports wearable include an inertia rating unit and a Global Positioning System (GPS) sensor, which can be modified for various purposes. In this audit, differences show which sensors are feasible and lead to sensor innovation for sport applications. The sport requires constant emotional assessment. This is because the details observed by the sensors are physical. The Colony Optimization Algorithm presentation classifies a portion of the assessment capabilities. Separation can give clients a picture of their performance. The sensors measure the execution details and are done by data preparation, where the channels may vary on the actual information in terms of execution. Other reliability concerns are whether the continuous data input is as accurate as the post-game information.

RETRACTED: Remote classroom system for Chinese linguistics teaching based on FPGA and embedded system

Online intelligent remote classrooms subject to Chinese Linguistics and FPGA (Field-programmable gate array) procedures are used to handle complex blends of teaching and work estimations. FPGA (Field-Programmable Gate Array) is regularly realized as ASICs (Application-Specific Integrated Circuit) because of the high model thickness and execution essentials. Embedded designs regularly don't achieve high efficiency and low power application. The FPGA (Field-Programmable Gate Array) online course replication, appropriately giving the Fault Distributed Algorithm and hardware stage to organizing and evaluating new features before silicon is set into usage. Chinese Linguistics causes the network interface to grow faster and decline the ASIC design cycle. The Fault Distributed Algorithm is the improved forefront FPGA (Field-Programmable Gate Array) introduced another maximize card that reinforces the latest ASIC and FPGA plans that are a bit of checking trigger. The delivered output is taken care of in a model group and set aside in the data line that makes up an amount model pack. Considering the produced test set, the proposed system discovers each level's progression closeness, ultimately the overall likeness.

RETRACTED: Research on virtual simulation of basketball technology 3D animation based on FPGA and motion capture system

A stable structure and group information for measuring the driving dynamic binding character information processing, network control and operation when ready. Created with Unity, Tensol Stream and PyTorch. This method can be done bipedal and quadruped movement in the past occupied the complex and rational activity. The study will help researchers select the appropriate exercise programs and motion capture framework to test their gadgets. The rose to select and added to the open network arena, improve audit in their investigation. Framework has instructed sub conventional and highly accurate three-dimensional movement. Article screening to determine the motion capture framework research study of distributed source in one hundred academic studies used in the report of human activity. The proposed use of support to Field Programmable Gate array (FPGA) virtual computing innovation replay basketball to move the ball from the foundation and other projects, such as the distinction between players and referees. The two-dimensional position of the ball results are calibrated to identify the real position of the ball. Reality from the position of the ball, shoot the scene from every angle camera, and further ground plane. True development continue to see the ball from the top. Tests showed that the proposed calculation obstacles can be handled quickly and less difficult ball, the ball slightly different size and shape.

RETRACTED: Simulation of heat transfer process of thermal protective clothing based on FPGA and sensor processing system

Abstract Low radiation exposure to the heat transfer of the heat flux protective clothing. Field Programmable Gate Arrays (FPGA) simulation software and the sensor are used to model the heat transfer through a particular multilayer textile structure. The transfer model is verified by comparison with experimental data. In the previous method, is Initial results with the corresponding experimental results are very consistent. The first of a series of tasks to optimize thermal performance for protective clothing in thermal comfort. It protects the skin from exposure to low-intensity aspects of thermal damage caused by heat radiation has the best performance. Exposed to heat and flame, the clothes will burn. However, these burns' nature depends mostly on the fabric, the fabric structure, garment moisture, and the heart of the finishing agent used. The proposed method improves combustion speed will not change wool than other natural fibers (e.g., cotton, linen, and silk) faster. Gas weaved or loosely woven fabric relatively intact motion of light, tight and more massive than the fabric structure to promote faster flame propagation of these materials.

RETRACTED: Animal tumor medical image analysis based on image processing techniques and embedded system

Abstract In terms of image segmentation and classification has been a lot of effort. To this end, various techniques have been employed. Image segmentation has great value, especially in the field of bio-medicine for disease diagnosis. Field Programmable Gate Arrays (FPGA) and embedded systems play a very important role in medical imaging tumors in animal studies neuroscience research. Embodiment's variety of techniques can improve the accuracy of the results of the composition. In this context, efforts to increase the diagnosis's accuracy made lists of previous studies and researchers in various targets. This study aims to propose a model for the FPGA and embedded systems to assess grayscale images' impact. Such a combination may provide better results and contribute to a more effective disease diagnosis in the shortest possible time. By introducing a more accurate and more efficient diagnosis of cancer models, the study contributed to image processing. According to this model, the present research includes other tasks: Classification and overview of a combination with other methods described. Recommendations for using segmentation techniques gradation FPGA and embedded system model. Improve diagnosis of animal tumor medical tumor for timely and effective treatment.