Field Programmable Gate Arrays Configuration Research Articles

A Hierarchical Priority Based Multi-Bit Error Tolerant Design for FPGA Configuration Memory

The reconfigurability of a field-programmable gate array (FPGA), which is utilized in many applications, permits changes to be made to an existing design. In hostile environments such as space, where radiation and ionizing particles increase the risk for failure and human maintenance is either impossible or time-consuming, this reconfigurable capability becomes even more important. Single event upsets (SEUs) and multi-bit upsets (MBUs) on configuration memory can cause soft errors and circuit malfunctions in SRAM-based field programmable gate arrays (FPGAs). The ever-increasing quantity of configuration bits in contemporary FPGAs makes it more difficult for traditional scrubbing to identify faults in a timely manner, leading to a mismatch between scrubbing performance and MBU sensitivity.A hierarchical multi-bit error correcting method fully utilizes the MBU sensitivity at various configuration frame locations. It employs distinct techniques for varying priorities and differentiates across configuration frames with multiple priorities. They divided code words into several sections and used distinct error-correction techniques in each section. In high radiation conditions, the suggested integrated error correction technique enhances FPGA configuration memory protection by substituting memory scrubbing. The suggested approach lowers total TTD and enables priority-based asynchronous MBU detection and correction. Index Terms—FPGA,MBU,Sensitivity,Configuration memory

Proton irradiation of FPGA-embedded hadron fluence sensors

Hadron fluence monitors based on static random access memories (SRAMs) are in use at particle accelerators for the protection of electronics and at proton-therapy facilities for measuring secondary neutrons. One shortcoming of current solutions is that they necessitate SRAMs to detect radiation-induced single event upsets and require additional components to transfer the counts from the radiation area. This approach limits the practicality of the sensors due to their power requirements, increased board complexity, larger physical footprint and reduced total ionizing dose tolerance. In this work, we present proton irradiation test results of a novel proton and neutron fluence sensor we designed. The sensor is fully embedded in a SRAM-based field programmable gate array (FPGA) solving the abovementioned limitations of the state of the art. The FPGA configuration SRAM is used as a sensitive element, while the Joint Test Action Group interface is leveraged as a read out circuitry. We irradiated six sensor units by means of a variable-energy proton beam at the Trento Institute for Fundamental Physics and Applications (TIFPA, Trento, Italy). We discuss our results in terms of proton to upset cross section as a function of the proton energy in the range from 70 to 228 MeV, also parameterized with respect to the power supply voltage. We evaluate the variability of the cross section in the set of irradiated samples. Moreover, we show how we used the device to image the proton beam and measure beam profiles for aligning the configuration RAM and beam centers. We also suggest alternate reading modes to measure the fluence on the device by measuring the drawn current, rather than counting upsets.

Application of double-error correction codes to protect configuration programmable logic memory against space radiation

Objectives. Programmable logic integrated circuits of the field programmable gate array (FPGA) type based on static configuration memory are widely used in the electronics of onboard spacecraft systems. Under the influence of space radiation, errors may occur in the FPGA configuration memory. The main methods of protection against such errors involve various options for reservation triggers, as well as the use of error-correcting codes in special error detection and correction circuits. The purpose of the present work is to determine which error-correcting codes are best suited to the implementation of internal scrubbing of the FPGA configuration memory taking redundancy into account.Methods. The paper analyses various methods for scrubbing FPGA configuration memory, which are used to correct errors caused by the action of space radiation. It is proposed to increase the efficiency of internal scrubbing of the FPGA configuration memory using codes that correct both single- and double-adjacent SEC-DED-DAEC errors. In this case, the need to perform external scrubbing of the configuration memory is reduced by overwriting it with a reference configuration from non-volatile radiation-resistant memory; in this way, FPGA downtime caused by the external scrubbing procedure is reduced. Due to the known SEC-DED-DAEC codes having a non-zero probability of erroneous detection and subsequent erroneous correction of a double non-adjacent error, as well as various redundancy and implementation complexities, a study was made of the most efficient code for internal scrubbing.Results. The results showed that the Datta, Neale and Hoyoon–Yongsurk codes are optimal from the indicated positions. Recommendations are given for selecting a specific code depending on the specific requirements for a particular planned space mission.Conclusions. The study confirms the effectiveness of protecting the memory of programmable logic by using two-error-correcting codes.

ACCELERATION OF BOOLEAN GENE REGULATORY NETWORKS ANALYSIS USING FPGA

Gene expression does not occur arbitrarily and spontaneously, it obeys certain patterns that can be expressed as a connected graph or network. The disclosure of these patterns requires a large amount of experimental research and accumulation of necessary statistical information. Then this information is subjected to mathematical processing, which involves significant computing resources and takes a lot of time. Boolean networks are often used as the basis for building mathematical models in those calculations. Recently, models based on Boolean networks have increasingly grown in size and complexity causing increased demands on traditional software solutions and computing tools. Field-programmable gate arrays (FPGAs) are a powerful and reconfigurable platform for implementing efficient and high-performance computing. The use of FPGA will significantly speed up the process of calculating sequential chains of gene states, both through the use of hardware acceleration in the calculation of logical dependencies, and through the implementation of an array of parallel computing cores, each of which can perform its own individual task. Another solution that can significantly simplify the work of researchers of gene regulation networks is the creation of a universal computing architecture that will allow dynamic reconfiguration of its internal structure when the task or logical dependencies for the current Boolean network change. Such a solution will relieve the researcher of the need to perform the entire set of actions for the technological preparation of a new FPGA configuration, from making changes to the HDL code that describes the network to uploading the updated configuration to the hardware accelerator. The article discusses how to use FPGA for the implementation and modeling of arbitrary Boolean networks, describes the concept of a universal reconfigurable architecture of a logical dependency calculating core for an arbitrary Boolean network and proposes a practical implementation of such a calculating core for modeling gene regulation networks.

Application of the Universal Quench Detection System to the Protection of the High-Luminosity LHC Magnets at CERN

The Universal Quench Detection System (UQDS) has been primarily developed to detect quenches in various superconducting magnets of LHC’s High Luminosity upgrade (HL-LHC). The functionality of the system, which comprises insulated high-resolution digitizing front-end channels and a central processing element, is mainly defined by the configuration of the central FPGA (Field Programmable Gate Array). Additional elements such as redundant power supplies, configurable interlocking capabilities and a communications controller are completing the functionality of the system. The system’s architecture is designed to be flexible enough to detect quenches in all superconducting elements of HL-LHC. The application-specific digital signal processing and quench detection algorithms are implemented in the firmware of the FPGA and thus can be changed according to the required specifications. To facilitate this process, the firmware has been structured accordingly and automated code generation techniques are used. The strategy of testing prototypes of the quench detection system with prototypes of the magnets allows an early evaluation of the system, minimizing operational issues in the final installation. This strategy has been already applied at CERN to the 11 T dipole magnets in previous years and extended as well to other magnet families of the HL-LHC Project. We give a system description and focus on the specific configurations for three different magnet families. Prototypes of these magnets have been recently tested at CERN. For each of these, specific features and detection methods have been developed, implemented and evaluated during the magnet tests.

Low-Cost Strategy to Detect Faults Affecting Scrubbers in SRAM-Based FPGAs

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to SEUs. For applications demanding high reliability this problem is often solved by integrating in the system a scrubber, a circuit that periodically scans the FPGA configuration memory and reconfigures it if an error is detected. Since the scrubber is usually implemented in the same FPGA device, it is also vulnerable to SEUs, thus the scrubber reliability is increased by adopting standard fault tolerance techniques. These solutions guarantee the scrubber reliability, but generally require a large area overhead.In this paper, we present a novel low-cost strategy capable to detect faults in the FPGA configuration memory implementing the scrubber. The proposed technique is based on time redundancy, forcing the scrubber output to produce an error indication for each word read from the FPGA memory, in order to detect the faults affecting the portion of FPGA memory implementing the scrubber. The implementation of our proposed strategy presents a negligible impact in terms of area overhead (4.17%) and a limited increase in power consumption (22.9%) over the original (unprotected) scrubber. As for the impact on system performance introduced by our strategy, it is of approximately the 38.2% over the unprotected scrubber, but it can be significantly lowered by reducing the frequency at which the scrubber is applied to test the FPGA.

100 Gb/s dynamically programmable SDN-enabled hardware encryptor for optical networks

We have successfully demonstrated an on-demand programmable hardware encryptor for optical networks enabled by the software-defined network (SDN) and tested its application in a quantum key distribution (QKD) use case. We believe our proposed encryptor is unique in the way that it combines on-demand programmable encryption algorithms with a 100G Ethernet network interface to provide a high-transmission capacity with flexible security. We have successfully formed an on-demand encryption library consisting of AES-256, AES-192, AES-128, Camellia-256, XOR, and no-encryption configurations. Our system has shown a network throughput of 91.3 Gb/s for AES variations and 90.2 Gb/s for Camellia-256, while theoretical encryption throughputs were 160 Gb/s. In addition, the goodputs of all the encryption schemes were measured as at least 90.4 Gb/s. For a faster reconfiguration of the field-programmable gate array (FPGA), partial reconfiguration technology has been used, and reconfiguration times of 2.6 s for encryption and 2 s for decryption have been achieved. The FPGA configuration rate was 3.35 MB/s. When our proposed design was tested in a QKD use case with 256-bit keys, the highest achieved key consumption rate was 27 keys/s, which corresponded to the minimum granularity of 474 MB per key. Thus, with a 256-bit key, up to a 6912 b/s key consumption rate was achieved. In addition, the encryptor’s end-to-end network latency has been tested using 300k standard Internet Control Message Protocol (ICMP) pings. For all encryption schemes, the latency was measured as 0.093 m s ± 0.028 m s on average, but the encryption/decryption processes did not have a meaningful latency impact with microsecond precision.

A Decoder – Look up Tables for FPGAs

The FPGA (Field-Programmable Gate Array) has recently become the popular hardware and so-called LUTs (Look up Tables) are the basic of the FPGAs logic. For example, n-LUT is the MOS pass transistors multiplexer 2n-1 which input data receive SRAM cells logic function configuration (user’s projects Truth Table). Address inputs of the LUT are the variables. Therefore, we get one n-arguments logic function for the actual FPGA configuration. To get m functions (even with the same n-arguments) we should take m LUT. Authors propose a novel Decoder n-LUT (n-DC LUT), which makes possible to get m functions with the same n-arguments, like in Program Logic Array (PLA) CPLD (Complex Programmable Logic Device). DC LUT activates one of the 2n product terms outputs. Combined with OR product terms we can get m functions with the same n-arguments. To do this option we can use, for example, FPGAs typical connections units. The restriction of Meade-Conway for the FPGAs allows n=3 in one tree. Two 3-LUTs with one 1-LUTs form 4-LUT. Modern Adaptive Logic Modules (ALM) have n=8, but not all possible functions are implemented. The article deals with the design and investigation of some variants 3-DC LUT: with pull up output resistors, with orthogonal output circuits, with orthogonal transistors for each pass transistor. Simulation confirms the feasibility of the proposed method and shows that DC LUT with orthogonal output circuits is better variant of the systems realization in terms of current consumption and time delay at large n. A further development of the ALM concept may be the introduction of adaptive DC LUT, which, by tuning, can calculate single LUT function or 2n decoder functions. The proposed elements allow to increase the functionality of the FPGAs.

FPGA Implementation of an NCO Based CDR for the JUNO Front-End Electronics

This article describes a design of an field-programmable gate array (FPGA) implementation of a clock and data recovery (CDR) system. The core will be integrated in the FPGA configuration for the front-end electronics (FEE) board of the Jiangmen underground neutrino observatory (JUNO) experiment. The front-end will be placed on the main detector, underground and underwater, making the electronics not accessible after installation. The timing and trigger system relies on a synchronous link connection over CAT5e cable (up to 100 m long) between the front-end and the back-end electronics (BEE), where a twisted-pair is dedicated to clock-forwarding. The robustness of the recovery clock system is essential for the stability of the FPGA firmware. The proposed project is intended to improve the clock recovery operation by increasing the immunity of the link to sudden electromagnetic interference (EMI). On top of this, the core allows to free a twisted-pair in the link, since the clock can be recovered from the data and there is no more need for a clock-dedicated transmission. This will optimize the link granting the possibility to implement other features. The design is based on two components: a numerically-controlled oscillator (NCO), in order to create a controlled frequency clock signal, and a digital phase detector (PD) to match the clock frequency with the data rate. NCOs are often coupled with a digital-to-analog converter (DAC) to create direct digital synthesizers (DDSs), which are able to produce analog waveforms of any desired frequency. In the presented case instead, the NCO generates a digital clock signal of an arbitrary frequency, while the PD manages this frequency by intercepting any shifting on the relative phase between the clock and the data. A phase aligner (PA) module guarantees that data are sampled in the middle of the eye pattern, which represents the optimal sampling point. The article presents an overview of the NCO-based CDR design and implementation, together with some tests and results in order to verify the CDR reliability. Moreover, in the last section, some other possible applications of the core are illustrated.

A Task-Schedulable Nonvolatile Spintronic Field-Programmable Gate Array

Despite the vast hardware resources available in field-programmable gate arrays (FPGAs), the implementation of very large and complex designs on these platforms is a challenging problem. One effective solution is to use task scheduling. In this method, the FPGA configuration is changed according to the required task. This requires access to external nonvolatile memory, which significantly reduces system performance. In this letter, the development of a nonvolatile spintronic FPGA structure with task-scheduling capability is described. By using the nonvolatile feature of the magnetic tunnel junction device, the structure can store two different configurations in a nonvolatile way, which eliminates the need for external memory access and significantly enhances system performance.

Trust in FPGA-accelerated Cloud Computing

Platforms combining Central Processing Systems (CPUs) with Field Programmable Gate Arrays (FPGAs) have become popular, as they promise high performance with energy efficiency. This is the result of the combination of FPGA accelerators tuned to the application, with the CPU providing the programming flexibility. Unfortunately, the security of these new platforms has received little attention: The classic software security assumption that hardware is immutable no longer holds. It is expected that attack surfaces will expand and threats will evolve, hence the trust models, and security solutions should be prepared. The attacker model should be enhanced and consider the following three basic entities as the source of threats: applications run by users, accelerators designed by third-party developers, and the cloud service providers enabling the computation on their platforms. In our work, we review current trust models and existing security assumptions and point out their shortcomings. We survey existing research that target secure remote FPGA configuration, the protection of intellectual property, and secure shared use of FPGAs. When combined, these are the foundations to build a solution for secure use of FPGAs in the cloud. In addition to analysing the existing research, we provide discussions on how to improve it and disclose various concerns that have not been addressed yet.

A Radiation-Tolerant, Multigigabit Serial Link Based on FPGAs

Multigigabit serial links implemented by means of static random access memory (SRAM)-based field-programmable gate arrays (FPGAs) are extensively used in trigger and data acquisition systems of high-energy physics experiments. Their usage is mostly in areas without radiation, due to the sensitivity of FPGA configuration memory to single-event upsets. In order to use these links in radiation environments, some mitigation techniques can be used. In this article, we present a bidirectional link running at 6.25 Gbps implemented in Xilinx Kintex-7 FPGAs. Transferred data are protected against radiation effects by means of a Reed-Solomon (RS) code and symbol interleaving. Logic features triple modular redundancy in critical blocks. The design includes a custom scrubber based on majority voting of configuration frames. Our custom protocol can vary the protection level of the RS code to cope with different rates of radiation-induced transmission errors, trading off the available bandwidth for reliability. We present the test results carried out using fault injection and a 62-MeV proton beam at the Istituto Nazionale di Fisica Nucleare (INFN) Laboratori Nazionali del Sud (Catania, Italy). We show the performance of the link in terms of mean time between failures and mean time between losses of lock.

Development of a Real-Time Force and Temperature Sensing System with MEMS-LSI Integrated Tactile Sensors for Next-Generation Robots

This study proposes a sensing system that can sense force and temperature at the same time. The system consists of MEMS-LSI integrated tactile sensor devices called sensor nodes, a field-programmable gate array (FPGA) based relay node, and a host PC. For real-time temperature and force data acquisition, a time-sharing force and temperature task processing mechanism was implemented with a dedicated computer architecture in the FPGA configuration and the host program. This study firstly reports the temperature dependency analysis of a capacitive sensor readout circuit in the sensor node by circuit-level simulation. With a fabricated sensor node, sensor output data were measured and analyzed with varying temperatures and applied force. Based on the measured data, linear multiple regression equations for temperature compensation of sensed force data were developed. In the temperature range of 24.8°C–60°C, the average/maximum force errors when considering the temperature effect were −0.98%/65% without the compensation, and 0.072%/17% with the compensation, respectively. One cycle time of temperature and force sensing for one sensor node was 113 ms on average. The experimental results showed that real-time temperature and force sensing and temperature compensation for accurate force sensing could be achieved successfully. The study also demonstrated the system with hot-coffee cup and finger touch examples.

Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based Reconfigurable Designs

This article presents an approach to providing fault tolerance to permanent effects in the substrate of dynamic, partially reconfigurable field-programmable gate arrays (FPGAs). Our proposal consists of modifying FPGA configuration at runtime to avoid permanently damaged regions of the FPGA. It demands that the circuit design fulfills several requirements regarding the functionality and interfaces of its reconfigurable modules, the structure of the communications, the inclusion of specialized modules to handle and optimize circuit reconfiguration at runtime, and the organization of the reconfigurable partitions. We evaluate two methods to select the new target partition for modules in faulty partitions and design their hardware as intellectual property modules. We evaluate the performance and scalability of this approach using a trapezoidal shaper, a filter used to detect high-energy particles in radiation experiments, and we carry out the experiments with a variable number of modules and reconfigurable partitions using the two selection algorithms. The proposal is compared with nonfault-tolerant and triple modular redundancy approaches, and it remains functional with up to $12\times $ more injected faults than those.

Understanding the Impact of Quantization, Accuracy, and Radiation on the Reliability of Convolutional Neural Networks on FPGAs

Convolutional neural networks are quickly becoming viable solutions for self-driving vehicles, military, and aerospace applications. At the same time, due to their high level of design flexibility, reprogrammable capability, low power consumption, and relatively low cost, the field-programmable gate arrays (FPGAs) are very good candidates to implement the neural networks. Unfortunately, the radiation-induced errors are known to be an issue in static random-access memory (SRAM)-based FPGAs. More specifically, we have seen that particles can change the content of the FPGA's configuration memory, consequently corrupting the implemented circuit and generating the observable errors at the output. Through extensive fault injection, we determine the reliability impact of applying binary quantization to the convolutional layers of neural networks on FPGAs, by analyzing the relationships between model accuracy, resource utilization, performance, error criticality, and radiation cross section. We were able to find that a design with quantized convolutional layers can be 39% less sensitive to radiation, whereas the portion of errors that are considered critical (misclassifications) in the network is increased by 12%. Moreover, we also derive generic equations that consider both accuracy and radiation in order to model the overall failure rate of neural networks.

Tunable FPGA Bitstream Obfuscation with Boolean Satisfiability Attack Countermeasure

Field Programmable Gate Arrays (FPGAs) are seeing a surge in usage in many emerging application domains, where the in-field reconfigurability is an attractive characteristic for diverse applications with dynamic design requirements, such as cloud computing, automotive, IoT, and aerospace. The security of the FPGA configuration file, or bitstream , is critical, especially for devices with long in-field lifetimes, where attackers may attempt to extract valuable Intellectual Property (IP) from within. In this article, we propose a tunable obfuscation approach that protects IP from typical bitstream attacks while enabling designers to trade off security with acceptable overhead. We also consider two potential attacks on this protection mechanism: Boolean SAT Attacks on the obfuscation and removal attacks on the protection circuitry. The obfuscation and SAT countermeasure are integrated in a custom CAD framework within a commercial FPGA toolflow and together provide mathematically strong protection against common bitstream attacks. Further, we quantify the difficulty of a removal attack on the protection circuitry through pattern matching and direct bitstream manipulation. The average area, power, and delay overhead for obfuscation with 95% mismatch probability are 18%, 16%, and 8%, respectively, for small combinational circuits, and 1%, 2%, and 5% for larger arithmetic modules.

TECHNIQUE OF C PROGRAM TRANSLATION FOR RECONFIGURABLE AND HYBRID COMPUTER SYSTEMS BASED ON FIELD-PROGRAMMABLE GATE ARRAYS

In this paper, we thoroughly consider the technique of conversion of procedural programs in C to configuration files for field-programmable gate arrays used in the toolkit for programming of reconfigurable and hybrid computer systems. The creation of parallel program in the COLAMO (Common Oriented Language for Architecture of Multi Objects) language using the analysis results of information dependences in the initial procedural program and its further conversion to a parallel and pipeline form are the distinctive characteristics of the technique. We addressed the methods of scalar splitting and array extension by iterations, which are applied for the fulfillment of the single assignment and unique substitution rules in parallel program and the saving of information communications of the initial procedural program. The technique of conversion of automatically created parallel program to the scalable parallel and pipeline form is presented. The “Procrustes” preprocessor adapts the form for different architectures and configurations of reconfigurable and hybrid computer systems. Owing to the described methodology, it is possible to synthesize a resource-independent scalable COLAMO-application, which can adapt to available computational resource by changing of several constants in automatic mode without any considerable modification of the program source code. Then, the scalable COLAMO-applicationis translated by the COLAMO-translator into field-programmable gate arrays configuration files for the specified reconfigurable computer resource.

Thwarting Security Threats From Malicious FPGA Tools With Novel FPGA-Oriented Moving Target Defense

The increasing usage and popularity of the field-programmable gate array (FPGA) systems bring in security concerns. Existing countermeasures are mostly based on the assumption that the computer-aided design (CAD) tools for FPGA configuration are trusted. Unfortunately, this assumption does not always hold. In this paper, we investigate the potential security threats originated from the untrusted CAD tools. Furthermore, we exploit the principle of moving target defense (MTD) to propose an FPGA-oriented MTD (FOMTD) method. The three defense lines in the FOMTD generate uncertainties, from the attacker’s point of view, to thwart hardware Trojan insertion attacks. The theoretical upper bound of the hardware Trojan hit rate for each defense line is provided in this paper. Experimental results show that the proposed defense line 2 and defense line 3 reduce the Trojan hit rate by up to 40% and 91%, respectively, for the scenario where the malicious CAD tool can insert Trojans in the occupied FPGA slices. The proposed gate replacement technique in the defense line 3 further improves the attack resilience and obtains 88% reduction on the Trojan hit rate. Compared to the static redundancy-based Trojan detection method, the proposed method achieves better resilience against Trojan insertions and consumes 50% less dynamic power.

Solving the Problems of Routing Interconnects with a Resynthesis for Reconfigurable Systems on a Chip

The existing means of design automation are focused mainly on the technology of foreign manufacturers, which makes it necessary to adapt the existing methods and means for designing reconfigurable systems-on-a-chip and to develop domestic specialized CAD tools to solve urgent problems in this field. Methods are proposed for solving interconnection routing problems in conjunction with logical resynthesis, applied to the architecture of a reconfigurable system-on-a-chip based on the domestic field-programmable gate array (FPGA) of the Almaz-14 family. Developers from JSC “NIIME” and PJSC “Micron” laid broad configurational solutions, which do not have foreign analogues, into this crystal. A wide range of additional elements for the configuration, as well as the potentialities for the logical resynthesis of the FPGA Almaz-14 chip, have led to the need to develop new methods for routing interconnections that would allow us to take into account and use these architectural features. An efficient algorithm for the automatic routing of interconnections for a reconfigurable system on a chip based on FPGAs belonging to the Almaz-14 family based on algorithm A* is developed. This algorithm represents a modification of the classical algorithm searching for the shortest path on a graph, the Dijkstra algorithm, including a mixed switching graph model. To describe the variety of additional switching elements, a special generalized mathematical model, as well as a special interface in the command language Tcl are developed, the latter includes a list of elements for configuration, as well as their description and functional purpose. This work has increased the efficiency of computer-aided design using programmed mechanisms developed and implemented in the C programming language for the optimal use of the configuration and routing elements of FPGAs, as well as mechanisms for the complete and entire routing of interconnections.

An Autonomous, Self-Authenticating, and Self-Contained Secure Boot Process for Field-Programmable Gate Arrays

Secure booting within a field-programmable gate array (FPGA) environment is traditionally implemented using hardwired embedded cryptographic primitives and non-volatile memory (NVM)-based keys, whereby an encrypted bitstream is decrypted as it is loaded from an external storage medium, e.g., Flash memory. A novel technique is proposed in this paper that self-authenticates an unencrypted FPGA configuration bitstream loaded into the FPGA during the start-up. The internal configuration access port (ICAP) interface is accessed to read out configuration information of the unencrypted bitstream, which is then used as input to a secure hash function SHA-3 to generate a digest. In contrast to conventional authentication, where the digest is computed and compared with a second pre-computed value, we use the digest as a challenge to a hardware-embedded delay physical unclonable function (PUF) called HELP. The delays of the paths sensitized by the challenges are used to generate a decryption key using the HELP algorithm. The decryption key is used in the second stage of the boot process to decrypt the operating system (OS) and applications. It follows that any type of malicious tampering with the unencrypted bitstream changes the challenges and the corresponding decryption key, resulting in key regeneration failure. A ring oscillator is used as a clock to make the process autonomous (and unstoppable), and a novel on-chip time-to-digital-converter is used to measure path delays, making the proposed boot process completely self-contained, i.e., implemented entirely within the re-configurable fabric and without utilizing any vendor-specific FPGA features.