Application Of Field Programmable Gate Array Research Articles

A FPGA-based rapid prototyping approach for teaching of Mechatronics Engineering

The degree of Mechatronics Engineering was first introduced in 2002 at the University of Auckland by the Department of Mechanical Engineering. Teaching such a degree requires an integrated approach to topics such as applied mechatronics, mechanical design, control and software engineering. The use of field programmable gate array (FPGA) with associated software enables students to learn various digital design techniques, simulate and quickly implement them into the design of mechatronics systems. This paper presents a FPGA-based rapid prototyping platform for teaching applied electronics, hardware description languages and motor control concepts. The platform is based on Altera’s University Program UP2 Development Kit. The approach used in the application of FPGA is to accurately reflect current practice in industry rather than the more traditional TTL or CMOS chips and breadboard based approach to quickly prototype a digital system.

Bio-inspired optic flow sensors based on FPGA: Application to Micro-Air-Vehicles

Tomorrow’s Micro-Air-Vehicles (MAVs) could be used as scouts in many civil and military missions without any risk to human life. MAVs have to be equipped with sensors of several kinds for stabilization and guidance purposes. Many recent findings have shown, for example, that complex tasks such as 3-D navigation can be performed by insects using optic flow (OF) sensors although insects’ eyes have a rather poor spatial resolution. At our Laboratory, we have been performing electrophysiological, micro-optical, neuroanatomical and behavioral studies for several decades on the housefly’s visual system, with a view to understanding the neural principles underlying OF detection and establishing how OF sensors might contribute to performing basic navigational tasks. Based on these studies, we developed a functional model for an Elementary Motion Detector (EMD), which we first transcribed into electronic terms in 1986 and subsequently used onboard several terrestrial and aerial robots. Here we present a Field Programmable Gate Array (FPGA) implementation of an EMD array, which was designed for estimating the OF in various parts of the visual field of a MAV. FPGA technology is particularly suitable for applications of this kind, where a single Integrated Circuit (IC) can receive inputs from several photoreceptors of similar (or different) shapes and sizes located in various parts of the visual field. In addition, the remarkable characteristics of present-day FPGA applications (their high clock frequency, large number of system gates, embedded RAM blocks and Intellectual Property (IP) functions, small size, light weight, low cost, etc.) make for the flexible design of a multi-EMD visual system and its installation onboard MAVs with extremely low permissible avionic payloads.

Floating-Point Divider Design for FPGAs

Growth in floating-point applications for field-programmable gate arrays (FPGAs) has made it critical to optimize floating-point units for FPGA technology. The divider is of particular interest because the design space is large and divider usage in applications varies widely. Obtaining the right balance between clock speed, latency, throughput, and area in FPGAs can be challenging. The designs presented here cover a range of performance, throughput, and area constraints. On a Xilinx Virtex4-11 FPGA, the range includes 250-MHz IEEE compliant double precision divides that are fully pipelined to 187-MHz iterative cores. Similarly, area requirements range from 4100 slices down to a mere 334 slices

Practical VHDL optimization for timing critical FPGA applications

This paper gives a hands-on example of how low-level optimization of the VHSIC Hardware Description Language (VHDL) code is extremely difficult within a contemporary Field Programmable Gate Array (FPGA) design flow. However, low-level optimization can be accomplished, and by changing the VHDL coding style synthesis results can be improved. The design flow is considered from high-level descriptions (bubble diagrams), through logic synthesis to the point where hand optimization is required. For performance benchmarking a state machine from a contemporary computer bus, PCI, implemented in a Xilinx FPGA, is used. Practical design issues applied to time-critical implementations using FPGAs, especially the trade-offs of high-level versus low-level synthesis, are analyzed. Performance evaluation results of several PCI target state machines, coded using different styles and design methods are given in terms of time and area efficiency. Based on these findings improvements to the FPGA design methodology are proposed.

High performance antifuse with planar double dielectricson Si 1-x Ge x pad for field programmable gate array applications

A new antifuse device with a planar metal/dielectric/poly-Si/sub 1-x/Ge/sub x//dielectric/metal structure has been proposed for use in FPGAs as a voltage programmable link. The device has low leakage current (/spl sim/0.01 pA/antifuse) at an operating voltage of 5 V and low on-resistance (/spl sim/13-15 /spl Omega/) with a 1 ms long 12.5 V pulse.

Novel Amorphous-Silicon-Based Double-Metal Antifuse with Barrier Enhancement Layer

The electrical characteristics, operating mechanism and reliability of a novel amorphous-silicon-based double-metal antifuse are reported in detail. A very thin α-SiC:H layer was inserted on both top and bottom Al/α-Si:H interfaces as barrier enhancement layer. With proper adjustment of the thickness of this layer, the programming voltage and leakage current can be controlled. The antifuse offers very low on-resistance (<2 Ω) and low preparation temperature (<250° C), and the characteristics are independent of area, therefore, the device is suitable for integration with field-programmable gate array applications.