Type Of Field Programmable Gate Array Research Articles

Novel FPGA clock concept and dual-mode basic logic element

Typically, field programmable gate arrays (FPGAs) use a clock generator, which frequency is calculated based on the worst-case transient. Asynchronous circuits operate on real transient delays, but their design is much more complex. Self-timed (ST) circuits, proposed by D. Muller in the late 50s of the twentieth century, the asynchronous circuit subclass, have built-in means of the transition process completion acknowledging. Thanks to this property, ST circuits are characterized by a wide range of performance in terms of supply voltage and ambient temperature and ensure reliable operation at any logic cell delays determined by the current operating conditions. There are currently no commercially available self-timed FPGAs on the market. And numerous attempts to use traditional synchronous FPGAs and their design tools to create self-timed prototypes have not made it possible to fully realize their potential advantages. This article aims to improve the ST circuit FPGA-implementation efficiency. The Institute of Informatics Problems of the Federal Research Center "Computer Science and Control" of the Russian Academy of Sciences is the major center of competence in the self-timed direction in the Russian Federation. On the topic of joint scientific research with the Perm National Research Polytechnic University, a number of logical cells for ST-FPGA have been previously developed. Target. Formulation of the new FPGA type concept using the operating mode choice, clarification of the proposed logical element's structure and methods of its reconfiguration for a given operating mode, and features of cascading elements of this type for the construction of multi-bit logical elements. The concept of a new type of FPGA with increased flexibility and operating mode selection is proposed. It allows developers to select not only functions and connections, but also to build digital circuits cases with different operating modes using computer-aided design systems: both synchronous and self-timed, or a combination of both. The design of a dual-mode logic element and details of its reconfiguration, as well as scaling issues for bit capacity increase, are also clarified. The practical use of the proposed two-mode basic logic element increases the flexibility of digital equipment projects on FPGAs, which is especially important for critical application areas at the current stage of integrated technology development in the Russian Federation.

Reinforcement Learning-Driven Bit-Width Optimization for the High-Level Synthesis of Transformer Designs on Field-Programmable Gate Arrays

With the rapid development of deep-learning models, especially the widespread adoption of transformer architectures, the demand for efficient hardware accelerators with field-programmable gate arrays (FPGAs) has increased owing to their flexibility and performance advantages. Although high-level synthesis can shorten the hardware design cycle, determining the optimal bit-width for various transformer designs remains challenging. Therefore, this paper proposes a novel technique based on a predesigned transformer hardware architecture tailored for various types of FPGAs. The proposed method leverages a reinforcement learning-driven mechanism to automatically adapt and optimize bit-width settings based on user-provided transformer variants during inference on an FPGA, significantly alleviating the challenges related to bit-width optimization. The effect of bit-width settings on resource utilization and performance across different FPGA types was analyzed. The efficacy of the proposed method was demonstrated by optimizing the bit-width settings for users’ transformer-based model inferences on an FPGA. The use of the predesigned hardware architecture significantly enhanced the performance. Overall, the proposed method enables effective and optimized implementations of user-provided transformer-based models on an FPGA, paving the way for edge FPGA-based deep-learning accelerators while reducing the time and effort typically required in fine-tuning bit-width settings.

Hardware/Software Solution for Low Power Evaluation of Tsunami Danger

Carbon footprint reduction issues have been drawing more and more attention these days. Reducing the energy consumption is among the basic directions along this line. In the paper, a low-energy approach to tsunami danger evaluation is concerned. After several disaster tsunamis of the XXIst century, the question arises whether is it possible to evaluate in a couple of minutes the tsunami wave parameters, expected at the particular geo location. The point is that it takes around 20 min for the wave to approach the nearest coast after a seismic event offshore of Japan. Currently, the main tool for studying tsunamis is computer modeling. In particular, the expected tsunami height near the coastline, when a major underwater earthquake is detected, can be estimated by a series of numerical experiments of various scenarios of generation and the following wave propagation. Reducing the calculation time of such scenarios and the necessary energy consumption for this is the scope of this study. Moreover, in case of the major earthquake, the electric power shutdown is possible (e.g., the accident at the Fukushima nuclear power station in Japan on 11 May 2011), so the solution should be of low energy-consuming, preferably based at regular personal computers (PCs) or laptops. The way to achieve the requested performance of numerical modeling at the PC platform is a combination of efficient algorithms and their hardware acceleration. Following this strategy, a solution for the fast numerical simulation of tsunami wave propagation has been proposed. Most of tsunami researchers use the shallow-water approximation to simulate tsunami wave propagation at deep water areas. For software implementation, the MacCormack finite-difference scheme has been chosen, as it is suitable for pipelining. For hardware code acceleration, a special processor, that is, the calculator, has been designed at a field-programmable gate array (FPGA) platform. This combination was tested in terms of precision by comparison with the reference code and with the exact solutions (known for some special cases of the bottom profile). The achieved performance made it possible to calculate the wave propagation over a 1000 × 500 km water area in 1 min (the mesh size was compared to 250 m). It was nearly 300 times faster compared to that of a regular PC and 10 times faster compared to the use of a central processing unit (CPU). This result, being implemented into tsunami warning systems, will make it possible to reduce human casualties and economy losses for the so-called near-field tsunamis. The presented paper discussed the new aspect of such implementation, namely low energy consumption. The corresponding measurements for three platforms (PC and two types of FPGA) have been performed, and a comparison of the obtained results of energy consumption was given. As the numerical simulation of numerous tsunami propagation scenarios from different sources are needed for the purpose of coastal tsunami zoning, the integrated amount of the saving energy is expected to be really valuable. For the time being, tsunami researchers have not used the FPGA-based acceleration of computer code execution. Perhaps, the energy-saving aspect is able to promote the use of FPGAs in tsunami researches. The approach to designing special FPGA-based processors for the fast solution of various engineering problems using a PC could be extended to other areas, such as bioinformatics (motif search in DNA sequences and other algorithms of genome analysis and molecular dynamics) and seismic data processing (three-dimensional (3D) wave package decomposition, data compression, noise suppression, etc.).

The Impact of Terrestrial Radiation on FPGAs in Data Centers

Field programmable gate arrays (FPGAs) are used in large numbers in data centers around the world. They are used for cloud computing and computer networking. The most common type of FPGA used in data centers are re-programmable SRAM-based FPGAs. These devices offer potential performance and power consumption savings. A single device also carries a small susceptibility to radiation-induced soft errors, which can lead to unexpected behavior. This article examines the impact of terrestrial radiation on FPGAs in data centers. Results from artificial fault injection and accelerated radiation testing on several data-center-like FPGA applications are compared. A new fault injection scheme provides results that are more similar to radiation testing. Silent data corruption (SDC) is the most commonly observed failure mode followed by FPGA unavailable and host unresponsive. A hypothetical deployment of 100,000 FPGAs in Denver, Colorado, will experience upsets in configuration memory every half-hour on average and SDC failures every 0.5–11 days on average.

Analysis of Existing and Proposed 3-Bit and Multi-Bit Multiplier Algorithms for FIR Filters and Adaptive Channel Equalizers on FPGA

Different multiplication algorithms have different performance characteristics. Some are good at speed while others consume less area when implemented on hardware, like Field Programmable Gate Array (FPGA)-the advanced implementation technology for DSP systems. The eminent parallel and sequential multiplication algorithms include Shift and Add, Wallace Tree, Booth, and Array. The multiplier optimization attempts have also been reported in adders used for partial product addition. In this paper, analogous to conventional multipliers, two new multiplication algorithms implemented on FPGA are shown and compared with conventional algorithms as stand-alone and by using them in the implementation of FIR filters and adaptive channel equalizer using the LMS algorithm. The work is carried out on Spartan-6 FPG that may be extended for any type of FPGA. Results are compared in terms of resource utilization, power consumption, and maximum achieved frequency. The results show that for a small length of coefficients like 3-bit, the proposed algorithms work very well in terms of achieved frequency, consumed power, and even resource utilization. Whilst for the length greater than 3-bit, the Pipelined multiplier is much better in frequency than the proposed and conventional ones, and the Booth multiplier consumes fewer resources in terms of lookup tables.

Configurable Ring Oscillator PUF Using Hybrid Logic Gates

Physical unclonable function (PUF), a hardware that can extract the differences of the same implementations and provide unique secret keys without the utilization of non-volatile memory, is regarded as a promising security primitive in the near future. Ring Oscillator (RO) PUF is one of its easy silicon implementations, which exploits the frequency difference between a pair of structurally identical ring oscillators. However, a large number of ROs must be constructed if multiple stable output bits are required, which means unacceptable area overhead for lightweight applications. To solve this problem, configurable ROs using multiplexers and different delay units were proposed in previous papers. Unfortunately, most of them take advantage of the specific structure of a certain type of field-programmable gate arrays (FPGAs), thus not cost-saving for application-specific integrated circuit (ASIC). In this paper, we propose a configurable RO using only two hybrid logic gates in each stage for ASIC, which costs less area and power compared with previous proposals. Experiment on 50 FPGAs and one self-designed printed circuit board demonstrates satisfactory uniformity and uniqueness of this novel RO PUF. Furthermore, our proposal is proved to be reliable in a wide variety of environment conditions.

POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator

In this brief, a low resource utilization field-programmable gate array (FPGA)-based long short-term memory (LSTM) network architecture for accelerating the inference phase is presented. The architecture has low-power and high-speed features that are achieved through overlapping the timing of the operations and pipelining the datapath. Moreover, this architecture requires negligible internal memory size for storing the intermediate data leading to low resource utilization and simple routing, which provides lower interconnect delay (higher operating frequency). A designer may adjust the resource utilization (as well as the latency) of the proposed architecture readily at the register-transfer level (RTL) design by adjusting the amount of parallelization. This makes the process of mapping the architecture onto different types of FPGAs, subject to defined constraints, a simple one. The efficacy of the proposed architecture is assessed by implementing an LSTM network on different types of FPGAs. Compared with the recent works, the proposed architecture provides up to about $1.6\times $ , $43.6\times $ , $21.9\times $ , and $114.5\times $ improvements in frequency, power efficiency, GOP/s, and GOP/s/W, respectively. Finally, our proposed architecture operates at 17.64 GOP/s, which is $2.31\times $ faster than the best previously reported results.

Heterogeneous FPGA-Based Cost-Optimal Design for Timing-Constrained CNNs

Field programmable gate array (FPGA) has been one of the most popular platforms to implement convolutional neural networks (CNNs) due to its high performance and cost efficiency; however, limited by the on-chip resources, the existing single-FPGA architectures cannot fully exploit the parallelism in CNNs. In this paper, we explore heterogeneous FPGA-based designs to effectively leverage both task and data parallelism, such that the resultant system can achieve the minimum cost while satisfying timing constraints. In order to maximize the task parallelism, we investigate two critical problems: 1) buffer placement , where to place buffers to partition CNNs into pipeline stages and 2) task assignment , what type of FPGA to implement different CNN layers. We first formulate the system-level optimization problem with a mixed integer linear programming model. Then, we propose an efficient dynamic programming algorithm to obtain the optimal solutions. On top of that, we devise an efficient algorithm that exploits data parallelism within CNN layers to further improve cost efficiency. Evaluations on well-known CNNs demonstrate that the proposed techniques can obtain an average of 30.82% reduction in system cost under the same timing constraint, and an average of 1.5 times speedup in performance under the same cost budget, compared with the state-of-the-art techniques.

Optimization on fixed low latency implementation of the GBT core in FPGA

In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAs

With increasing scale of Field Programmable Gate Arrays (FPGAs), architecture of interconnect resources (IRs) in FPGA is becoming more and more complicated. IR testing plays an important role to guarantee correct functionality of FPGAs. Usually, architecture of Global IRs is regular, while architecture of Local IRs is more complicated compared to Global IRs. In the paper, a generic IR model revealing the connection relationships for both Global and Local IRs in Xilinx series FPGAs is studied. A routability-aware algorithm based on the generic IR model is also presented. Test configurations (TCs) can be automatically generated by the proposed algorithm. Thus, both Global and Local IRs can be tested with identical method. Further, the algorithm is generic and independent of type and size of FPGAs. The algorithm is evaluated in Virtex series FPGAs. Experimental results demonstrate that the routing algorithm is applicable to Virtex series FPGAs with higher IR coverage achieved.

Time-to-Digital Converter Using a Tuned-Delay Line Evaluated in 28-, 40-, and 45-nm FPGAs

This paper proposes a bin-width tuning method for a field-programmable gate array (FPGA)-based delay line for a time-to-digital converter (TDC). Changing the hit transitions and sampling patterns of the carry chain considering delays of the sum and carry-out bins can improve the bin-width uniformity and thus measurement precision. The proposed sampling method was evaluated and compared with the ordinary tapped-delay-line (TDL) method in three different types of FPGAs: Kintex-7, Virtex-6, and Spartan-6. The linearity, equivalent bin width, and measurement precision improved for all the evaluated FPGAs by adopting the proposed method. The measurement precision obtained using the simple TDL architecture is comparable with other complex TDC architectures. In addition, the proposed method improves bin-width uniformity and measurement precision while maintaining the advantages of TDL TDCs, that is, fast conversion rate and small resource usage. Furthermore, the enhanced linearity of the delay line can also improve other carry-chain-based FPGA-TDCs.

Practical feasibility evaluation and improvement of a pay-per-use licensing scheme for hardware IP cores in Xilinx FPGAs

In earlier published work, Maes et al. present a pay-per-use licensing scheme for hardware Intellectual Property (IP) cores. This scheme focuses on the use of IP cores on static random access memory-based field programmable gate arrays (FPGAs) and is mainly based on the partial reconfigurability property of this type of FPGA. Our work evaluates the practical feasibility of the scheme and the accompanying architecture. As already (partly) indicated by Maes et al., their solution introduces some security and usability issues. Therefore, we present improvements to the scheme and the architecture together with an additional method for decreasing the area overhead. The overall result is the first practical implementation of the pay-per-use licensing scheme occupying 841 slices on a Xilinx XC6S-LX45 FPGA. The small area overhead is mainly achieved by moving the storage of keys from slice flip-flops to configuration memory. Moreover, the implementation would not have been feasible with commercially available tools. We use an academic tool that allows nested partial reconfiguration and flexible IP core placement.

Digital Current Controller for a 1 MHz, 10 kW Three-Phase VIENNA Rectifier

Active three-phase rectifiers operated at switching frequencies of 500 kHz and above, in order to increase their power density, require high-speed current controllers. If these current controllers are implemented purely digitally, which is well established today for 20-200 kHz converter systems, then very high numerical data processing demands result. In this paper, two different types of field-programmable gate arrays (FPGAs) are evaluated for realizing high-speed converter current control. For the implementation of such controllers, not only the FPGA has to be considered but rather the entire signal chain. Two alternative A/D interfaces (including high-speed low-voltage differential signaling data transmission) that are able to handle data sampling rates up to 25 MSa/s are verified. Subsequently, a digital current controller is designed and it is shown how hardware multiplier blocks of modern FPGAs can be used advantageously. Furthermore, the FPGA implementation of high-resolution pulsewidth modulation providing symmetrical pulse patterns for high switching frequencies is described. Measurements taken from a 10 kW VIENNA rectifier laboratory prototype finally demonstrate the high performance of the proposed control concept and show that a low mains current total harmonic distortion of 1.4% can be achieved for such ultrahigh switching frequency converters.

Performance evaluation of multipliers in reconfigurable hardware

Hardware multiplier is a critical element in many computing intensive sub-systems that are implemented in Field Programmable Gate Arrays (FPGAs). In this study, performance comparison between several different types of array-based unsigned 8-bit multipliers (both combinational and pipelined) for two types of FPGAs (XC4005XLPC84-3C and XC3S1000FT256-4C Spartan 3) in terms of resource utilization and critical path delays was carried out. For combinational multipliers, the embedded multiplier in the high density Spartan 3 FPGA has the lowest critical path delay. MUX-based Carry Save Array (CSA) multiplier when implemented in the low density XC4005 FPGA, utilized 24% less resources and resulted is 42% improvement in the latency than the standard multiplier available in the hardware description language (VHDL) library. For pipelined multipliers, single stage pipelined multiplier of the same architecture, for the same chip, utilized 18% more resources but produced a 84% improvement in the latency. Thus, to obtain the optimum performance of FPGA hardware in high speed applications, MUX-based pipelined CSA multipliers are recommended. Keywords: FPGA, Multiplier hardware architecture, reconfigurable computing, VHDL doi:10.4038/jnsfsr.v36i3.160 Journal of the National Science Foundation of Sri Lanka 36 (3) 235-237

KGPMAP:library-based technology-mapping technique for antifuse based FPGAs

Owing to their high degree of flexibility and low design-turnaround time, field-programmable-gate-array (FPGA) based designs are becoming very popular. With the availability of different types of FPGA, the need of a unified approach for logic-block-independent technology mapping is being felt increasingly. The paper presents a new approach to efficient realisation of a given combinational function in terms of a prespecified k-input-single-output logic block. All subfunctions of 1 to k inputs realisable by the logic block are generated and kept in a library. The approach is general in the sense that it is not targeted to any specific FPGA built around a specified set of basic blocks. It uses a node-clustering technique for breaking up the given combinational function into subfunctions with special treatment for the fanout nodes. The scheme utilises a novel signature-based strategy to find a match for a subfunction in the library. One contribution is the elegant signature-generation scheme that can be applied for any library-based search problem. The signature is unique for functions of up to four variables and has an aliasing of around 0.5% for functions with larger number of variables. For comparison with other mapping techniques, the KGPMAP algorithm has been applied to several combinational benchmark circuits using Actel's act1-library. The result has been found to be superior to other well known library-based technology mappers and some Actel-specific mappers.