Programming Field Programmable Gate Arrays Research Articles

FEINT: Automated Framework for Efficient INsertion of Templates/Trojans into FPGAs

Field-Programmable Gate Arrays (FPGAs) play a significant and evolving role in various industries and applications in the current technological landscape. They are widely known for their flexibility, rapid prototyping, reconfigurability, and design development features. FPGA designs are often constructed as compositions of interconnected modules that implement the various features/functionalities required in an application. This work develops a novel tool FEINT, which facilitates this module composition process and automates the design-level modifications required when introducing new modules into an existing design. The proposed methodology is architected as a “template” insertion tool that operates based on a user-provided configuration script to introduce dynamic design features as plugins at different stages of the FPGA design process to facilitate rapid prototyping, composition-based design evolution, and system customization. FEINT can be useful in applications where designers need to tailor system behavior without requiring expert FPGA programming skills or significant manual effort. For example, FEINT can help insert defensive monitoring, adversarial Trojan, and plugin-based functionality enhancement features. FEINT is scalable, future-proof, and cross-platform without a dependence on vendor-specific file formats, thus ensuring compatibility with FPGA families and tool versions and being integrable with commercial tools. To assess FEINT’s effectiveness, our tests covered the injection of various types of templates/modules into FPGA designs. For example, in the Trojan insertion context, our tests consider diverse Trojan behaviors and triggers, including key leakage and denial of service Trojans. We evaluated FEINT’s applicability to complex designs by creating an FPGA design that features a MicroBlaze soft-core processor connected to an AES-accelerator via an AXI-bus interface. FEINT can successfully and efficiently insert various templates into this design at different FPGA design stages.

High-precision high-speed nanopore ping-pong control system based on field programmable gate array.

"Molecular ping-pong," emerging as a control strategy in solid-state nanopore technology, presents a highly promising approach for repetitive measurements of single biomolecules, such as DNA. This paper introduces a high-precision, high-speed nanopore molecular ping-pong control system consisting of a home-built trans-impedance amplifier (TIA), a control system based on a Field Programmable Gate Array (FPGA), and a LabVIEW program operating on the host personal computer. Through feedback compensation and post-stage boosting, the TIA achieves a high bandwidth of about 200kHz with a gain of 100 MΩ, along with low input-referred current noise of 1.6 × 10-4pA2/Hz at 1kHz and 1.1 × 10-3pA2/Hz at 100kHz. The FPGA-based control system demonstrates a minimum overall response time (tdelay) of 6.5 μs from the analog input current signal trigger to the subsequent reversal of the analog output drive voltage signal, with a control precision of 1 μs. Additionally, a LabVIEW program has been developed to facilitate rapid data exchange and communication with the FPGA program, enabling real-time signal monitoring, parameter adjustment, and data storage. Successful recapture of individual DNA molecules at various tdelay, resulting in an improvement in capture rate by up to 2 orders of magnitude, has been demonstrated. With unprecedented control precision and capture efficiency, this system provides robust technical support and opens novel research avenues for nanopore single-molecule sensing and manipulation.

A Domain-Specific Accelerator for Ultralow Latency Market Data Distribution System

Ultralow latency parsing of financial data is gaining significance in the high-frequency trading of the security exchange market. Hardware-aided systems exhibit superior improvement of latency over traditional software solutions, but flexibility may suffer when processing the financial protocol. This article presents a domain-specific accelerator for the market data distribution system, which integrates a financial information exchange adapted for streaming (FAST) decoder, a 10-Gbps network interface, and a high-speed PCIe host interface into a single field programmable gate array (FPGA) acceleration card. The proposed FAST decoder adopts the finite state machines-coordinated sequence mapping table to achieve run-time reconfigurability over fine-grained FPGA programming, and 16 fields can be decoded simultaneously in a pipelined manner, resulting in a decoding latency of only 33 ns. Evaluated on the Xilinx Alveo U200 acceleration card, this work improves the latency of decoding a FAST message by 26%–72% than state-of-the-art FPGA designs, and outperforms the software baseline by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$&gt;27\times$</tex-math></inline-formula> in terms of latency covering both decoding and communication.

Design of novel fractional order FPGA based reactor protection and safety controllers for ACP1000 nuclear power plant in LabVIEW

In this research work, an advanced most modern ACP1000 Nuclear Power Plant is addressed. An enhanced fractional order model of ACP1000 nuclear power plant is adopted with an addition of protection and safety systems. The whole plant model is developed by using innovative hybrid technology of Visual Basic, LabVIEW, Fractional Order and Field Programmable Gate Array (FPGA). A reactor trip system is designed and modeled using FPGA technology in LabVIEW. Plant parameters are systematically modeled and panels are designed in LabVIEW for reactor protection controllers. Twenty one reactor trip controllers are designed and modeled based on complex digital logics using FPGA programming in LabVIEW. Two fractional order trip controllers are designed for over temperature protection and over power protection in LabVIEW. FPGA based safety controllers are designed for Engineered Safety Features (ESF) in LabVIEW. For enhanced model of ACP1000 nuclear power plant, 374 systems are modeled in modular form in Visual Basic Environment. Nine process controllers are configured in ANFIS framework in LabVIEW. In this research work, process controllers are used in conjunction with protection and safety controllers using FPGA. The parametric display of simulations is carried out in Visual Basic. The closed loop performance of proposed protection controllers is evaluated under reactor trip and turbine trip while that of safety controllers are evaluated under inadvertent opening of safety valves of pressurizer. Various parameters are simulated for severe transient conditions and the results are evaluated and validated against reference design data and Final Safety Analysis Report (FSAR) of ACP1000 nuclear power plant. All the results are well within the trip and safety systems design bounds under abnormal and severe operating conditions.

Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAs

Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications, embedded, and an emerging alternative for cloud-scale acceleration. However, FPGA adoption found limitations in their programmability and required knowledge. Therefore, researchers focused on FPGA abstractions and automation tools. Here, we survey three leading digital design abstractions: Hardware Description Languages (HDLs) , High-Level Synthesis (HLS) tools, and Domain-Specific Languages (DSLs) . We review these abstraction solutions, provide a timeline, and propose a taxonomy for each abstraction trend: programming models for HDLs; Intellectual Property (IP) -based or System-based toolchains for HLS; application, architecture, and infrastructure domains for DSLs.

Software Design of VerilogHDL Code Generation for Ladder Diagram and Data Acquisition Using LABVIEW

Powerful advantages of programmable logic controller (PLC) dominate process industries. Scan time of PLC increases with the number of inputs, rungs added in ladder diagram (LD). Researchers have identified and proved that field programmable gate array (FPGA) is more suitable than PLC for high speed applications. PLC executes the instructions represented through LD. PLC programmers are not familiar with FPGA programming. But, FPGA does not support LD based programming. This work has developed application software to generate equivalent VerilogHDL code for LD using LabVIEW. Novelty in this work is that each rung is defined using an "assign" statement which helps simultaneous execution of all the rungs. A data acquisition system was created to monitor the digital signals handled by the FPGA. The software was verified with a case study of substances mixing and traffic light control system.

Kendali Kecepatan Switched Reluctance Motor Berbasis FPGA

-- Renewable drive technology is developing in the current era, one of which is electric transportation. The Switched Reluctance Motor (SRM) was chosen for the transportation development because it has many advantages, including not using permanent magnets and simple construction in the form of an iron core in the rotor and stator windings. SRM works based on the reluctance phenomenon, namely, if the stator is energized, the stator will attract the nearby rotor, this is based on the tendency of the rotor poles to align with the stator excitation poles. SRM requires high speed switching control to operate and requires correct rotor position to operate. Maximum switching and good accuracy can use Field-Programmable Gate Array (FPGA) and rotary encoder as input for rotor position information. To use SRM in electric transport, it is necessary to adjust the speed with ease and precision. With the Pulse Width Modulation (PWM) technique, the size of the excitation depends on the size of the current, the size of the current is determined by the input voltage to the SRM. In this control, the PWM width can be changed by setting the carrier set and modulation set in the FPGA program. In this study, it is proposed to control the SRM speed by adjusting the PWM of the rotary encoder to produce the desired RPM. To support the achievement of this research, hardware testing was carried out in the laboratory. Keywords-- Duty cycle, FPGA, PWM, Reluctance, Switched Reluctance Motor.

Eğitsel SDR Tekniklerine Dayalı FPGA Tabanlı FM Radyo Verici Tasarım ve Uygulaması

The basic purpose of Software Defined Radio (SDR) systems is to use a digital signal processor to numerically handle radio signals. The use of a processor like a Field Programmable Gate Array (FPGA) to perform tasks like modulation, demodulation, signal creation, and line coding on these systems dramatically decreases the demand for analog circuit-based hardware. FPGAs are digital integrated circuits with a wide range of applications which are made up of links between programmable logic blocks. It's aimed at assisting the creator realize the logic functions that the designer needs. In consequence, the user may change the function of each logic block. VHSIC Hardware Description Language (VHDL) is commonly used in FPGA programming. In this study, VHDL code was created, and a FM transmitter was implemented on a FPGA board (CMOD A7) in this research. The sound card interface on the PC used to send and receive the signals while suitable ADC and DAC cards are used on the FPGA side for the same purpose. Audacity program was used to playback the sample wav files while HDSDR SDR program was used to monitor and record the signals in wav file format. Finally, using the MATLAB code, the recorded transmitter signal was demodulated offline, and the output was stored to the hard drive. The demodulated signal obtained is identical to the initial modulation signal, indicating that the modulation was correctly executed. As a result, a perfect foundation for the development and training of SDR systems using FPGA has been established.

Optimization with the OpenACC-to-FPGA framework on the Arria 10 and Stratix 10 FPGAs

The reconfigurable computing paradigm with field programmable gate arrays (FPGAs) has received renewed interest in the high-performance computing field due to FPGAs’ unique combination of performance and energy efficiency. However, difficulties in programming and optimizing FPGAs have prevented them from being widely accepted as general-purpose computing devices. In accelerator-based heterogeneous computing, portability across diverse heterogeneous devices is also an important issue, but the unique architectural features in FPGAs make this difficult to achieve. To address these issues, a directive-based, high-level FPGA programming and optimization framework was previously developed. In this work, developed optimizations were combined holistically using the directive-based approach to show that each individual benchmark requires a unique set of optimizations to maximize performance. We perform this exploration on Intel Arria 10 and Stratix 10 FPGAs. We also explored the relationships between performance, resource usages, and compilation times, and investigated implications for performance portability. Finally, we present an initial evaluation of a real-world proxy application, LULESH.

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

SummaryStatistical analysis of High Efficiency Video Coding (HEVC) encoder reveals that in the motion compensation block, the interpolation filter consumes more than 30% in the encoder time in comparison with other blocks. In this paper, we start with an optimized hardware implementation of the interpolation filter on field‐programmable gate array (FPGA) based on Xilinx setup environment. In a second step, a Hardware/Software (HW/SW) co‐design implementation of HM16.7 encoder is performed on Zynq MPSoC platform to evaluate the proposed interpolation filter IP in terms of total encoder run‐time, taking advantages of both processing units (quad‐core ARM Cortex TM‐A53 processor and Programmable Logic FPGA component) available on the Zynq MPSoC. The proposed architecture of luma and chroma filters was simulated and synthesized on Xilinx XCZU7EV‐2FFVC1156 FPGA at 250‐MHz clock frequency. The synthesis results present an optimized power consumption of 3.308 mW for higher resolutions (2560 × 1600 and 1920 × 1080) at 50 fps with the use of just 1% of the FPGA resources. The experimental results of the co‐design implementation of HEVC encoder present a speedup of 2 times (41% in PeopleOnStreet sequence) in terms of processing time compared to the software alone implementation, with a an increase of 0.51% of bit rate and a very small degradation of peak signal‐to‐noise ratio (PSNR) (0.01%).

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs

Ever since transistor cost stopped decreasing, customized programmable platforms, such as field-programmable gate arrays (FPGAs), became a major way to improve software execution performance and energy consumption. While software developers can use high-level synthesis (HLS) to speed up register-transfer level (RTL) code generation from C++ or OpenCL source code, placement and routing issues, such as congestion, can still prevent achieving an FPGA programming bitstream or dramatically reduce the FPGA implementation performance. Congestion reports from physical design tools refer to thousands of RTL signal names instead of developer-accessible identifiers and statements, considerably complicating the developer understanding and resolution of the issues at the source level. We propose a high-level back-annotation flow that summarizes the routing congestion issues at the source level by analyzing the reports from the FPGA physical design tools and the internal debugging files of the HLS tools. Our flow describes congestion using comments back-annotated on the source code and identifies if the congestion causes are the on-chip memories or the DSP units (multipliers/adders), which are the shared resources very often associated with routing problems on FPGAs. We demonstrate on realistic large designs how the information provided by our flow helps to quickly spot congestion causes at the source level and to solve them using appropriate HLS directives.

Introduction Of Special Issue on FPGA-Based Computing [From The Guest Editors

The articles in this special section focus on field-programmable gate arrays (FPGAs)- based computing. Over the past three decades, FPGAs have evolved from small chips with a few thousand logic blocks to billion- transistor system-on-chips. Modern FPGAs provide massive fine-grained parallelism, high energy efficiency, and more predictable performance than CPUs and GPUs. More importantly, they can be reconfigured to implement a special-purpose architecture that is specifically customized based on the key characteristics of a target application (or domain). For these reasons, recent years have seen a rapidly increasing use of FPGAs for computing, where a plethora of new architectures, compilers, and FPGA-accelerated applications are being demonstrated and actively developed. This special issue includes five survey papers from renowned experts in the field of FPGAs. The goal is to summarize some of the recent advances on FPGA-based computing, to elucidate the architecture- and application-level trends, and to promote new tools to enable productive FPGA programming.

UNILOGIC

One of the main characteristics of High-performance Computing (HPC) applications is that they become increasingly performance and power demanding, pushing HPC systems to their limits. Existing HPC systems have not yet reached exascale performance mainly due to power limitations. Extrapolating from today’s top HPC systems, about 100–200 MWatts would be required to sustain an exaflop-level of performance. A promising solution for tackling power limitations is the deployment of energy-efficient reconfigurable resources (in the form of Field-programmable Gate Arrays (FPGAs)) tightly integrated with conventional CPUs. However, current FPGA tools and programming environments are optimized for accelerating a single application or even task on a single FPGA device. In this work, we present UNILOGIC (Unified Logic), a novel HPC-tailored parallel architecture that efficiently incorporates FPGAs. UNILOGIC adopts the Partitioned Global Address Space (PGAS) model and extends it to include hardware accelerators, i.e., tasks implemented on the reconfigurable resources. The main advantages of UNILOGIC are that (i) the hardware accelerators can be accessed directly by any processor in the system, and (ii) the hardware accelerators can access any memory location in the system. In this way, the proposed architecture offers a unified environment where all the reconfigurable resources can be seamlessly used by any processor/operating system. The UNILOGIC architecture also provides hardware virtualization of the reconfigurable logic so that the hardware accelerators can be shared among multiple applications or tasks. The FPGA layer of the architecture is implemented by splitting its reconfigurable resources into (i) a static partition, which provides the PGAS-related communication infrastructure, and (ii) fixed-size and dynamically reconfigurable slots that can be programmed and accessed independently or combined together to support both fine and coarse grain reconfiguration. 1 Finally, the UNILOGIC architecture has been evaluated on a custom prototype that consists of two 1U chassis, each of which includes eight interconnected daughter boards, called Quad-FPGA Daughter Boards (QFDBs); each QFDB supports four tightly coupled Xilinx Zynq Ultrascale+ MPSoCs as well as 64 Gigabytes of DDR4 memory, and thus, the prototype features a total of 64 Zynq MPSoCs and 1 Terabyte of memory. We tuned and evaluated the UNILOGIC prototype using both low-level (baremetal) performance tests, as well as two popular real-world HPC applications, one compute-intensive and one data-intensive. Our evaluation shows that UNILOGIC offers impressive performance that ranges from being 2.5 to 400 times faster and 46 to 300 times more energy efficient compared to conventional parallel systems utilizing only high-end CPUs, while it also outperforms GPUs by a factor ranging from 3 to 6 times in terms of time to solution, and from 10 to 20 times in terms of energy to solution.

Remote update solution for LHAASO wide field-of-view Cherenkov telescope array electronic readout system

The wide field-of-view Cherenkov telescope array (WFCTA), which consists of 18 wide field telescopes, is one of the main detectors used in the Large High Altitude Air Shower Observatory (LHAASO) . The WFCTA collects Cherenkov light and fluorescence signals from cosmic ray showers and converts them into electrical signals that are then processed by an electronic system based on a field-programmable gate array (FPGA) for later physical analysis. The high altitude of the array and the difficulties involved in disassembling the electronics inside the telescope mean that an electronic remote update solution with high fault tolerance and simple operation is required. The proposed remote update solution for the LHAASO-WFCTA electronic readout system is based on Xilinx Multiboot and is intended to implement remote updates without appended circuits. When compared with other remote update solutions based on Multiboot, the solution used on the WFCTA saves numerous resources in the original FPGA program, eases the timing constraint burden, and enhances security. This solution has been successfully implemented and used in remote updating of FPGAs in the LHAASO-WFCTA several times.

FPGA Based Real Time Simulations of the Face Milling Process

The article presents a successful implementation of the milling process simulation at the Field-Programmable Gate Array (FPGA). By using FPGA, very rigorous Real-Time (RT) simulation requirements can be met. The response time of the FPGA simulations is significantly reduced, and the time synchronization is better than in a typical RT system implemented in software. The FPGA-based approach is characterized by enormous flexibility when it comes to input and output operations that can be implemented deterministically in RT. Complex simulation software has been implemented using the High Level Synthesis technique, which is a relatively easy and fast approach for FPGA programming without using complex Hardware Description Languages. The hardware functions are based on procedures written in high-level C programming language. The mathematical descriptions of simulations, results of computer simulations, Hardware-in-the-Loop Simulation experiments, and real experiments are presented. The approach presented in this paper can be used to simulate the dynamics of various mechatronic systems.

Forming and Co-simulation of Square and Triangular Waveforms by Using System Generator

Nowadays Field Programmable Gate Arrays(FPGAs) are used to implement several processes in different areas such military defense, medical devices, automation, telecommunication, and image processing etc. Some of the advantages of FPGA are parallel and hardware processing. On the other hand programming FPGAs by classic design methodologies requires much effort. Therefore, design tools like System Generator can provide facilities about programming FPGAs. System Generator is a design tool from Xilinx to program the Xilinx FPGAs in MATLAB/Simulink graphic based editor. Also its block set is limited with respect to Simulink, has. In this study square, and triangular waveforms are built with the basic blocks of System Generator tool. These waveforms belong to basic sources for signal processing. Generally, they are used in power electronics especially for producing PWM, or sinus PWM. Also co-simulation can be done by using System Generator. Square waveform block, which is implemented, has variable amplitude, frequency, duty cycle, and offset values whereas triangular waveform has variable amplitude, frequency, and offset values. Triangular waveform has an error as 2 % due to data bus width.

OpenCL Implementation of FPGA-Based Signal Generation and Measurement

Signal generation and measurement have been widely used in many engineering applications, such as for creating test signals in radar, communication, and software-defined radio. In field programmable gate array (FPGA) design, to generate and measure an analog signal, compatible software and hardware interfaces are required. Traditionally, hardware description language (HDL) is required to program an FPGA. HDL programming provides an efficient logic resource with low latency. However, it is time-consuming for designs that are more complex. Currently, OpenCL is implemented for FPGA programming. OpenCL reduces the FPGA development time because it increases the abstraction level of the code. OpenCL is an open and royalty-free framework for accelerating the algorithm executed on a heterogeneous system, such as a GPU, CPU, DSP, or FPGA. OpenCL implementation on FPGAs yields high-performance results for the computation process. However, compared to HDL design, OpenCL does not provide a particular function to access the FPGA hardware directly. In this paper, we have demonstrated the implementation of OpenCL programming on an FPGA for signal generation and measurement. We have developed OpenCL components that can interact with the FPGA hardware directly. An OpenCL I/O channel extension is employed in the kernel to read data from and write data to the OpenCL components. The experimental results indicate that OpenCL can be used for signal measurement and generation using FPGAs.

Hardware software co-design in Haskell

We present a library in Haskell for programming Field Programmable Gate Arrays (FPGAs), including hardware software co-design. Code for software (in C) and hardware (in VHDL) is generated from a single program, along with the code to support communication between hardware and software. We present type-based techniques for the simultaneous implementation of more than one embedded domain specific language (EDSL). We build upon a generic representation of imperative programs that is loosely coupled to instruction and expression types, allowing the individual parts to be developed and improved separately. Code generation is implemented as a series of translations between progressively smaller, typed EDSLs, safeguarding against errors that arise in untyped translations. Initial case studies show promising performance.

Melia: A MapReduce Framework on OpenCL-Based FPGAs

MapReduce, originally developed by Google for search applications, has recently become a popular programming framework for parallel and distributed environments. This paper presents an energy-efficient architecture design for MapReduce on Field Programmable Gate Arrays (FPGAs). The major goal is to enable users to program FPGAs with simple MapReduce interfaces, and meanwhile to embrace automatic performance optimizations within the MapReduce framework. Compared to other processors like CPUs and GPUs, FPGAs are (re-)programmable hardware and have very low energy consumption. However, the design and implementation of MapReduce on FPGAs can be challenging: firstly, FPGAs are usually programmed with hardware description languages, which hurts the programmability of the MapReduce design to its users; secondly, since MapReduce has irregular access patterns (especially in the reduce phase) and needs to support user-defined functions, careful designs and optimizations are required for efficiency. In this paper, we design, implement and evaluate Melia , a MapReduce framework on FPGAs. Melia takes advantage of the recent OpenCL programming framework developed for Altera FPGAs, and abstracts FPGAs behind the simple and familiar MapReduce interfaces in C. We further develop a series of FPGA-centric optimization techniques to improve the efficiency of Melia, and a cost- and resource-based approach to automate the parameter settings for those optimizations. We evaluate Melia on a recent Altera Stratix V GX FPGA with a number of commonly used MapReduce benchmarks. Our results demonstrate that 1) the efficiency and effectiveness of our optimizations and automated parameter setting approach, 2) Melia can achieve promising energy efficiency in comparison with its counterparts on CPUs/GPUs on both single-FPGA and cluster settings.

A Gracefully Degrading and Energy-Efficient FPGA Programming using LabVIEW

&lt;p&gt;Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.&lt;/p&gt;