FPGA Based Real Time Simulations of the Face Milling Process

Michal R Mazur,Krzysztof J Kalinski,Marek A Galewski

doi:10.1109/access.2020.3041177

Michal R Mazur, Krzysztof J Kalinski + Show 1 more

Open Access

https://doi.org/10.1109/access.2020.3041177

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Journal: IEEE Access	Publication Date: Jan 1, 2020
Citations: 29	License type: CC BY 4.0

Affiliation: Gdańsk University of Technology

Abstract

The article presents a successful implementation of the milling process simulation at the Field-Programmable Gate Array (FPGA). By using FPGA, very rigorous Real-Time (RT) simulation requirements can be met. The response time of the FPGA simulations is significantly reduced, and the time synchronization is better than in a typical RT system implemented in software. The FPGA-based approach is characterized by enormous flexibility when it comes to input and output operations that can be implemented deterministically in RT. Complex simulation software has been implemented using the High Level Synthesis technique, which is a relatively easy and fast approach for FPGA programming without using complex Hardware Description Languages. The hardware functions are based on procedures written in high-level C programming language. The mathematical descriptions of simulations, results of computer simulations, Hardware-in-the-Loop Simulation experiments, and real experiments are presented. The approach presented in this paper can be used to simulate the dynamics of various mechatronic systems.

Highlights

The paper concerns the simulation of the milling process with simulation procedures implemented in the FPGA (Field-Programmable Gate Array) system using the High Level Synthesis (HLS) technique [1,2,3]
Real Time (RT) EXPERIMENTAL VALIDATION It was assumed that the hardware implementation of the RT milling process simulation would be part of the Hardware-in-the-Loop Simulation (HiLS) system designed to develop a tool for detecting self-excited chatter vibrations
SUMMARY AND CONCLUSIONS The presented RT hardware simulation results allow for the conclusion that it is possible to create RT simulations of a complex process, e.g. dynamic milling systems using FPGA and HLS techniques

Summary

INTRODUCTION

The paper concerns the simulation of the milling process with simulation procedures implemented in the FPGA (Field-Programmable Gate Array) system using the High Level Synthesis (HLS) technique [1,2,3]. Making changes to the simulated system may be restricted to a limited range of parameters only because major changes may even require redesigning the analog subsystem or replacing its components To solve this problem, the hardware implementation of the computational simulation algorithm can be realized using CPLDs (Complex Programmable Logic Devices) or FPGAs. When operating FPGAs with a relatively low frequency (e.g. 100 MHz), it is possible to obtain response time (excluding the time needed to propagate signals in additional input and output circuits) at the microsecond level and with jitter limited to a few nanoseconds. 100 MHz), it is possible to obtain response time (excluding the time needed to propagate signals in additional input and output circuits) at the microsecond level and with jitter limited to a few nanoseconds In this way, FPGA-based simulation systems provide a response time that can be compared with analog systems, while maintaining the reliability of digital systems. Due to the use of HLS, various control procedures can be implemented relatively quickly on FPGA [28], the knowledge presented in this document may be applicable to the simulation of the milling process, and to other HiLS applications or control problems in general [29]

MILLING SIMULATIONS

DESCRIPTION OF THE CUTTING PROCESS

D Ol w l

SIMULATION AND EXPERIMENTAL RESULTS

Findings

SUMMARY AND CONCLUSIONS