Field-programmable Gate Array Emulation Research Articles

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

This article presents an open-source framework for emulating mixed-signal chip designs on a field-programmable gate array (FPGA). It includes a Python-based synthesizable model generator for mixed-signal blocks (msdsl), a fixed-point and floating-point synthesizable SystemVerilog library for representing real numbers (svreal), and a Python-based tool that generates emulator control infrastructure and automates the FPGA build process (anasymod). The framework includes features for efficiently modeling analog dynamics, nonlinearity, and noise, often making use of compile-time caching to reduce the required computational resources of the FPGA. We demonstrate the framework’s generality by discussing three applications: 1) a high-speed link receiver (DragonPHY); 2) a firmware-controlled flyback converter; and 3) an NFC-powered chip. Our framework makes it easy to emulate these systems, while providing runtimes 2–3 orders of magnitude faster than CPU simulations with real-number functional models.

FPGA-Based Rate-Compatible LDPC Codes for the Next Generation of Optical Transmission Systems

In this paper, we propose a rate-compatible forward error-correcting (FEC) scheme based on low-density-parity check (LDPC) codes together with its software reconfigurable unified field-programmable gate array (FPGA) architecture. By FPGA emulation, we demonstrate that the proposed class of rate-compatible LDPC codes based on puncturing and generalized LDPC coding with an overhead from 25% to 46% provides a coding gain ranging from 12.67 to 13.8 dB at a post-FEC bit-error rate (BER) of 10−15. As a result, the proposed rate-compatible codes represent one of the strong FEC candidates of soft-decision FEC for both short-haul and long-haul optical transmission systems.

A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection

Real-time object detection is becoming necessary for a wide number of applications related to computer vision and image processing, security, bioinformatics, and several other areas. Existing software implementations of object detection algorithms are constrained in small-sized images and rely on favorable conditions in the image frame to achieve real-time detection frame rates. Efforts to design hardware architectures have yielded encouraging results, yet are mostly directed towards a single application, targeting specific operating environments. Consequently, there is a need for hardware architectures capable of detecting several objects in large image frames, and which can be used under several object detection scenarios. In this work, we present a generic, flexible parallel architecture, which is suitable for all ranges of object detection applications and image sizes. The architecture implements the AdaBoost-based detection algorithm, which is considered one of the most efficient object detection algorithms. Through both field-programmable gate array emulation and large-scale implementation, and register transfer level synthesis and simulation, we illustrate that the architecture can detect objects in large images (up to 1024 × 768 pixels) with frame rates that can vary between 64-139 fps for various applications and input image frame sizes.

Latch-based FPGA emulation method for design verification: case study with microprocessor

Using latches in a digital design is considered wrong owing to the timing issue. Field-programmable gate array (FPGA) vendors also recommend flip-flops instead of latches in emulation. In this reported work, however, the usefulness and benefit of utilising latches in FPGA emulation for processor design verification is demonstrated. The study shows that a latch-based register file provides the seamless capability of functionality validation, whereas the flip-flop based one requires modification to the original design, potentially harming the completeness of functional verification. Experiment results with Xilinx and Altera devices show marginal differences in terms of emulation performance and area requirement in both approaches. This study reveals that replacing SRAM with latches rather than flip-flops is appealing and preferable in emulation with FPGAs.

Highly Parallel FPGA Emulation for LDPC Error Floor Characterization in Perpendicular Magnetic Recording Channel

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Low-density parity-check (LDPC) codes offer a promising error correction approach for high-density magnetic recording systems due to their near-Shannon limit error-correcting performance. However, evaluation of LDPC codes at the extremely low bit error rates (BER) required by hard disk drive systems, typically around <formula formulatype="inline"><tex Notation="TeX">$10^{-12}$</tex> </formula> to <formula formulatype="inline"><tex Notation="TeX">$10^{- 15}$</tex> </formula>, cannot be carried out on high-performance workstations using conventional Monte Carlo techniques in a tractable amount of time. Even field-programmable gate array (FPGA) emulation platforms take a few weeks to reach BER between <formula formulatype="inline"><tex Notation="TeX">$10^{-11}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">$10^{-12}$</tex></formula>. Thus, we implemented a highly parallel FPGA processing cluster to emulate a perpendicular magnetic recording channel, which enabled us to accelerate the emulation by <formula formulatype="inline"><tex Notation="TeX">$&gt; 100 \times$</tex></formula> over the fastest reported emulation. This increased throughput enabled us to characterize the performance of LDPC code BER down to near <formula formulatype="inline"> <tex Notation="TeX">$10^{- 14}$</tex></formula> and investigate its error floor. </para>