Highly Parallel FPGA Emulation for LDPC Error Floor Characterization in Perpendicular Magnetic Recording Channel

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Low-density parity-check (LDPC) codes offer a promising error correction approach for high-density magnetic recording systems due to their near-Shannon limit error-correcting performance. However, evaluation of LDPC codes at the extremely low bit error rates (BER) required by hard disk drive systems, typically around <formula formulatype="inline"><tex Notation="TeX">$10^{-12}$</tex> </formula> to <formula formulatype="inline"><tex Notation="TeX">$10^{- 15}$</tex> </formula>, cannot be carried out on high-performance workstations using conventional Monte Carlo techniques in a tractable amount of time. Even field-programmable gate array (FPGA) emulation platforms take a few weeks to reach BER between <formula formulatype="inline"><tex Notation="TeX">$10^{-11}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">$10^{-12}$</tex></formula>. Thus, we implemented a highly parallel FPGA processing cluster to emulate a perpendicular magnetic recording channel, which enabled us to accelerate the emulation by <formula formulatype="inline"><tex Notation="TeX">$&gt; 100 \times$</tex></formula> over the fastest reported emulation. This increased throughput enabled us to characterize the performance of LDPC code BER down to near <formula formulatype="inline"> <tex Notation="TeX">$10^{- 14}$</tex></formula> and investigate its error floor. </para>