Field Programmable Gate Array Development Board Research Articles

MBIST Implementation and Evaluation in FPGA Based on Low-Complexity March Algorithms

March algorithms are widely used in Memory Built-In Self-Test (MBIST) on-chip memory testing, providing linear test complexities that reduce the test time and cost. However, studies show that March algorithms with complexities lower than 18N have poor coverages of faults that have emerged with the advent of the nanometer process technologies and are more relevant to nowadays memories. New March AZ1 and March AZ2 algorithms, with 13N and 14N complexities, respectively, were introduced to provide optimum coverage of those faults and to produce a shorter test than an 18N-complexity test algorithm with a lesser area overhead, thus reducing chip manufacturing costs. This paper presents the implementation and validation of MBIST controllers that applied the March AZ1 and March AZ2 algorithms in a Field-Programmable Gate Array (FPGA) device. They were implemented in the Intel Max 10 DE10-Lite FPGA Development Board. A test generator was built in FPGA, as an alternative to the external tester, to provide test vectors required in initiating the test on the memory model using the implemented MBIST. The FPGA experimental tests demonstrated that they function correctly as the expected test sequences were observed. In addition, their fault detection abilities were also validated through tests on a fault-injected memory model, which shows that the implemented March AZ1 and March AZ2 provide 80.6% and 83.3% coverage of the intended faults, respectively, which outperform any other existing 14N-complexity March algorithms.

Design and Testing of a Wireless Communication Enabled FPGA Development Board: A Comprehensive Education and Application Platform from IoT to Circuit Design

Field Programmable Gate Array (FPGA) is an integrated circuit (IC) that can be reprogrammed or configured by the customer or designer after production for rapid prototyping and post-process development. In this study, a cost-effective FPGA development board is designed to create basic engineering education applications and implement them in real-time. The FPGA development board utilizes an Altera Cyclone IV E-series chip and includes Bluetooth and Wi-Fi modules to provide a wider range of applications. This integration simplifies the use of wireless communication in various projects and applications for researchers and engineers. To verify the accuracy of the proposed board, simulations of selected digital designs and Bluetooth applications were first performed in VHDL (Very High Speed Integrated Circuit Hardware Description Language) using Intel® Quartus® Prime Lite Edition software. Then, experiments were performed on the board following the pin assignment configurations. It was observed that the developed applications worked successfully on the FPGA development board. As a result, this board, equipped with Bluetooth and Wi-Fi modules, offers a fast and cost-effective solution for users in various fields such as mobile, robotics, smart home systems, and remote monitoring and control devices

FPGA based telecommand system for balloon-borne scientific payloads

Abstract Telecommand (TC) plays a crucial role in the success of high-altitude balloon experiments. Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes are commonly employed to ensure reliable command operation. The Balloon Facility (BF) of Tata Institute of Fundamental Research (TIFR) uses a TC system based on BCH (31,16) coding technique, to control balloon and payload operations. This paper presents prototyping and implementation of TC encoder and decoder using Spartan 6 Field Programmable Gate Array (FPGA). The code is written in Very high-speed integrated circuit Hardware Description Language (VHDL). Simulation and synthesis are done using Xilinx ISE 14.7 design suite. Simulation results show the design is robust. The TC encoder is implemented in a commercial FPGA development board and the TC decoder is implemented in a specially designed FPGA board, successfully. This paper presents the salient features of the TC system in use and the implementation of the system using FPGA.

A 4.32-ps precision Time-to-Digital Convertor using multisampling wave union method on a 28-nm FPGA

In this paper, a fully implemented field programmable gate array (FPGA) based time-to-digital converter (TDC) using multisampling wave union method (MSWU) is proposed to get higher measurement precision with lower resource utilization. Different from the previously published works based on wave union methods, an inverter-chain-based wave launcher is introduced to generate more low-jitter edges in the same operation range. Meanwhile, a new de-bubble solution combining with offline bin alignment and online bin sorting is applied to eliminate severe bubbles in FPGAs of advanced manufacturing technologies. The proposed TDCs are verified on a Virtex-7 (28 nm) of FPGA development board VC707. According to test results, the average measurement precision and mean resolution reach 4.32 ps and 0.82 ps, respectively with [-0.98;3.43] LSB DNL and [-6.06;34.1] LSB INL. A complete TDC channel only uses 831 D-type flip-flops (DFFs), 1305 look-up tables (LUTs) and 6 block random access memories (BRAMs) of 36k bits.

A field programmable gate array-based biomedical noise reduction framework using advanced trilateral filter

Filtering is one of the essential tools utilized to remove undesirable features in biomedical images. Most biomedical image denoising systems are used for clinical diagnosis. So, in this paper, we use the advanced trilateral filter in the field programmable gate array (FPGA) for removing noise in the biomedical image. Generally, the trilateral filter is used as an edge preserving smoothing filter. This advanced approach of trilateral filter gives the best noise diminution and enhances the image quality. This paper also proposes the hardware implementation of an efficient FPGA-based advanced trilateral filter on real time execution. In this manuscript, we intend to design and implement the FPGA architecture using an advanced trilateral filter. Biomedical images with different noises are used during implementation and compared with the existing bilateral and trilateral architecture to assess the proposed architecture performance. For evaluating the performance metrics of the proposed advanced trilateral filter on MATLAB platform, peak signal-to-noise ratio (PSNR), mean squared error (MSE) and structured similarity index (SSIM) are calculated for different biomedical images – such as brain (MRI), chest (x-ray) and lungs (CT) – with different noises – such as salt and pepper, Gaussian, Poisson and Speckle noises – compared with existing bilateral filter and trilateral filter, respectively. The proposed advanced trilateral filter implementations are checked on Virtex-6, Virtex-7 and Zynq FPGA development board using Verilog programming language in Xilinx ISE 14.5 design tools. The simulation outcomes display that the FPGA execution of the advanced trilateral filter contains better noise removal efficiency in biomedical images compared with the existing bilateral and trilateral filter.

Post-Measurement Adjustment of the Coincidence Window in Quantum Optics Experiments

We report on an electronic coincidence detection circuit for quantum photonic applications implemented on a field-programmable gate array (FPGA), which records each the time separation between detection events coming from single-photon detectors. We achieve a coincidence window as narrow as 500 ps with a series of optimizations on a readily-available and affordable FPGA development board. Our implementation allows real-time visualization of coincidence measurements for multiple coincidence window widths simultaneously. To demonstrate the advantage of our high-resolution visualization, we certified the generation of polarized entangled photons by collecting data from multiple coincidence windows with minimal accidental counts, obtaining a violation of the Clauser-Horne-Shimony-Holt (CHSH) Bell inequality by more than 338 standard deviations. Our results have shown the applicability of our electronic design in the field of quantum information.

WITHDRAWN: Analysis, design and implementation of hardware neural network based rotor oscillations compensator

In this paper, an Artificial Neural Network (ANN) based Rotor Oscillations Compensator (ROC) is proposed and its equivalent Hardware Realizable Neural Network (HARNN) has been developed on the Field Programmable Gate Array (FPGA) board. The basic function of a ROC is to minimize the low frequency electro mechanical oscillations created in the Electric power network. Whenever the fault is occurred outside the operating range of a fixed gain ROC, the system damping is insufficient and the machine is still under unstable mode. Hence a hardware having sufficient “intelligence” that is capable of producing necessary and sufficient damping to the system is proposed in this paper. A detailed study has been done with the plant response without any controller, with a fixed gain controller and a FPGA based ANN controller. The studies revealed that when an intelligent controller has been included in the Exciter loop, the oscillations have been eliminated more effectively. But it is also observed that the realization of an ANN absolutely on an FPGA is having its own design limitations. The ARTIX 7 FPGA development board has been used for the complete analysis and the results and outcomes discussed at the end.

Hardware Root-of-Trust-based integrity for shared library function pointers in embedded systems

Many security measures designed for large-scale compute hardware (e.g., workstations and servers) are not optimized for embedded systems. One such measure, Relocation Read-Only (RelRO), protects binary relocation sections from tampering after dynamic linking; however, RelRO depends on the presence of memory management hardware that not all embedded systems include. More generally, the latest hardware modifications to processor architectures may not always be available to provide security in small-scale embedded systems. In this paper, we propose another solution for relocation protection for use in embedded systems that have a field-programmable gate array (FPGA) on chip. Our solution prevents relocation section overwrites from diverting control flow as they would in an unprotected binary by implementing a hardware Root of Trust into which to store and out of which to retrieve shared library function pointers. We offer two system variations which provide designers with flexibility to choose a lighter or a more robust protection. We also demonstrate a proof of concept implemented on a popular FPGA development board and provide comparison with RelRO. Our work provides embedded system developers with a security measure like RelRO without requiring a customized memory management unit. Our work is useful on computer systems that include embedded reconfigurable logic on chip. The authors believe this is the first paper in which reconfigurable logic is used to provide security functionality previously implemented in a custom instruction set or other computer architecture modifications. Our work points toward a future where FPGA logic embedded on chip can be adapted to improve the security of software.

FPGA-based hardware accelerator for SENSE (a parallel MR image reconstruction method)

SENSE (Sensitivity Encoding) is a parallel MRI (pMRI) technique that allows accelerated data acquisition using multiple receiver coils and reconstructs the artifact-free images from the acquired under-sampled data. However, an increasing number of receiver coils has raised the computational demands of pMRI techniques to an extent where the reconstruction time on general purpose computers becomes impractically long for real-time MRI. Field Programmable Gate Arrays (FPGAs) have recently emerged as a viable hardware platform for accelerating pMRI algorithms (e.g. SENSE). However, recent efforts to accelerate SENSE using FPGAs have been focused on a fixed number of receiver coils (L=8) and acceleration factor (Af=2). This paper presents a novel 32-bit floating-point FPGA-based hardware accelerator for SENSE (HW-ACC-SENSE); having an ability to work in coordination with an on-chip ARM processor performing reconstructions for different values of L and Af. Moreover, the proposed design provides flexibility to integrate multiple units of HW-ACC-SENSE with an on-chip ARM processor, for low-latency image reconstruction. The VIVADO High-Level-Synthesis (HLS) tool has been used to design and implement the HW-ACC-SENSE on the Xilinx FPGA development board (ZCU102). A series of experiments has been performed on in-vivo datasets acquired using 8, 12 and 30 receiver coil elements. The performance of the proposed architecture is compared with the single thread and multi-thread CPU-based implementations of SENSE. The results show that the proposed design withstands the reconstruction quality of the SENSE algorithm while demonstrating a maximum speed-gain up to 298× over the CPU counterparts in our experiments.

A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching

The scale invariant feature transform (SIFT) algorithm is considered a classical feature extraction algorithm within the field of computer vision. SIFT keypoint descriptor matching is a computationally intensive process due to the amount of data consumed. In this work, we designed a novel fully pipelined hardware accelerator architecture for SIFT keypoint descriptor matching. The accelerator core was implemented and tested on a field programmable gate array (FPGA). The proposed hardware architecture is able to properly handle the memory bandwidth necessary for a fully-pipelined implementation and hits the roofline performance model, achieving the potential maximum throughput. The fully pipelined matching architecture was designed based on the consine angle distance method. Our architecture was optimized for 16-bit fixed-point operations and implemented on hardware using a Xilinx Zynq-based FPGA development board. Our proposed architecture shows a noticeable reduction of area resources compared with its counterparts in literature, while maintaining high throughput by alleviating memory bandwidth restrictions. The results show a reduction in consumed device resources of up to 91% in LUTs and 79% of BRAMs. Our hardware implementation is 15.7 × faster than the comparable software approach.

Desarrollo de un sistema mecatrónico para robot humanoide que permita emular el movimiento del cuello de los seres humanos

En el presente trabajo se muestra el diseño de un sistema mecatrónico, el cual emula los movimientos del cuello humano, ya que sostendrá la cabeza de un robot humanoide (Arthur) desarrollado por la empresa Hanson Robotics. El diseño mecánico se basa en un robot esférico de 3 grados de libertad (3-GDL), se desarrolla el modelo dinámico a través de las ecuaciones de movimiento de Euler-Lagrange. La etapa de control es una tarjeta de desarrollo FPGA (arreglos de compuertas programables en campo) de la familia Cyclone IV, la etapa de potencia se basa en transistores BJT, se implementa el controlador Tangente hiperbólico y una interfaz de comunicación WiFi para configurar el robot desde una PC con ayuda del software Labview. Como resultado se muestra la integración del sistema mecatrónico, la interfaz desarrollada junto con la comunicación FPGA-PC y control de posición. El trabajo futuro será la implementación del sistema en el robot humanoide.

Design and Implementation of Multicore System for Wireless Intelligent Control

This paper presents the design and implementation of multicore system based on Nios II processor in field programmable gate array (FPGA) for wireless intelligent control. The system includes FPGA as a central controller to control the devices connected to it. We monitor the devices wirelessly by using the Bluetooth. We are using the android mobile for Bluetooth connectivity. The central implementation was conceded out by a Cyclone-II FPGA Development Board to evaluate the proposed concept of the system.

Facial Expression Emotion Detection for Real-Time Embedded Systems

Recently, real-time facial expression recognition has attracted more and more research. In this study, an automatic facial expression real-time system was built and tested. Firstly, the system and model were designed and tested on a MATLAB environment followed by a MATLAB Simulink environment that is capable of recognizing continuous facial expressions in real-time with a rate of 1 frame per second and that is implemented on a desktop PC. They have been evaluated in a public dataset, and the experimental results were promising. The dataset and labels used in this study were made from videos, which were recorded twice from five participants while watching a video. Secondly, in order to implement in real-time at a faster frame rate, the facial expression recognition system was built on the field-programmable gate array (FPGA). The camera sensor used in this work was a Digilent VmodCAM — stereo camera module. The model was built on the Atlys™ Spartan-6 FPGA development board. It can continuously perform emotional state recognition in real-time at a frame rate of 30. A graphical user interface was designed to display the participant’s video in real-time and two-dimensional predict labels of the emotion at the same time.

An Improved High-Resolution DPWM Control Circuit Based on FPGA

Digital pulse width modulation (DPWM) has advantages of strong anti-interference ability, high efficiency and good flexibility, therefore it has been widely used in switching power supply, communications, power control and transform and other fields. This paper proposed a high resolution DPWM control circuit based on field programmable gate array (FPGA), which solved the problem of low resolution and instability of the traditional DPWM control circuit. The principle of the proposed circuit is presented in this paper, and the circuit has been successfully implemented on the Xilinx Artix-7 FPGA development board. The experiment shows that, when the frequency of the circuit is 50 MHz, the resolution of DPWM can reach 78ps, and the proposed DPWM control circuit has wide application prospects.

No latency feedback controller coupled to real-time physical models using programmable hardware

Over the last years, advances in technology and methodology made it possible to simulate and synthesize highly realistic finite difference (FD) models in real-time or close to real-time. Still, most conventional processing platforms introduce latency to the signal processing chain due to sequential processing and/or communication protocol timing and throughput restrictions. This can act as a severe penalty when developing expressive controller interfaces for large geometry physical models. Using field programmable gate array (FPGA) hardware enables highly customized interface and FD model designs that are able to meet hard real-time requirements even for large physical models. In this work, a modified five-string banjo coupled to a real-time physical modeling synthesis application running on an FPGA development board is presented. The proposed methodology is an extension of an existing PCIe enabled interface which was primarily developed for research applications. The new interface is aimed at facilitating expressive interaction for musical purposes. The bi-directional excitation and feedback is realized using standard electro-mechanical sensors and actuators, making it possible to connect the string vibration of the modified banjo to arbitrary geometries as well as capturing the response of the modeled structure and feeding it back to the acoustic instrument. FD-models of different shapes and materials are implemented resulting in physically impossible instrument configurations yielding unique tone production capabilities.

Secure and Dependable NoC-Connected Systems on an FPGA Chip

The growing reliance on intellectual properties exposes systems on chip (SoCs) to many security vulnerabilities and is raising more and more concerns. At the same time, with the quick increase in chip density and deep scaling of feature size, current billion-transistor chip designs introduce more challenges to manufacturing fault-free chips. In this paper, we propose an integrated run-time solution for both security and fault tolerance of field-programmable gate arrays (FPGA)-based SoCs through digital signatures, live monitoring, adaptive routing, and partial reconfiguration supported by an in-house-developed network on chip, X-Network. Our X-Network reduces the ratio of required routers versus processing elements with better performance, and more importantly, offers more flexibility than conventional networks to facilitate fault tolerance and security designs. A multiplexed Montgomery modular multiplication architecture is used to increase the speed of the Rivest-Shamir-Adleman algorithm. The design has been implemented and tested on a Xilinx Virtex-6 FPGA development board. Experimental results show that even if up to 20% of the links in the network are faulty, our reconfigurable architecture and algorithm manage to route packets around such faults, and deliver them to their destinations in a relatively low latency. Unlike conventional fault-tolerant methods that usually require resource redundancy, our design does not incur significant area or speed degradation. The resource overhead for both security and fault-tolerant features is around 10% more lookup tables.

Low-Cost High-Accuracy QRS Detection for Body Area Network Applications

In this study, the low-cost So and Chan (SC) detection method for body area network is combined with the moving average and distance calculation methods for detecting R-waves. The proposed method is compared to existing methods in terms of noise immunity, R-wave detection accuracy, and heartbeat error percent (HBEP). The arrhythmia database provided by the Massachusetts Institute of Technology and Beth Israel Hospital is used. The proposed method effectively reduced HBEP compared to that of the traditional SC method (2.072 vs. 8.518%). R-wave detection verification is conducted using a field-programmable gate array development board, with the obtained R_point data imported into MATLAB for data comparison.

A novel hardware plane fitting implementation and applications for bionic vision

This paper presents a high-speed real-time plane fitting implementation on a field-programmable gate array (FPGA) platform. A novel hardware-based least squares algorithm fits planes to patches of points within a depth image captured using a Microsoft Kinect v2 sensor. The validity of a plane fit and the plane parameters are reported for each patch of 11 by 11 depth pixels. The high level of parallelism of operations in the algorithm has allowed for a fast, low-latency hardware implementation on an FPGA that is capable of processing depth data at a rate of 480 frames per second. A hybrid hardware---software end-to-end system integrates the hardware solution with the Kinect v2 sensor via a computer and PCI express communication link to a Terasic TR4 FPGA development board. We have also implemented two proof-of-concept object detection applications as future candidates for bionic vision systems. We show that our complete end-to-end system is capable of running at 60 frames per second. An analysis and characterisation of the Kinect v2 sensor errors has been performed in order to specify logic precision requirements, statistical testing of the validity of a plane fit, and achievable plane fitting angle resolution.

Simple and robust self‐healing technique for millimetre‐wave amplifiers

A simple and robust self-healing technique for millimetre-wave (mm-wave) amplifiers is proposed. The self-healing technique can correct the operation frequency shifting of the amplifier (including its input and output impedance matching shifting) due to process, voltage, and temperature variations and modelling inaccuracy. A mm-wave amplifier with digitally controlled artificial dielectric transmission lines as fine frequency tuning components and an on-chip power detector as the frequency shifting detector has been implemented in 65 nm complementary metal–oxide–semiconductor to verify the effectiveness of the technique. The operating frequency of five amplifier chips is calibrated by running the self-healing algorithm on a field-programmable gate array development board. On average, the gain of the amplifier is improved by 2.60 dB from 13.66 to 16.26 dB and the input matching is improved by 12.78 dB from −4.89 to −17.67 dB at 56 GHz after the proposed self-healing procedure.

FPGA Implementation of Multiplier for Floating-Point Numbers Based on IEEE 754-2008 Standard

This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis etc. Implementation of floating-point multiplication is handy and easy for high level language. However it is a challenging task to implement a floating-point multiplication in hardware level/low level language due to the complexity of algorithm. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floating-point multiplier module using Verilog Hardware Description Language (HDL). Electronic Design Automation (EDA) tool of Altera Quartus II has been used for floating-point multiplier. The hardware implementation has been done by downloading the Verilog code onto Altera DE2 FPGA development board and found a satisfactory performance.