FPGA-based hardware accelerator for SENSE (a parallel MR image reconstruction method)

Abstract

SENSE (Sensitivity Encoding) is a parallel MRI (pMRI) technique that allows accelerated data acquisition using multiple receiver coils and reconstructs the artifact-free images from the acquired under-sampled data. However, an increasing number of receiver coils has raised the computational demands of pMRI techniques to an extent where the reconstruction time on general purpose computers becomes impractically long for real-time MRI. Field Programmable Gate Arrays (FPGAs) have recently emerged as a viable hardware platform for accelerating pMRI algorithms (e.g. SENSE). However, recent efforts to accelerate SENSE using FPGAs have been focused on a fixed number of receiver coils (L=8) and acceleration factor (Af=2). This paper presents a novel 32-bit floating-point FPGA-based hardware accelerator for SENSE (HW-ACC-SENSE); having an ability to work in coordination with an on-chip ARM processor performing reconstructions for different values of L and Af. Moreover, the proposed design provides flexibility to integrate multiple units of HW-ACC-SENSE with an on-chip ARM processor, for low-latency image reconstruction. The VIVADO High-Level-Synthesis (HLS) tool has been used to design and implement the HW-ACC-SENSE on the Xilinx FPGA development board (ZCU102). A series of experiments has been performed on in-vivo datasets acquired using 8, 12 and 30 receiver coil elements. The performance of the proposed architecture is compared with the single thread and multi-thread CPU-based implementations of SENSE. The results show that the proposed design withstands the reconstruction quality of the SENSE algorithm while demonstrating a maximum speed-gain up to 298× over the CPU counterparts in our experiments.