Field Programmable Gate Array Chip Research Articles

Large-Scale Bio-Inspired FPGA Models for Path Planning.

The hippocampus provides significant inspiration for spatial navigation and memory in both humans and animals. Constructing large-scale spiking neural network (SNN) models based on the biological neural systems is an important approach to comprehend the computational principles and cognitive function of the hippocampus. Such models are usually implemented on neuromorphic computing platforms, which often have limited computing resources that constrain the achievable scale of the network. This work introduces a series of digital design methods to realize a Field-Programmable Gate Array (FPGA) friendly SNN model. The methods include FPGA-friendly nonlinear calculation modules and a fixed-point design algorithm. A brain-inspired large-scale SNN of ∼21 k place cells for path planning is mapped on FPGA. The results show that the path planning tasks in different environments are finished in real-time and the firing activities of place cells are successfully reproduced. With these methods, the achievable network size on one FPGA chip is increased by 1595 times with higher resource usage efficiency and faster computation speed compared to the state-of-the-art.

Field-programmable gate array-based residual amplitude modulation suppression and control for compact atomic clocks.

We designed a field-programmable gate array (FPGA) fabric to provide phase modulation techniques to lock lasers to optical frequency references. The method incorporates an active residual amplitude modulation (RAM) suppression scheme that relies on complex modulation. All the required servos to construct an optical atomic clock are incorporated into the same low-cost, commercial FPGA chip. We demonstrate a reliable, long-term RAM suppression of 60 dB with the remaining RAM level at -100 dBc and an improved stability of three decades when applied on a two-photon rubidium clock.

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

Field Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chips and the escalating scale of system designs, the significance of their accompanying Electronic Design Automation (EDA) tools has never been more pronounced. The placement process, serving as the linchpin in FPGA EDA, directly influences FPGA development and operational efficiency. This paper introduces an FPGA placement methodology hinging on the Verilog-to-Routing (VTR) framework. We introduce a novel packing approach grounded in the weighted Edmonds’ Blossom algorithm, ensuring that the CLB generation strategy aligns more closely with load-balanced distribution. Furthermore, we enhanced the electric field-driven resolver placement process for CLB locations and leverage GPU-accelerated design. Experimental results demonstrate substantial improvements over the traditional VTR algorithm, with an average optimization of 28.42% in the packing process runtime, an average acceleration ratio of 2.85 times in the placement phase, and a 39.97% reduction in total packing and placement runtime consumption.

A new design of a digital filter for an efficient field programmable gate array using quantum dot technology

Digital filtering algorithms are most frequently used to implement generic-based Field-programmable gate arrays (FPGAs) chips, which are used for higher sampling rates. In the filtering structure, delay and occupied areas play a vital role. Since the existing structures suffered from shortcomings such as high delay and high occupied area, implementing a high-performance digital filter circuit with high speed and low occupied area based on unique technology can significantly improve the performance of whole FPGA structures. One of the best technologies to implement this vital structure to solve these shortcomings is quantum-dot cellular automata (QCA) technology. This paper presents several new efficient full adders for digital filter applications based on quantum technology, including a multiplier, AND gate, and accumulator. The QCADesigner 2.0.3 tool is used to create and validate the suggested designs. According to the results, all designed circuits have simple structures with few quantum cells, low area, and low latency.

Fully Parallel Stochastic Computing Hardware Implementation of Convolutional Neural Networks for Edge Computing Applications.

Edge artificial intelligence (AI) is receiving a tremendous amount of interest from the machine learning community due to the ever-increasing popularization of the Internet of Things (IoT). Unfortunately, the incorporation of AI characteristics to edge computing devices presents the drawbacks of being power and area hungry for typical deep learning techniques such as convolutional neural networks (CNNs). In this work, we propose a power-and-area efficient architecture based on the exploitation of the correlation phenomenon in stochastic computing (SC) systems. The proposed architecture solves the challenges that a CNN implementation with SC (SC-CNN) may present, such as the high resources used in binary-to-stochastic conversion, the inaccuracy produced by undesired correlation between signals, and the complexity of the stochastic maximum function implementation. To prove that our architecture meets the requirements of edge intelligence realization, we embed a fully parallel CNN in a single field-programmable gate array (FPGA) chip. The results obtained showed a better performance than traditional binary logic and other SC implementations. In addition, we performed a full VLSI synthesis of the proposed design, showing that it presents better overall characteristics than other recently published VLSI architectures.

Multiloop Control With Two Duty-Ratio Feedforward Current Loops via Sensing Series-Capacitor Current for Voltage Doubler PFC Converter

In this paper, the voltage doubler PFC converter with two boost inductors and one series-capacitor is studied. Only when both symmetrical duty ratios are larger than 0.5, the conventional multiloop control with one inner current loop and one voltage loop can be directly applied to the voltage doubler PFC converter due to its topology asymmetry. To remove this duty-ratio limit, the multiloop control with two duty-ratio feedforward current loops is proposed where the series-capacitor current is sensed to reconstruct two inductor currents. It follows that the number of sensor in the proposed control is three equal to the number of sensor in the conventional multiloop control. The proposed method is implemented in a Field Programmable Gate Array (FPGA) chip. The provided simulation and experimental results validate the effectiveness.

Hardware in the Loop-Based Testing of Three Schemes for Mitigation the Effect of Unsymmetrical Grid Faults on DFIG

This paper presents three-proposed schemes to mitigate the effect of unsymmetrical voltage sag fault on a wind-driven grid-connected Double Fed Induction Generator (DFIG). The first tested scheme comprises a static compensator (STATCOM) connected to the DFIG stator, while a three-phase parallel RL external impedance is connected to the rotor circuit in the second scheme. The STATCOM and the added rotor impedance are connected simultaneously in the third scheme. The effect of applying the three schemes on the responses of the stator and rotor voltages and currents, the dc-link voltage and current, the electrical torque, and the rotor speed during an unsymmetrical voltage sag are presented and compared at sub-and super-synchronous speeds. All systems were emulated, implemented, and tested through an OPAL RT-4510 Digital Real-Time Simulator (DRTS) in a Hardware-In-the-Loop (HIL) application. The internal Field-Programmable Gate Array (FPGA) chip assisted in using this platform as a Rapid Control Prototyping (RCP) for virtual mitigation control and testing. The Matlab/ Simulink RT-lab software packages combination helped in the RT development environment. All real-time waveforms of parameters for the proposed scenarios were monitored through the HIL-controller and data acquisition interface and then compared with the simulated results. The results reveal that the simulation waveforms and the real time waveforms are congruent. Results prove the better performance of the DFIG during unsymmetrical voltage sag for sub-synchronous speed when applying both protection schemes, while best results are obtained when using only the rotor impedance at super-synchronous speed operation of the DFIG.

Optimal Design of Electromagnetic Tomography Flaw Detection System for Train Wheel Based on FPGA

Electromagnetic tomography (EMT) is a new type of nondestructive testing technology that can be used for metal flaw detection. The implementation of the signal demodulation and filtering algorithm of the current electromagnetic tomography flaw detection system relies on the microprocessor MCU, and the reliability is low in real time. To improve the reliability and system integration of signal processing and transmission of the electromagnetic tomography flaw detection system, this paper uses the field programmable gate array chip to integrate the excitation signal generation module and the digital demodulation module based on the EMT train wheel flaw detection system. A digital filter is designed, and the filter parameters are adjusted to achieve a signal-to-noise ratio of 15 dB. UDP communication protocol is utilized to realize Ethernet communication between FPGA and upper computer. Using three algorithms on the host computer for image reconstruction, the train wheel defect information is visualized. The experimental results show that the FPGA chip improves the immunity of the train wheel flaw detection system, realizes the high integration of the system, and achieves the purpose of train wheel defect detection.

A Legalization Algorithm for Heterogeneous FPGAs

Heterogeneous cells are cells with special functions in Field-Programmable Gate Arrays (FPGA) and gradually become an important resource of FPGA chips. The legalization algorithm is a key step in resolving the global placement results of heterogeneous cells to their actual locations. The algorithm in this paper is improved on the abacus algorithm. We use subspaces to evaluate the degree of congestion of cells and sort them, and use optional columns to filter to achieve a reasonable allocation of resources. The experimental results show that our work has less average moving and worst movement in the case of high density and complex distribution.

Enhancing Quality and Security of the PLL-TRNG

Field Programmable Gate Arrays (FPGAs) are used more and more frequently to implement cryptographic systems, which need random number generators (RNGs) to be embedded in the same device. The main challenge related to the implementation of a generator running inside FPGAs is that the physical source of randomness, such as jittered clock generator, is implemented in the configurable logic area, i.e. in the close vicinity of noisy running algorithms, which can have significant impact on generated numbers or even serve to attack the generator. A possible approach to prevent such influence is the use of Phase-Lock Loops (PLLs), which are separated from the re-configurable logic area inside the FPGA chip. In this paper, we propose a new architecture of the PLL-based TRNG including a method to avoid correlation in the output through control of timing in the sampling process, as well as new embedded tests based on the enhanced stochastic model. We also propose a workflow to help find the best parameters, such as output bitrate and entropy rate. We show that bitrates of around 400 kb/s or more can be achieved, while guaranteeing min-entropy rates per bit higher than 0.98 as required by the latest security standards.

A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design

Configuration circuitry is an essential component of a field-programmable gate array (FPGA) fabric, which enables the configuration of each programmable logic and takes over 40% of the FPGA chip area. Following the recent trends of automated custom FPGA design, it is essential to study the impact on the area and power of the configuration circuitry. This study compares the performance of different configuration circuitries using a strictly automated and complete standard cell-based semi-custom design methodology. We leverage an open-source framework, OpenFPGA, and extended it to support two configuration protocols: shift-register-based configuration (SRC) and memory-bank-based configuration (MBC) circuitries and their variants. We proposed area optimization strategies to improve the physical implementation of each configuration circuitry. Our results show that compared with naive SRC implementation, the proposed optimization strategies minimize the area overhead by more than 30% and power dissipation during programming by 20%. Whereas compared with MBC implementation, the optimized SRC implementation requires approximately a similar area. However, considering the more practical implementation of MBC with the write-verify functionality with optimized SRC implementation, the MBC implementation requires an 11% higher area and 30% higher routing wirelength, but results in a 62% reduction in the power dissipation during programming.

IRIS: An embedded secure boot for IoT devices

This study proposes a hardware secure boot solution, an instant retrieval information system (IRIS) that is suitable for integrating Internet of Things (IoT) devices. IRIS can boot a Linux kernel image pre-stores in removable media and comprises a data verifier securing the authenticity, integrity, and confidentiality of the boot process. IRIS is fully developed as a hardware module and the results reveal short boot-up times and a small hardware footprint when implemented on field programmable gate array chips. In addition, IRIS is an open-source generic solution that can be adapted to multiple architectures and includes a crypto-core called E-LUKS that can be used outside the boot-loading process to add confidentiality, integrity, and authenticity to data stored on off-chip storage like a flash device.IRIS shows a reduction in lookup tables footprint when compared to other IoT solutions consuming from 90% to 750% less resources and only slightly greater, around 30%, with solutions that only cover authentication and integrity.

Turbo encoder and decoder chip design and FPGA device analysis for communication system

<p>Turbo codes are error-correcting codes with performance that is close to the Shannon theoretical limit (SHA). The motivation for using turbo codes is that the codes are an appealing mix of a random appearance on the channel and a physically realizable decoding structure. The communication systems have the problem of latency, fast switching, and reliable data transfer. The objective of the research paper is to design and turbo encoder and decoder hardware chip and analyze its performance. Two convolutional codes are concatenated concurrently and detached by an interleaver or permuter in the turbo encoder. The expected data from the channel is interpreted iteratively using the two related decoders. The soft (probabilistic) data about an individual bit of the decoded structure is passed in each cycle from one elementary decoder to the next, and this information is updated regularly. The performance of the chip is also verified using the maximum a posteriori (MAP) method in the decoder chip. The performance of field-programmable gate array (FPGA) hardware is evaluated using hardware and timing parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers a better global rate for the same component code performance, and reduced delay, low hardware complexity, and higher frequency support.</p>

Accurate Multi-Channel QCM Sensor Measurement Enabled by FPGA-Based Embedded System Using GPS

This paper presents a design and implementation proposal for a real-time frequency measurement system for high-precision, multi-channel quartz crystal microbalance (QCM) sensors using a field programmable gate array (FPGA). The key contribution of this work lies in the integration of a frequency measurement and mass resolution computation based on Global Positioning System (GPS) signals within a single FPGA chip, utilizing Input/Output Blocks to incorporate logic QCM oscillator circuits. The FPGA design enables parallel processing, ensuring accurate measurements, faster calculations, and reduced hardware complexity by minimizing the need for external components. As a result, a cost-effective and accurate multi-channel sensor system is developed, serving as a reconfigurable standalone measurement platform with communication capabilities. The system is implemented and tested using the FPGA Xilinx Virtex-6, along with multiple QCM sensors. The implementation on a Xilinx XC6VLX240T FPGA achieves a maximum frequency of 324 MHz and consumes a dynamic power of 120 mW. Notably, the design utilizes a modest number of resources, requiring only 188 slices, 733 flip-flops, and 13 IOBs to perform a double-channel sensor microbalance. The proposed system meets the precision measurement requirements for QCM sensor applications, exhibiting low measurement error when monitoring QCM frequencies ranging from 1 to 50 MHz, with an accuracy of 0.2 ppm and less than 0.1 Hz.

Design and implementation of 1553B module communication system based on FPGA

This thesis introduces the design and implementation method of 1553B module communication system based on Field Programmable Gate Array (FPGA). The configuration and data communication of parallel and multi-channel 1553B module are realized by combining pipeline technology and table lookup method on FPGA chip, and the communication of 1553B module is verified by logic analyzer.

Research on the Deployment Strategy of Big Data Visualization Platform by the Internet of Things Technology

INTRODUCTION: To improve the big data visualization platform's performance and task scheduling capability, a big data visualization platform is constructed based on Field Programmable Gate Array (FPGA) chip application power equipment.OBJECTIVES: This study proposes to combine a genetic algorithm and an ant colony scheduling (ACOS) algorithm to design a big data visualization platform deployment strategy based on an improved ACOS algorithm.METHODS: Firstly, big data technology is analyzed. Then, the basic theory of the ant colony algorithm is studied. According to the basic theory of ACOS and genetic algorithm, an improved ACOS algorithm model is constructed. The improved ACOS algorithm scheduler is compared with the other three schedulers. Under the same environment, the completion time of scheduling the same job and different task amounts are analyzed. The Central Processing Unit (CPU) utilization is analyzed when different schedulers have entirely different workloads. RESULTS: The results show that the constructed big data visualization platform based on the improved ACOS algorithm model has higher task scheduling efficiency than other schedulers and can greatly shorten the data processing time. The experimental results show that under the homogeneous cluster, the completion time of the improved ACOS algorithm generally lags the capacity scheduler and the fair scheduler. Under the heterogeneous cluster, the improved ACOS algorithm scheduler can reasonably allocate tasks to nodes with different performances, reducing the task completion time. When the number of completed tasks increases from 50 to 200, the time increases by 45s, and the completion time is shorter than other schedulers. The CPU utilization of different task volumes is the highest, and the utilization rate increases from 81% to 95%. CONCLUSION: The improved ACOS algorithm scheduler has the shortest data processing time and the highest efficiency. This work provides a specific reference value for optimizing the big data visualization platform's deployment strategy and improving the platform's performance.

Scalable serial hardware architecture of multilayer perceptron neural network for automatic wheezing detection

This paper proposes a serial hardware architecture of a multilayer perceptron (MLP) neural network for real-time wheezing detection in respiratory sounds. As an established classification tool, the MLP has proven its ability to identify complex patterns within respiratory sounds. The proposed fully serial architecture uses a single calculation unit, independently of the number of neurons in the MLP network. It is also a fully scalable architecture that permits to implement MLP networks, of any size, easily and efficiently without modifying the design or wiring. The proposed serial architecture has been implemented on a low-cost and power-efficient field programmable gate array (FPGA) chip using a high-level programming tool. The respiratory sounds classification rates are evaluated in terms of sensitivity, specificity, performance, and accuracy. The proposed serial architecture reaches the same classification performances as the parallel one, but it presents the main advantage of using much fewer hardware resources.

Unequal Duty-Ratio Feedforward Control to Extend Balanced-Currents Input Voltage Range for Series-Capacitor-Based Boost PFC Converter

In this letter, the series-capacitor-based boost power factor correction (PFC) converter (or called the voltage doubler PFC converter) is studied. It possesses the voltage doubler and intrinsic current balancing characteristics only when their equal duty ratios are larger than 0.5. Thus, for PFC application, the balanced-currents input voltage should be smaller than the quarter (1/4) output dc voltage. To extend the balanced-currents input voltage range, the unequal duty-ratio feedforward control is proposed in this letter. For the case of dc output voltage 400 V, the maximum input voltage with balanced inductor currents increased from 100 V (the quarter output dc voltage) to 200 V. The proposed control method is implemented in the field programmable gate array chip to evaluate its performance.

A microsystem design for controlling a DC motor by pulse width modulation using MicroBlaze soft-core

This paper proposes a microsystem based on the field programmable gate arrays (FPGA) electronic board. The preliminary objective is to manipulate a programming language to achieve a control part capable of controlling the speed of electric actuators, such as direct current (DC) motors. The method proposed in this work is to control the speed of the DC motor by a purely embedded architecture within the FPGA in order to reduce the space occupied by the circuit to a minimum and to ensure the reliability of the system. The implementation of this system allows the embedded MicroBlaze processor to be installed side by side with its memory blocks provided by Xilinx very high-speed integrated circuit (VHSIC) hardware description language (VHDL), Embedded C. The control signal of digital pulse-width modulation pulses is generated by an embedded block managed by the same processor. This potential application is demonstrated by experimental simulation on the Vertix5 FPGA chip.

FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology

Field-programmable gate array (FPGA) bitstream reverse engineering and counterfeiting is a pertinent challenge in the modern hardware supply chain. To this end, this article proposes a blockchain-based technology to foster authenticity and integrity of the FPGA supply chain for trustworthy traceability. The proposed approach is transformative in being able to detect counterfeit FPGA chips and bitstreams using state-of-the-art blockchain technologies.—Kanad Basu, The University of Texas at Dallas