FPGA Research Articles

Design and FPGA Implementation of a Hyper-Chaotic System for Real-time Secure Image Transmission

Recently, chaos theory has been widely used in multimedia and digital communications due to its unique properties that can enhance security, data compression, and signal processing. It plays a significant role in securing digital images and protecting sensitive visual information from unauthorized access, tampering, and interception. In this regard, chaotic signals are used in image encryption to empower the security; that's because chaotic systems are characterized by their sensitivity to initial conditions, and their unpredictable and seemingly random behavior. In particular, hyper-chaotic systems involve multiple chaotic systems interacting with each other. These systems can introduce more randomness and complexity, leading to stronger encryption techniques. In this paper, Hyper-chaotic Lorenz system is considered to design robust image encryption/ decryption system based on master-slave synchronization. Firstly, the rich dynamic characteristics of this system is studied using analytical and numerical nonlinear analysis tools. Next, the image secure system has been implemented through Field-Programmable Gate Arrays (FPGAs) Zedboard Zynq xc7z020-1clg484 to verify the image encryption/decryption directly on programmable hardware Kit. Numerical simulations, hardware implementation, and cryptanalysis tools are conducted to validate the effectiveness and robustness of the proposed system.

FPGA Realization of an Image Encryption System Using a 16-CPSK Modulation Technique

Nowadays, M-Quadrature Amplitude Modulation (M-QAM) techniques are widely used to modulate information by bit packets due to their ability to increase transfer rates. These techniques require more power when increasing the modulation index M to avoid interference between symbols. This article proposes a technique that does not suffer from interference between symbols, but instead uses memory elements to store the modulation symbols. In addition, the aim of this paper is to implement a four-dimensional reconfigurable chaotic oscillator that generates 16-Chaotic Phase Shift Keying (16-CPSK) modulation–demodulation carriers. An encryption and modulation transmitter module, a reception module, and a master–slave Hamiltonian synchronization module make up the system. A 16-CPSK modulation scheme implemented in Field Programmable Gate Array (FPGA) and applied to a red-green-blue (RGB) and grayscale image encryption system are the main contributions of this work. Matlab and Vivado were used to verify the modulation–demodulation scheme and synchronization. This proposal achieved excellent correlation coefficients according to various investigations, the lowest being −15.9×10−6 and 0.13×10−3 for RGB and grayscale format images, respectively. The FPGA implementation of the 16-CPSK modulation–demodulation system was carried out using a manufacturer’s card, Xilinx’s Artix-7 AC701 (XC7A200TFBG676-2).

Developing a Cloud and IoT-Integrated Remote Laboratory to Enhance Education 4.0: An Approach for FPGA-Based Motor Control

Remote laboratories are essential in addressing access and quality challenges in technical education. They enable students from various locations to engage with real equipment, overcome geographic and economic constraints, and provide solutions during crises, such as pandemics, when in-person learning is limited. As a key element of Education 4.0, remote labs promote technical skill development, enhance engineering education, and support diverse learning approaches. This study presents a remote laboratory based on Field Programmable Gate Arrays (FPGAs), developed using a waterfall methodology integrating IoT and Cloud Computing technologies to facilitate close interaction between hardware and software. The lab focuses on controlling DC, servo, and stepper motors, allowing students to apply theoretical concepts such as digital signals, pulse-width modulation (PWM), and data representation in bits in a practical setting. The testing phase involved 50 robotics and mechatronics engineering students who participated in hands-on sessions for one month, followed by a structured survey evaluating their experience, interaction, and the educational relevance of the platform. The survey shows high student satisfaction, highlighting the platform’s strengths and identifying areas for improvement. The results also underscore the system’s potential to significantly enhance the educational experience in remote environments, aligning with the United Nations Sustainable Development Goals (SDGs).

A Field-Programmable Gate Array-Based Adaptive Sleep Posture Analysis Accelerator for Real-Time Monitoring

This research presents a sleep posture monitoring system designed to assist the elderly and patient attendees. Monitoring sleep posture in real time is challenging, and this approach introduces hardware-based edge computation methods. Initially, we detected the postures using minimally optimized sensing modules and fusion techniques. This was achieved based on subject (human) data at standard and adaptive levels using posture-learning processing elements (PEs). Intermittent posture evaluation was performed with respect to static and adaptive PEs. The final stage was accomplished using the learned subject posture data versus the real-time posture data using posture classification. An FPGA-based Hierarchical Binary Classifier (HBC) algorithm was developed to learn and evaluate sleep posture in real time. The IoT and display devices were used to communicate the monitored posture to attendant/support services. Posture learning and analysis were developed using customized, reconfigurable VLSI architectures for sensor fusion, control, and communication modules in static and adaptive scenarios. The proposed algorithms were coded in Verilog HDL, simulated, and synthesized using VIVADO 2017.3. A Zed Board-based field-programmable gate array (FPGA) Xilinx board was used for experimental validation.

Accelerating data acquisition with FPGA-based Edge Machine Learning: a case study with LCLS-II

Abstract New scientific experiments and instruments generate vast amounts of data that need to be transferred for storage or further processing, often overwhelming traditional systems. Edge Machine Learning (EdgeML) addresses this challenge by integrating
Machine Learning (ML) algorithms with edge computing, enabling real-time data processing directly at the point of data generation. EdgeML is particularly beneficial for environments where immediate decisions are required, or where bandwidth and
storage are limited. In this paper, we demonstrate a high-speed configurable ML model in a fully customizable EdgeML system using a Field Programmable Gate Array (FPGA). Our demonstration focuses on an angular array of electron spectrometers,
referred to as the ’CookieBox,’ developed for the Linac Coherent Light Source II (LCLS-II) project. The EdgeML system captures 51.2 Gbps from a 6.4 GS/s analog to digital converter and is designed to integrate data pre-processing and ML inside an
FPGA. Our implementation achieves an inference latency of 0.2 μs for the ML model, and a total latency of 0.4 μs for the complete EdgeML system, which includes preprocessing, data transmission, digitization, and ML inference. The modular design of
the system allows it to be adapted for other instrumentation applications requiring low-latency data processing.

Machine learning and FPGA implementation for predicting luminance decay and temperature distribution in micro-LED displays

AbstractA machine learning-based method predicts the luminance decay of micro light emitting diode (micro-LED) displays, utilizing temperature distribution and degradation experiments alongside implementation on field-programmable gate array (FPGA). Micro-LEDs, used in outdoor and indoor billboards, experience degradation due to harsh environmental conditions. To model temperature distribution in indoor advertising displays using minimal data, a temperature model is constructed based on sensor from the panel and thermal images captured by a camera, in relation to the display pattern. The input data is processed using an FPGA, which transmits the sensed temperatures and display patterns to the micro-LED panel. Multilayer Perceptron (MLP), a type of neural network, predicts the temperature distribution over the panel surface, achieving an error of less than 1.1 °C. Separate degradation models forecast luminance decay, factoring in enclosure temperature, input current, and usage time, with distinct models for red, green, and blue LEDs. Exponential curve-fitting and interpolation, following TM-21 standards, ensure long-term accuracy. The luminance decay predictions have an average error below 1.05% (approximately 9 nits). The FPGA implementation minimizes resource consumption while maintaining prediction accuracy, making it suitable for real-time applications. The degradation model accurately predicts performance over tens or even hundreds of thousands of hours, aligning with the exponential decay trends defined by TM-21.

Moving objects detection based on histogram of oriented gradient algorithm chip for hazy environment

<span>The most important aspects of computer vision are moving object detection (MOD) and tracking. Many signal-processing applications use regional image statistics. Compute-intensive video and image processing with low latency and high throughput is done with field programmable gate array (FPGA) image processing. Local image statistics are used for edge identification and filtering. The histogram of oriented gradients (HoG) algorithm extracts local shape characteristics by equalizing histograms. The objective of the work is to design the hardware chip of the algorithm and perform the simulation in the Xilinx ISE 14.7 simulation environment. The performance of the chip is evaluated in Modelsim 10.0 simulation software to check its feasibility. The performance of the chip design is estimated on Viretx-5 FPGA and compared with the MATLAB-2020 image processing tool-based response time. This form of tracking typically deals with identifying, anchoring, and tracking images and videos. A mask made from a cut-out of the object can then determine the plane's coordinates depending on its position. This type of object tracking is frequently utilized in the field of augmented reality (AR). The algorithm is most suited for object detection using hardware controllers in haze and foggy environments.</span>

Timing issues on power side-channel leakage of advanced encryption standard circuits designed by high-level synthesis

In recent years, field programmable gate array (FPGA) have been used in many internet of things (IoT) devices and are equipped with cryptographic circuits to ensure security. However, they are exposed to the risk of cryptographic keys being stolen by side-channel attacks. Countermeasures against side-channel attacks have been developed, but they are becoming more of a threat to IoT devices due to the diversity of attacks. Therefore, it is necessary to understand the basic characteristics of side-channel attacks. Therefore, this study clarifies the relationship between two timing issues, the clock period of the circuit and the power sampling interval, and the amount of side-channel leakage. We design seven advanced encryption standard (AES) circuits with different clock periods and conduct empirical experiments using logic simulations to clarify the correlation between the two timings and the amount of side-channel leakage. T-test is used to evaluate the leakage amount, which is evaluated based on four metrics. From the results, we argue that the clock period and sampling interval do not interfere with each other in the side-channel leakage amount.

Real-time fully digital control scheme for pulse coherent beam combining.

A fully digital control scheme for non-polarization-maintaining (non-PM) nanosecond pulse coherent beam combining (CBC) is proposed, where digital locking of optical coherence by single-detector electronic-frequency tagging (LOCSET) for active phase control and stochastic parallel gradient descent (SPGD) for active polarization control is proposed. The fully digital control scheme is integrated on a real-time field-programmable gate array (FPGA) empowered hardware platform and then experimentally validated in a four-channel all-fiber non-fully polarization-maintaining nanosecond pulse CBC system. Consequently, the system can be fully locked in 9.5 ms, and the polarization extinction ratio (PER) of the combined beam is 21.5 dB with a CBC efficiency of 95.3%. The fully digital control scheme integrates the advantages of digital LOCSET and multi-channel active polarization control, enhancing the channel scalability and the potential output power of the non-PM pulse CBC system.

Enhancing IoT data acquisition efficiency via FPGA-based implementation with OpenCL framework

The increasing demand for real-time data processing in Internet of Things (IoT) applications necessitates the development of efficient and flexible data acquisition systems capable of receiving and processing data from various sensor types. In conjunction with OpenCL, field-programmable gate arrays (FPGAs) have recently emerged as powerful platforms for accelerating data-intensive tasks. This study explored the implementation of an FPGA for data acquisition using OpenCL, aiming to design and implement an efficient data acquisition system tailored for IoT applications. Utilizing OpenCL for FPGA-based data acquisition offers several advantages that contribute to system efficiency, particularly in hardware interfaces between FPGA and external devices used in IoT applications. OpenCL abstracts the complexity of the FPGA hardware interface to external DDR memory for storing temporary data and a communication interface to the host CPU for transferring the collected data and enabling remote access, enabling developers to focus on algorithm design and functionality. To enable data reading from an external analog-to-digital converter (ADC) chip for IoT applications, we developed a component module that utilizes the Avalon-streaming interface and can stream the data to the OpenCL kernel. An experiment was conducted to demonstrate the performance of our proposed design. According to the findings of the experiments, a data acquisition implementation based on an FPGA and OpenCL can simultaneously read analog signals via a multichannel ADC. The proposed design provides a foundation for designing efficient data acquisition solutions, addressing the increasing needs of FPGA-based data acquisition in various IoT environments.

Automatic control strategy of electronic and electrical engineering based on FPGA

Field Programmable Gate Array (FPGA) have demonstrated significant potential in the field of automation control due to their flexibility, programmability, and high performance. This study designs an FPGA-based automation control strategy for motor control systems, encompassing four core modules: signal acquisition, signal processing, control algorithm, and output drive. The signal acquisition module employs the AD9280 high-speed, high-precision ADC chip to achieve rapid and accurate signal acquisition. The signal processing module utilizes digital filtering and FFT analysis within the FPGA to extract key information such as motor speed. The control algorithm module adopts an adaptive fuzzy control strategy that fine-tunes control rules in real-time to ensure precise control. The output drive module generates PWM signals via the FPGA to drive the motor, guaranteeing efficient and stable operation. Experimental results indicate that the FPGA-based control strategy significantly outperforms traditional methods in terms of response speed and stability, capable of meeting the high-performance requirements of modern industrial motor control systems. This research provides new technical insights and practical references for the field of automation control in electrical and electronic engineering.

An Innovative Honeypot Architecture for Detecting and Mitigating Hardware Trojans in IoT Devices

The exponential growth and widespread adoption of Internet of Things (IoT) devices have introduced many vulnerabilities. Attackers frequently exploit these flaws, necessitating advanced technological approaches to protect against emerging cyber threats. This paper introduces a novel approach utilizing hardware honeypots as an additional defensive layer against hardware vulnerabilities, particularly hardware Trojans (HTs). HTs pose significant risks to the security of modern integrated circuits (ICs), potentially causing operational failures, denial of service, or data leakage through intentional modifications. The proposed system was implemented on a Raspberry Pi and tested on an emulated HT circuit using a Field-Programmable Gate Array (FPGA). This approach leverages hardware honeypots to detect and mitigate HTs in the IoT devices. The results demonstrate that the system effectively detects and mitigates HTs without imposing additional complexity on the IoT devices. The Trojan-agnostic solution offers full customization to meet specific security needs, providing a flexible and robust layer of security. These findings provide valuable insights into enhancing the security of IoT devices against hardware-based cyber threats, thereby contributing to the overall resilience of IoT networks. This innovative approach offers a promising solution to address the growing security challenges in IoT environments.

Optimizing Security and Cost Efficiency in N-Level Cascaded Chaotic-Based Secure Communication System

In recent years, chaos-based secure communication systems have garnered significant attention for their unique attributes, including sensitivity to initial conditions and periodic orbit density. However, existing systems face challenges in balancing encryption strength with practical implementation, especially for multiple levels. This paper addresses this gap by introducing a novel N-level cascaded chaotic-based secure communication system for voice encryption, leveraging the four-dimensional unified hyperchaotic system. Performance evaluation is conducted using various security metrics, including Signal-to-Noise Ratio (SNR), Peak Signal-to-Noise Ratio (PSNR), Percent Residual Deviation (PRD), and correlation coefficient, as well as Field-Programmable Gate Array (FPGA) resource metrics. A new Value-Based Performance Metrics (VBPM) framework is also introduced, focusing on both security and efficiency. Simulation results reveal that the system achieves optimal performance at N = 4 levels, demonstrating significant improvements in both security and FPGA resource utilization compared to existing approaches. This research offers a scalable and cost-efficient solution for secure communication systems, with broader implications for real-time encryption in practical applications.

Adaptive FPGA-Based Accelerators for Human–Robot Interaction in Indoor Environments

This study addresses the challenges of human–robot interactions in real-time environments with adaptive field-programmable gate array (FPGA)-based accelerators. Predicting human posture in indoor environments in confined areas is a significant challenge for service robots. The proposed approach works on two levels: the estimation of human location and the robot’s intention to serve based on the human’s location at static and adaptive positions. This paper presents three methodologies to address these challenges: binary classification to analyze static and adaptive postures for human localization in indoor environments using the sensor fusion method, adaptive Simultaneous Localization and Mapping (SLAM) for the robot to deliver the task, and human–robot implicit communication. VLSI hardware schemes are developed for the proposed method. Initially, the control unit processes real-time sensor data through PIR sensors and multiple ultrasonic sensors to analyze the human posture. Subsequently, static and adaptive human posture data are communicated to the robot via Wi-Fi. Finally, the robot performs services for humans using an adaptive SLAM-based triangulation navigation method. The experimental validation was conducted in a hospital environment. The proposed algorithms were coded in Verilog HDL, simulated, and synthesized using VIVADO 2017.3. A Zed-board-based FPGA Xilinx board was used for experimental validation.

Emerging Technologies and Applications of AI Chips: Integrating Deep Learning Algorithms with Advanced Hardware Architectures

Due to the ongoing promotion of the latest technological revolution and industrial upgrading, as well as the widespread use of artificial intelligence and deep learning, the intelligent Internet of Things terminal has reached a more advanced stage of development. The combination of training data, model algorithms, and processing power is the basis for advancing artificial intelligence. The semiconductor business plays a crucial role in shaping the future of AI algorithms and the computing power industry. This study explores the progression of artificial intelligence, and essential technologies, and examines the categorization and structure of AI chips. The process of deep learning was then analyzed, demonstrating the application of AI in real life. Next, this study showcases distinct AI chip-related models, specifically designed for the automated implementation of Convolutional Neural Networks (CNNs) on Field-Programmable Gate Arrays (FPGAs). The study then proceeds to examine the unique procedure and the significance of the resulting data. The future of AI was examined in the domains of space exploration, healthcare, and autonomous driving, along with future forecasts.

Construction and analysis of symmetric Sprott B multi-attractors with electric implementation

Abstract In chaos theory, a number of systems and models which apparently contain simple ordinary differential equations (ODEs) turn out to show a dynamic characterized by complicated behaviors and complex trajectories. One of such systems is the Sprott B model. We construct some set of multi-attractors based on the Sprott B model where additional parameters and operators are considered. After summarizing important preliminaries relevant to simple chaotic differential systems, the model is firstly solved analytically and numerically, then graphical simulations are provided. The later show coexistence and evolution of two chaotic attractors in a symmetrical representation. Lastly, similar results and expected outcomes are recovered via an electrical circuit implementation, realized using the Field Programmable Gate Array (FPGA) board, the Digital-to-Analog Converter (DAC) and the Rigol Oscilloscope. They also show progressing sets of coexisting multi-attractors.

Research on Phase Stabilization Algorithm of Femtosecond Timing System

This paper presents the design, implementation, and validation of a femtosecond timing system aimed at achieving precise time control and phase synchronization for large particle accelerators. A prototype system utilizing a continuous wave laser was developed, focusing on minimizing timing jitter and long-term phase drift. Key components include an optical delay line for coarse adjustments and a fiber stretcher for fine-tuning, achieving an adjustment precision of 1 femtosecond. The system incorporates a phase detection module with a non-In-phase/Quadrature downconversion approach, enabling high-accuracy phase measurements. A collaborative algorithm was designed to optimize the interplay between the optical delay line and the fiber stretcher, utilizing a proportional-integral-derivative (PID) control algorithm to enhance adjustment precision. A Field Programmable Gate Array (FPGA) served as the core interface converter, facilitating data communication and real-time phase information acquisition. Experimental results demonstrated significant improvements in phase stability, with average phase deviation reduced from 1374.104 fs to 15.782 fs, showcasing the effectiveness of the proposed system in achieving high precision and stability in phase control. This research provides a solid foundation for future advancements in timing systems for high-frequency reference signals.

Implementation of Robust and Secure Watermarking Algorithm on FPGA using DCT

Digital watermarking deals with embedding digital content in a cover signal so that it becomes indiscernible to make it robust against different security threats. This work demonstrates the implementation of a robust and secure watermarking technique on a Field Programmable Gate Array (FPGA) using Discrete Cosine Transform (DCT). Block by block DCT of the cover image was computed and watermark pixels in each of the blocks were hidden using middle-frequency band coefficients. Security is ensured by encrypting the watermarkwith a secret key and Arnold transform. The resultant watermark image is robust to various threats like JPEG compression, scaling, cropping, and noise attacks. This watermarking approach requires a large amount of data to be processed at high speed. FPGA is the best choice for such an application. Also, it is reprogrammable and easily upgradable according to user application. In this work, a watermarking algorithm is implemented using Xilinx design tools on the Artix-7 FPGA board.

Dynamic Analysis and FPGA Implementation of Fractional-Order Hopfield Networks with Memristive Synapse

Memristors have become important components in artificial synapses due to their ability to emulate the information transmission and memory functions of biological synapses. Unlike their biological counterparts, which adjust synaptic weights, memristor-based artificial synapses operate by altering conductance or resistance, making them useful for enhancing the processing capacity and storage capabilities of neural networks. When integrated into systems like Hopfield neural networks, memristors enable the study of complex dynamic behaviors, such as chaos and multistability. Moreover, fractional calculus is significant for their ability to model memory effects, enabling more accurate simulations of complex systems. Fractional-order Hopfield networks, in particular, exhibit chaotic and multistable behaviors not found in integer-order models. By combining memristors with fractional-order Hopfield neural networks, these systems offer the possibility of investigating different dynamic phenomena in artificial neural networks. This study investigates the dynamical behavior of a fractional-order Hopfield neural network (HNN) incorporating a memristor with a piecewise segment function in one of its synapses, highlighting the impact of fractional-order derivatives and memristive synapses on the stability, robustness, and dynamic complexity of the system. Using a network of four neurons as a case study, it is demonstrated that the memristive fractional-order HNN exhibits multistability, coexisting chaotic attractors, and coexisting limit cycles. Through spectral entropy analysis, the regions in the initial condition space that display varying degrees of complexity are mapped, highlighting those areas where the chaotic series approach a pseudo-random sequence of numbers. Finally, the proposed fractional-order memristive HNN is implemented on a Field-Programmable Gate Array (FPGA), demonstrating the feasibility of real-time hardware realization.

An Ultrawide Bandwidth Digital Backend System Based on PFB Algorithm for QTT

For the planning of the QiTai radio Telescope ultrawide bandwidth low-frequency pulsar receiving system, we designed and implemented a Field-Programmable Gate Array (FPGA)+CPU/GPU hybrid architecture digital backend system based on the Polyphase FilterBank (PFB) channeling algorithm. We used the FPGA signal acquisition and processing platform to implement ultrawide bandwidth signal sampling and designed the PFB algorithm to realize the digital channelization of multiple analog bandwidth signals. We also developed data encapsulation and multichannel parallel distribution firmware algorithms and realized the real-time parallel transmission of high-speed astronomical data streams based on the VLBI Data Interchange Format. We developed the Ultra Wide bandwidth Low-frequency pulsar data process PIPEline, which realized the real-time processing and data packaging of massive pulsar signals. Using the L-band (964–1732 MHz bandwidth) receiving system of the Nanshan 26 m radio telescope, we conducted a systematic test on the designed digital backend system and obtained high-quality observation data. By using the professional pulsar data processing software DSPSR to process the observation data, we obtained high signal-to-noise ratio pulse profiles.