FPGA Research Articles

Design of mean filter using field programmable gate arrays for digital images

In this paper, we design and analysis of mean filter using field programmable gate arrays (FPGAs) for digital images, FPGAs are integrated circuits consisting of interconnections that connect programmable internal hardware blocks allows users to customize operations for a specific application. FPGA is an ideal choice for real-time image processing, these FPGA devices are controlled in Verilog or VHDL languages, allowing to design at different levels and adapt to design changes or even support new applications throughout the life of the component. Digital image filtering is the most important task in image processing and with the help of computers, image recognition involves identifying and classifying objects in an image. This paper design of mean filter for digital image processing, implementation and analysis of image processing algorithms on FPGAs. The results obtained on the FPGA are compared and analyzed with the results by MATLAB software.

Design and implementation of deep neural network hardware chip and its performance analysis

The artificial neural network (ANN) with a single layer has a limited capacity to process data. Multiple neurons are connected in the human brain, and the actual capacity of the brain lies in the interconnectedness of multiple neurons. As a specified generalization of ANN deep learning makes use of two or more hidden layers, which implies that a greater number of neurons are required to construct the model. A network that has more than one hidden layer, also known as two or more hidden layers, is referred to as a deep neural network, and the process of training such networks is referred to as deep learning. The research article focuses on the design of a multilayer or deep neural network presented for the target field programmable gate array (FPGA) device spartan-6 (xc6stx4-2t9g144) FPGA. The simulation is carried out using Xilinx ISE and ModelSim software. There are two hidden layers in which (2×1) multiplexer blocks are utilized for processing twenty neurons into the output of ten neurons in the first hidden layer and demultiplexers (1×2) and vice versa. The hardware utilization is estimated on FPGA to compute the performance of the deep neural hardware chip based on memory, flip flops, delay, and frequency parameters. The design is scalable and applicable to various FPGA devices, which makes the work novel. FPGA-based neuromorphic hardware acceleration platform with high speed and low power for discrete spike processing on hardware with great real-time performance.

Low power computation of transoceanic wave propagation for tsunami hazard mitigation

This paper proposes the use of specialized hardware accelerator based on the Field Programmable Gates Array (FPGA) microchip to compute tsunami wave propagation to assess and manage risks of marine natural disasters, namely, tsunami waves caused by underwater earthquakes. After a sufficiently strong seismic event, many countries and research centres launch extensive computations to estimate the tsunami wave parameters in certain parts of the coast to determine if a declaration of a tsunami alarm is warranted. This requires high computating powers which leads to higher energy costs. The paper demonstrates how an FPGA–based special Calculator (architecture of which has been earlier proposed by the authors), installed on a Personal Computer (PC) could be used to calculate the propagation of a tsunami wave over the entire Pacific Ocean, from the subduction zone offshore Kamchatka Peninsula and Kuril Islands to the coast of Chile. Such calculations offer reliable results within a few minutes and make it possible to obtain the distribution of expected tsunami wave heights along the coast. If the obtained results indicate a danger to the population or possible distruction of infrastructure, it becomes paramount to carry out more detailed calculations to accurately estimate the wave parameters at specific locations along the coast where negative consequences are expected. This requires cluster and/or supercomputer systems, which consume significant energy and hence are expensive. In case the modelling results indicate small values of maximum wave heights at populated coastal areas, population of the near–shore regions can be immediately informed about low amplitude tsunami wave; more detailed studies are not needed. This hence leads to noticeable savings in energy consumption. The paper presents a calculation of the propagation of a tsunami wave across the Pacific Ocean on a personal computer using a FPGA–based hardware acceleration of a computer code execution.

Analysis of single layer artificial neural network neuromorphic hardware chip

The neuromorphic architectures are hardware network systems designed with neural functions. Neural networks seen in biology serve as an inspiration for network systems. A synapse connects every node or neuron in an artificial neural network (ANN) to every other node. As in biological brains, the amplitude of the linking between nodes referred to as synaptic weights will regulate the connection. In contrast to conventional design, ANN uses many highly organized dealing pieces that work together to solve real-world issues. The design of the neuromorphic hardware chip is discussed in the paper. The target device used is a Virtex-5 Field Programmable Gate Array (FPGA) and the simulation is taken on Xilinx ModelSim software. This chip is designed for 20 neuron inputs, each of the neuron inputs is 8-bit. Each 20-neuron input is multiplied by 20 input weights and each weight is 8-bit so when these 20 input weights are multiplied by 20 neuron inputs in the multiplier it gives 16-bit output. A control logic is used in this neuromorphic hardware chip design which is used to feed multiplier output to each input of the hidden layer. The system-level outcome of the hidden layer is then given to the multiplexer which has 20 inputs and one single output. The multiplexer is used to select any of the 20 outputs of the control logic. Finally, to gain an understanding of the performance of this neuromorphic hardware chip, we have computed the hardware utilization parameters. These parameters include slices, input/output blocks (IOBs), registers used, memory, and the overall propagation delay used by the hardware chip.

Nonvolatile silicon photonic MEMS switch based on centrally clamped stepped bistable mechanical beams

High-performance photonic switches are essential for large-scale optical routing for AI large models and the Internet of Things. Realizing nonvolatility can further reduce power consumption and expand application scenarios. We propose a nonvolatile 2×2 silicon photonic micro-electromechanical system (MEMS) switch compatible with standard silicon photonic foundry processes. The switch employs an electrostatic comb actuator to change the air gap of the compact horizontal adiabatic coupler and achieves nonvolatility with centrally clamped stepped bistable mechanical beams. The photonic switch features a 10s μs-scale switching speed and a 10s fJ-scale simulated switching energy within a 100 μm×100 μm footprint, with ≤12 V driving voltages. This 2×2 switch can be used in a variety of topologies for large-scale photonic switches, and its nonvolatility can potentially support future photonic field programmable gate array designs.

SIMTAM: Generation Diversity Test Programs for FPGA Simulation Tools Testing Via Timing Area Mutation

Field-Programmable Gate Array (FPGA) timing simulation is essential in electronic circuit design, allowing for the verification of timing characteristics like delays and clock frequencies. However, bugs in timing simulation tools can lead to inaccurate results, potentially causing designers to miss critical issues in chip performance. Traditional testing methods often fall short in thoroughly assessing these tools, as current FPGA testing primarily focuses on synthesis and behavioral simulation, neglecting timing aspects. To address this issue, we propose SIMTAM for testing timing simulation tools. Specifically, SIMTAM consists of three components: equivalent delay region construction, diversity program segment generation, and differential testing. Given a seed circuit design file written by hardware description language such as Verilog, the delay region construction component randomly identifies delay structures for inertial delay in the design file to construct equivalent delay sleep regions. In the sleep region, the simulator skips the signal pulse whose width is less than the specified delay, thus ensuring the equivalence of the variations. The diversity program segment generation component combines Verilog expressions using generation operators and inject them into the sleep region to generate diverse design files. The differential testing component compares the seed and variant design files to find compilation inconsistency issues. In five months, SIMTAM reported 16 bugs to developers in two popular timing simulation tools Iverilog and Vivado; ten of which are confirmed.

Lightweight, Post-Quantum Secure Cryptography Based on Ascon: Hardware Implementation in Automotive Applications

With the rapid growth of connected vehicles and the vulnerability of embedded systems against cyber attacks in an era where quantum computers are becoming a reality, post-quantum cryptography (PQC) is a crucial solution. Yet, by nature, automotive sensors are limited in power, processing capability, memory in implementing secure measures. This study presents a pioneering approach to securing automotive systems against post-quantum threats by integrating the Ascon cipher suite—a lightweight cryptographic protocol—into embedded automotive environments. By combining Ascon with the Controller Area Network (CAN) protocol on an Artix-7 Field Programmable Gate Array (FPGA), we achieve low power consumption while ensuring high performance in post-quantum-resistant cryptographic tasks. The Ascon module is designed to optimize computational efficiency through bitwise Boolean operations and logic gates, avoiding resource-intensive look-up tables and achieving superior processing speed. Our hardware design delivers significant speed improvements of 100 times over software implementations and operates effectively within a 100 MHz clock while demonstrating low resource usage. Furthermore, a custom digital signal processing block supports CAN protocol integration, handling message alignment and synchronization to maintain signal integrity under automotive environmental noise. Our work provides a power-efficient, robust cryptographic solution that prepares automotive systems for quantum-era security challenges, emphasizing lightweight cryptography’s readiness for real-world deployment in automotive industries.

Design and Practical Implementation of a Stream Cipher Algorithm Based on a Lorenz System

Currently, the security of data has gained significant attention in modern life. Researchers have continued to address this issue. This work addresses image encryption in communication systems. It presents a proposed design and implementation of a cryptography system based on the Lorenz chaos oscillator. The paper methodology uses Xilinx System Generator (XSG) and Field Programmable Gate Array (FPGA) technologies to implement the chaotic system. To determine the approach that uses the least amount of FPGA resources while providing effective and efficient performance, the differential equations of the Lorenz chaotic system are solved via the forward-Euler and Runge–Kutta integration techniques. In the XSG environment, a secure communication system is constructed on the basis of the solution of the differential equations. After that, the planned communication system is implemented on the FPGA board and tested to encrypt images (coloured images). The histogram, entropy and other related security analysis factors are calculated and analysed to test the efficiency of the designed system. Six statistical methods were employed to provide a high level of image encryption in this work. Findings have shown that the proposed system generates (with stable, fast and robust performance) pseudorandom bits that can be successfully used to encrypt the data bits. The simulation and FPGA results are in good agreement; however, the security analysis factors prove that the system can be successfully adopted for image encryption purposes in real-time applications.

Field‐Programmable Topographic‐Morphing Array for General‐Purpose Lab‐on‐a‐Chip Systems

AbstractLab‐on‐a‐chip systems seek to leverage microfluidic chips to enable small‐scale fluid manipulation, holding significant potential to revolutionize science and industry. However, existing microfluidic chips have been largely designed with static fluid structures for specific single‐purpose applications, which lack adaptability and flexibility for diverse applications. Inspired by the general‐purpose design strategy of the customizable chip of integrated circuit – field programmable gate array whose hardware can be reconfigured via software programming for multifunctionality after manufacturing, a conceptual‐new reconfigurable microfluidic chip — field programmable topographic morphing array (FPTMA) is devised with exceptional structural reconfiguration, field programmability, and function scalability for general‐purpose lab‐on‐a‐chip systems that beyond the reach of current state‐of‐art lab‐on‐chip systems. FPTMA can be software programmed to dynamically shape an elastic meta‐interface from the initial smooth structure into desired time‐varying topographic structures and thus generate spatiotemporal topographic‐morphing‐induced capillary forces to actively manipulate multidroplets in parallel and enable real‐time reconfiguring diverse microfluidic operations/functions/flow networks as well as workflows. It is envisioned that the development of the FPTMA‐driven lab‐on‐a‐chip systems that leverage dynamic interfacial topographies to digitally handle microfluidics would significantly stimulate numerous technological innovations in biology/medicine/chemistry.

FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities

Sparse matrix multiplication (SpMM) plays a critical role in high-performance computing applications, such as deep learning, image processing, and physical simulation. Field-Programmable Gate Arrays (FPGAs), with their configurable hardware resources, can be tailored to accelerate SpMMs. There has been considerable research on deploying sparse matrix multipliers across various FPGA platforms. However, the FPGA-based design of sparse matrix multipliers still presents numerous challenges. Therefore, it is necessary to summarize and organize the current work to provide a reference for further research. This article first introduces the computational method of SpMM and categorizes the different challenges of FPGA deployment. Following this, we introduce and analyze a variety of state-of-the-art FPGA-based accelerators tailored for SpMMs. In addition, a comparative analysis of these accelerators is performed, examining metrics including compression rate, throughput, and resource utilization. Finally, we propose potential research directions and challenges for further study of FPGA-based SpMM accelerators.

Advanced Security Strategies for Software Vulnerability Protection: A Multi-Scale Detection Model With FPGA-RFID

This paper proposes a multi-scale software vulnerability detection model using Radio Frequency Identification (RFID) target recognition technology and Field-Programmable Gate Array (FPGA) hardware design. The systematic analysis of RFID systems and FPGA architectures provides the foundation for constructing robust security solutions against code-based threats. The Scalable Vulnerability Detection Method (SVDM) is developed leveraging multi-scale code metrics and deep feature extraction techniques. The evaluations of vulnerability datasets CWE-119 and CWE-399 demonstrated over 84% accuracy, recall, and F1 score. The precision, recall, and F1 score of the CWE-399 vulnerability dataset in the SVDM were 85.15%, 85.12%, and 84.79%, respectively, while the values of the CWE-199 dataset were 83.12%, 82.16%, and 82.38%, respectively. Compared with existing methods, the functionality of SVDM was further highlighted. This research provides an extensible and adaptable framework for identifying security vulnerabilities with both hardware and software techniques. It can optimize threat detection, risk analysis, and system integrity across software development and operation life cycles, providing technical reference and scientific support for the security protection of software vulnerabilities, while promoting the development of industries such as intelligent monitoring and traceability.

Graph-OPU: A Highly Flexible FPGA-Based Overlay Processor for Graph Neural Networks

Field-programmable gate arrays (FPGAs) are an ideal candidate for accelerating graph neural networks (GNNs). However, the FPGA redeployment process is time-consuming when updating or switching between diverse GNN models across different applications. Existing GNN processors eliminate the need for FPGA redeployment when switching between different GNN models. However, adapting matrix multiplication types by switching processing units decreases hardware utilization. In addition, the bandwidth of DDR limits further improvements in hardware performance. This article proposes a highly flexible FPGA-based overlay processor for GNN accelerations. Graph-OPU provides excellent flexibility and programmability for users, as the executable code of GNN models is automatically compiled and reloaded without requiring FPGA redeployment. First, we customize the compiler and instruction sets for the inference process of different GNN models. Second, we customize the datapath and optimize the data format in the microarchitecture to fully leverage the advantages of high bandwidth memory (HBM). Third, we design a unified matrix multiplication to handle both sparse-dense matrix multiplication (SpMM) and general matrix multiplication (GEMM), enhancing Graph-OPU performance. During Graph-OPU execution, the computational units are shared between SpMM and GEMM instead of being switched, which improves the hardware utilization. Finally, we implement a hardware prototype on the Xilinx Alveo U50 and test the mainstream GNN models using various datasets. Experimental results show that Graph-OPU achieves up to 1,654 \(\times\) and 63 \(\times\) speedup, as well as up to 5,305 \(\times\) and 422 \(\times\) energy efficiency boosts, compared to implementations on CPU and GPU, respectively. Graph-OPU outperforms state-of-the-art (SOTA) end-to-end overlay accelerators for GNN, reducing latency by an average of 1.36 \(\times\) and improving energy efficiency by 1.41 \(\times\) on average. Moreover, Graph-OPU exhibits an average 1.45 \(\times\) speed improvement in end-to-end latency over the SOTA GNN processor. Graph-OPU represents an in-depth study of an FPGA-based overlay processor for GNNs, offering high flexibility, speedup, and energy efficiency.

Protocol-aware approach for mitigating radiation-induced errors in free-space optical downlinks

Multigigabit per second satellite-to-ground communications are evolving owing to free-space optical (FSO) communications. They benefit greatly from the use of commercial off-the-shelf field-programmable gate arrays, which offer higher performance than their space-grade counterparts. However, these capabilities are severely diminished in the case of improper implementation of radiation mitigation schemes not being properly assessed. Although these schemes have been improved over the years, they can be further optimized. Therefore, this study proposes, to our knowledge, a new protocol-aware approach, tailored for FSO satellite downlinks, to classify the criticality of radiation-induced errors. This approach can achieve a reduction in overhead by nearly an order of magnitude compared to current protection schemes.

Towards sustainable AI: a comprehensive framework for Green AI

The rapid advancement of artificial intelligence (AI) has brought significant benefits across various domains, yet it has also led to increased energy consumption and environmental impact. This paper positions Green AI as a crucial direction for future research and development. It proposes a comprehensive framework for understanding, implementing, and advancing sustainable AI practices. We provide an overview of Green AI, highlighting its significance and current state regarding AI’s energy consumption and environmental impact. The paper explores sustainable AI techniques, such as model optimization methods, and the development of efficient algorithms. Additionally, we review energy-efficient hardware alternatives like tensor processing units (TPUs) and field-programmable gate arrays (FPGAs), and discuss strategies for designing and operating energy-efficient data centers. Case studies in natural language processing (NLP) and Computer Vision illustrate successful implementations of Green AI practices. Through these efforts, we aim to balance the performance and resource efficiency of AI technologies, aligning them with global sustainability goals.

Reconfigurable Acceleration of Neural Networks: A Comprehensive Study of FPGA-based Systems

This paper explores the potential of Field-Programmable Gate Arrays (FPGAs) for accelerating both neural network inference and training. We present a comprehensive analysis of FPGA-based systems, encompassing architecture design, hardware implementation strategies, and performance evaluation. Our study highlights the advantages of FPGAs over traditional CPUs and GPUs for neural network workloads, including their inherent parallelism, reconfigurability, and ability to tailor hardware to specific network needs. We delve into various hardware implementation strategies, from direct mapping to dataflow architectures and specialized hardware blocks, examining their impact on performance. Furthermore, we benchmark FPGA-based systems against traditional platforms, evaluating inference speed, energy efficiency, and memory bandwidth. Finally, we explore emerging trends in FPGA-based neural network acceleration, such as specialized architectures, efficient memory management techniques, and hybrid CPU-FPGA systems. Our analysis underscores the significant potential of FPGAs for accelerating deep learning applications, particularly those requiring high performance, low latency, and energy efficiency.

FPGA Readout for Frequency-Multiplexed Array of Micromechanical Resonators for Sub-Terahertz Imaging.

Field programmable gate arrays (FPGAs) have not only enhanced traditional sensing methods, such as pixel detection (CCD and CMOS), but also enabled the development of innovative approaches with significant potential for particle detection. This is particularly relevant in terahertz (THz) ray detection, where microbolometer-based focal plane arrays (FPAs) using microelectromechanical (MEMS) resonators are among the most promising solutions. Designing high-performance, high-pixel-density sensors is challenging without FPGAs, which are crucial for deterministic parallel processing, fast ADC/DAC control, and handling large data throughput. This paper presents a MEMS-resonator detector, fully managed via an FPGA, capable of controlling pixel excitation and tracking resonance-frequency shifts due to radiation using parallel digital lock-in amplifiers. The innovative FPGA architecture, based on a lock-in matrix, enhances the open-loop readout technique by a factor of 32. Measurements were performed on a frequency-multiplexed, 256-pixel sensor designed for imaging applications.

Accelerating data acquisition with FPGA-based edge machine learning: a case study with LCLS-II

Abstract New scientific experiments and instruments generate vast amounts of data that need to be transferred for storage or further processing, often overwhelming traditional systems. Edge Machine Learning (EdgeML) addresses this challenge by integrating
Machine Learning (ML) algorithms with edge computing, enabling real-time data processing directly at the point of data generation. EdgeML is particularly beneficial for environments where immediate decisions are required, or where bandwidth and
storage are limited. In this paper, we demonstrate a high-speed configurable ML model in a fully customizable EdgeML system using a Field Programmable Gate Array (FPGA). Our demonstration focuses on an angular array of electron spectrometers,
referred to as the ’CookieBox,’ developed for the Linac Coherent Light Source II (LCLS-II) project. The EdgeML system captures 51.2 Gbps from a 6.4 GS/s analog to digital converter and is designed to integrate data pre-processing and ML inside an
FPGA. Our implementation achieves an inference latency of 0.2 μs for the ML model, and a total latency of 0.4 μs for the complete EdgeML system, which includes preprocessing, data transmission, digitization, and ML inference. The modular design of
the system allows it to be adapted for other instrumentation applications requiring low-latency data processing.

A Survey on Design Space Exploration Approaches for Approximate Computing Systems

Approximate Computing (AxC) has emerged as a promising paradigm to enhance performance and energy efficiency by allowing a controlled trade-off between accuracy and resource consumption. It is extensively adopted across various abstraction levels, from software to architecture and circuit levels, employing diverse methodologies. The primary objective of AxC is to reduce energy consumption for executing error-resilient applications, accepting controlled and inherently acceptable output quality degradation. However, harnessing AxC poses several challenges, including identifying segments within a design amenable to approximation and selecting suitable AxC techniques to fulfill accuracy and performance criteria. This survey provides a comprehensive review of recent methodologies proposed for performing Design Space Exploration (DSE) to find the most suitable AxC techniques, focusing on both hardware and software implementations. DSE is a crucial design process where system designs are modeled, evaluated, and optimized for various extra-functional system behaviors such as performance, power consumption, energy efficiency, and accuracy. A systematic literature review was conducted to identify papers that ascribe their DSE algorithms, excluding those relying on exhaustive search methods. This survey aims to detail the state-of-the-art DSE methodologies that efficiently select AxC techniques, offering insights into their applicability across different hardware platforms and use-case domains. For this purpose, papers were categorized based on the type of search algorithm used, with Machine Learning (ML) and Evolutionary Algorithms (EAs) being the predominant approaches. Further categorization is based on the target hardware, including Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), general-purpose Central Processing Units (CPUs), and Graphics Processing Units (GPUs). A notable observation was that most studies targeted image processing applications due to their tolerance for accuracy loss. By providing an overview of techniques and methods outlined in existing literature pertaining to the DSE of AxC designs, this survey elucidates the current trends and challenges in optimizing approximate designs.

Charge-coupled device readout by digital-correlated double sampling

Charge-coupled devices (CCDs) play crucial roles in astronomy owing to their widespread use in the optical band, offering high sensibility, low noise, high dynamic range, and high spatial resolution. Recent advancements in CCDs have focused on improving the sub-electron noise levels for particle detection and enhancing readout speeds through simulation studies. The main objective of this study is to replace the analog processing of CCD signals using the digital-correlated double sampling (DCDS) technique. DCDS allows post-acquisition noise correction through intermittent sampling of an internal reference voltage to provide compact and flexible performance. In this study, DCDS was evaluated using two digital processing systems, namely, a 2.5 mega-samples per second (MSPS) 24-bit analog-to-digital converter (ADC) board and a 250 MSPS 16-bit ADC field-programmable-gate-array( FPGA)-based buffer memory board. The readout noise value at 74 kpix/s (7.1 e) was a significant improvement over that obtained with analog processing (9.7 e). The DCDS implementation demonstrates optimal signal-to-noise ratio for a wide range of readout speeds. Parameters such as the sample positions per pixel, number of samples, and number of pixels were identified to be essential in achieving an accurate gain value. Finally, hardware implementation of the DCDS IP core algorithm on a Xilinx Zynq-7000 AP system-on-a-chip (SoC) showed a significant improvement in power dissipation (7.1 W) compared to the analog Monsoon correlated double sample (CDS) circuit (13.6 W). The DCDS IP core implementation also showed a background noise reduction of up to 34% compared to DCDS offline readout processing using a Python algorithm.

Advanced, Real-Time Programmable FPGA-Based Digital Filtering Unit for IR Detection Modules

This paper presents a programmable digital filtering unit dedicated to operating with signals from infrared (IR) detection modules. The designed device is quite useful for increasing the signal-to-noise ratio due to the reduction in noise and interference from detector–amplifier circuits or external radiation sources. Moreover, the developed device is flexible due to the possibility of programming the desired filter types and their responses. In the circuit, an advanced field-programmable gate array FPGA chip was used to ensure an adequate number of resources that are necessary to implement an effective filtration process. The proposed circuity was assisted by a 32-bit microcontroller to perform controlling functions and could operate at frequency sampling of up to 40 MSa/s with 16-bit resolution. In addition, in our application, the sampling frequency decimation enabled obtaining relatively narrow passband characteristics also in the low frequency range. The filtered signal was available in real time at the digital-to-analog converter output. In the paper, we showed results of simulations and real measurements of filters implementation in the FPGA device. Moreover, we also presented a practical application of the proposed circuit in cooperation with an InAsSb mid-IR detector module, where its self-noise was effectively reduced. The presented device can be regarded as an attractive alternative to the lock-in technique, artificial intelligence algorithms, or wavelet transform in applications where their use is impossible or problematic. Comparing the presented device with the previous proposal, a higher signal-to-noise ratio improvement and wider bandwidth of operation were obtained.