FPGA Research Articles

Advanced Security Strategies for Software Vulnerability Protection: A Multi-Scale Detection Model With FPGA-RFID

This paper proposes a multi-scale software vulnerability detection model using Radio Frequency Identification (RFID) target recognition technology and Field-Programmable Gate Array (FPGA) hardware design. The systematic analysis of RFID systems and FPGA architectures provides the foundation for constructing robust security solutions against code-based threats. The Scalable Vulnerability Detection Method (SVDM) is developed leveraging multi-scale code metrics and deep feature extraction techniques. The evaluations of vulnerability datasets CWE-119 and CWE-399 demonstrated over 84% accuracy, recall, and F1 score. The precision, recall, and F1 score of the CWE-399 vulnerability dataset in the SVDM were 85.15%, 85.12%, and 84.79%, respectively, while the values of the CWE-199 dataset were 83.12%, 82.16%, and 82.38%, respectively. Compared with existing methods, the functionality of SVDM was further highlighted. This research provides an extensible and adaptable framework for identifying security vulnerabilities with both hardware and software techniques. It can optimize threat detection, risk analysis, and system integrity across software development and operation life cycles, providing technical reference and scientific support for the security protection of software vulnerabilities, while promoting the development of industries such as intelligent monitoring and traceability.

Graph-OPU: A Highly Flexible FPGA-Based Overlay Processor for Graph Neural Networks

Field-programmable gate arrays (FPGAs) are an ideal candidate for accelerating graph neural networks (GNNs). However, the FPGA redeployment process is time-consuming when updating or switching between diverse GNN models across different applications. Existing GNN processors eliminate the need for FPGA redeployment when switching between different GNN models. However, adapting matrix multiplication types by switching processing units decreases hardware utilization. In addition, the bandwidth of DDR limits further improvements in hardware performance. This article proposes a highly flexible FPGA-based overlay processor for GNN accelerations. Graph-OPU provides excellent flexibility and programmability for users, as the executable code of GNN models is automatically compiled and reloaded without requiring FPGA redeployment. First, we customize the compiler and instruction sets for the inference process of different GNN models. Second, we customize the datapath and optimize the data format in the microarchitecture to fully leverage the advantages of high bandwidth memory (HBM). Third, we design a unified matrix multiplication to handle both sparse-dense matrix multiplication (SpMM) and general matrix multiplication (GEMM), enhancing Graph-OPU performance. During Graph-OPU execution, the computational units are shared between SpMM and GEMM instead of being switched, which improves the hardware utilization. Finally, we implement a hardware prototype on the Xilinx Alveo U50 and test the mainstream GNN models using various datasets. Experimental results show that Graph-OPU achieves up to 1,654 \(\times\) and 63 \(\times\) speedup, as well as up to 5,305 \(\times\) and 422 \(\times\) energy efficiency boosts, compared to implementations on CPU and GPU, respectively. Graph-OPU outperforms state-of-the-art (SOTA) end-to-end overlay accelerators for GNN, reducing latency by an average of 1.36 \(\times\) and improving energy efficiency by 1.41 \(\times\) on average. Moreover, Graph-OPU exhibits an average 1.45 \(\times\) speed improvement in end-to-end latency over the SOTA GNN processor. Graph-OPU represents an in-depth study of an FPGA-based overlay processor for GNNs, offering high flexibility, speedup, and energy efficiency.

Accelerating DTLS on SoC FPGA for secure IoT applications

In the realm of embedded systems and IoT, efficiency and security are among paramount challenges. Datagram Transport Layer Security (DTLS) plays a crucial role in securing IoT communication, but it often imposes significant computational overhead. Stemming from these observations, this study introduces an innovative solution using an System-on-Chip (SoC) Field Programmable Gate Array (FPGA) to address these challenges. Notably, the study effectively demonstrates the integration of DTLS acceleration into the IoT network stack, utilizing the inherent Application-Specific Integrated Circuit (ASIC) cryptographic accelerators embedded within the SmartFusion2 SoC FPGA. The detailed experiments have been conducted for the comparison of the developed hardware with a software implementation of DTLS. The results are remarkable, showcasing substantial gains in key metrics. These improvements include a performance increase of 8 times, a latency reduction of 8.1 times, and a decrease in power consumption of 1.5 times. In summary, this study highlights the crucial role of hardware acceleration, enabled by heterogeneous computing units on a single chip, in enhancing IoT security. The findings underscore the value of SoC FPGAs as an a practical solution for enabling secure IoT communication across a spectrum of IoT applications.

A digital neuromorphic system for working memory based on spiking neuron-astrocyte network

Among various types of memory, working memory (WM) plays a crucial role in reasoning, decision-making, and behavior regulation. Neuromorphic computing is a well-established engineering approach that offers promising avenues for advancing our understanding of WM processes by mimicking the structure and operation of the human brain using electronic technology. In this work, a digital neuromorphic system is proposed and then implemented in hardware to illustrate the real-time WM process based on the spiking neuron-astrocyte network (SNAN). The implemented SNAN utilizes a bidirectional neuron-astrocyte interaction to realize the WM process, allowing for a more brain-like memory emulation. Various hardware optimization methods, including piecewise linear approximation, double buffering, and time multiplexing are recruited to minimize the area and power consumption and facilitate the implementation of the WM concept on a single field programmable gate array (FPGA) chip. The proposed neuromorphic system is evaluated by testing its capacity for multi-item memory formation, an essential characteristic of human WM. The results show that the time duration between the store and recall phases is a critical parameter for acceptable retrieval performance. Additionally, the results demonstrate that the proposed neuromorphic system for WM is resilient to noise. Finally, the design modularity of the system facilitates easy extension for implementing larger networks and adapting to real-world applications.

Protocol-aware approach for mitigating radiation-induced errors in free-space optical downlinks

Multigigabit per second satellite-to-ground communications are evolving owing to free-space optical (FSO) communications. They benefit greatly from the use of commercial off-the-shelf field-programmable gate arrays, which offer higher performance than their space-grade counterparts. However, these capabilities are severely diminished in the case of improper implementation of radiation mitigation schemes not being properly assessed. Although these schemes have been improved over the years, they can be further optimized. Therefore, this study proposes, to our knowledge, a new protocol-aware approach, tailored for FSO satellite downlinks, to classify the criticality of radiation-induced errors. This approach can achieve a reduction in overhead by nearly an order of magnitude compared to current protection schemes.

Towards sustainable AI: a comprehensive framework for Green AI

The rapid advancement of artificial intelligence (AI) has brought significant benefits across various domains, yet it has also led to increased energy consumption and environmental impact. This paper positions Green AI as a crucial direction for future research and development. It proposes a comprehensive framework for understanding, implementing, and advancing sustainable AI practices. We provide an overview of Green AI, highlighting its significance and current state regarding AI’s energy consumption and environmental impact. The paper explores sustainable AI techniques, such as model optimization methods, and the development of efficient algorithms. Additionally, we review energy-efficient hardware alternatives like tensor processing units (TPUs) and field-programmable gate arrays (FPGAs), and discuss strategies for designing and operating energy-efficient data centers. Case studies in natural language processing (NLP) and Computer Vision illustrate successful implementations of Green AI practices. Through these efforts, we aim to balance the performance and resource efficiency of AI technologies, aligning them with global sustainability goals.

Reconfigurable Acceleration of Neural Networks: A Comprehensive Study of FPGA-based Systems

This paper explores the potential of Field-Programmable Gate Arrays (FPGAs) for accelerating both neural network inference and training. We present a comprehensive analysis of FPGA-based systems, encompassing architecture design, hardware implementation strategies, and performance evaluation. Our study highlights the advantages of FPGAs over traditional CPUs and GPUs for neural network workloads, including their inherent parallelism, reconfigurability, and ability to tailor hardware to specific network needs. We delve into various hardware implementation strategies, from direct mapping to dataflow architectures and specialized hardware blocks, examining their impact on performance. Furthermore, we benchmark FPGA-based systems against traditional platforms, evaluating inference speed, energy efficiency, and memory bandwidth. Finally, we explore emerging trends in FPGA-based neural network acceleration, such as specialized architectures, efficient memory management techniques, and hybrid CPU-FPGA systems. Our analysis underscores the significant potential of FPGAs for accelerating deep learning applications, particularly those requiring high performance, low latency, and energy efficiency.

FPGA Readout for Frequency-Multiplexed Array of Micromechanical Resonators for Sub-Terahertz Imaging.

Field programmable gate arrays (FPGAs) have not only enhanced traditional sensing methods, such as pixel detection (CCD and CMOS), but also enabled the development of innovative approaches with significant potential for particle detection. This is particularly relevant in terahertz (THz) ray detection, where microbolometer-based focal plane arrays (FPAs) using microelectromechanical (MEMS) resonators are among the most promising solutions. Designing high-performance, high-pixel-density sensors is challenging without FPGAs, which are crucial for deterministic parallel processing, fast ADC/DAC control, and handling large data throughput. This paper presents a MEMS-resonator detector, fully managed via an FPGA, capable of controlling pixel excitation and tracking resonance-frequency shifts due to radiation using parallel digital lock-in amplifiers. The innovative FPGA architecture, based on a lock-in matrix, enhances the open-loop readout technique by a factor of 32. Measurements were performed on a frequency-multiplexed, 256-pixel sensor designed for imaging applications.

Accelerating data acquisition with FPGA-based edge machine learning: a case study with LCLS-II

Abstract New scientific experiments and instruments generate vast amounts of data that need to be transferred for storage or further processing, often overwhelming traditional systems. Edge Machine Learning (EdgeML) addresses this challenge by integrating
Machine Learning (ML) algorithms with edge computing, enabling real-time data processing directly at the point of data generation. EdgeML is particularly beneficial for environments where immediate decisions are required, or where bandwidth and
storage are limited. In this paper, we demonstrate a high-speed configurable ML model in a fully customizable EdgeML system using a Field Programmable Gate Array (FPGA). Our demonstration focuses on an angular array of electron spectrometers,
referred to as the ’CookieBox,’ developed for the Linac Coherent Light Source II (LCLS-II) project. The EdgeML system captures 51.2 Gbps from a 6.4 GS/s analog to digital converter and is designed to integrate data pre-processing and ML inside an
FPGA. Our implementation achieves an inference latency of 0.2 μs for the ML model, and a total latency of 0.4 μs for the complete EdgeML system, which includes preprocessing, data transmission, digitization, and ML inference. The modular design of
the system allows it to be adapted for other instrumentation applications requiring low-latency data processing.

AESware: Developing AES-enabled low-power multicore processors leveraging open RISC-V cores with a shared lightweight AES accelerator

As open-source RISC-V cores continue to be released, the development of low-power multicore processors utilizing these cores is invigorating the edge/IoT device market. Nevertheless, comprehensive research on developing low-power multicore processors with integrated security features using existing open RISC-V cores remains limited. This study addresses this gap by introducing AESware, a dedicated lightweight hardware designed for energy-efficient AES (Advanced Encryption Standard) task execution, contributing to the development of AES-specific low-power RISC-V multicore processors. AESware supports variable key lengths and ensures minimal power consumption with a compact design. This standalone IP (Intellectual Property) is compatible with various open RISC-V cores, offering scalability and convenience. And importantly, we propose the most energy-efficient architecture for multicore processors equipped with AESware. Instead of assigning dedicated AESware to each core, we introduce a shared AESware architecture to maximize energy efficiency. We develop an operational algorithm for task scheduling in AESware, achieving maximum utilization and minimal latency while maintaining its lightweight nature. To evaluate our solution, we developed 24 processors into three groups: AESware-equipped, baseline, and those with an external AES accelerator per core. After FPGA (Field-Programmable Gate Array) prototyping for functional verification and power consumption analysis via 45 nm process technology synthesis, our findings revealed significant energy savings. AESware-equipped processors achieved up to 76%, 47%, and 33% energy savings at dual-, quad-, and octa-core configurations compared to baseline, respectively, and were more energy-efficient in running AES applications than those with individual accelerators.

A Survey on Design Space Exploration Approaches for Approximate Computing Systems

Approximate Computing (AxC) has emerged as a promising paradigm to enhance performance and energy efficiency by allowing a controlled trade-off between accuracy and resource consumption. It is extensively adopted across various abstraction levels, from software to architecture and circuit levels, employing diverse methodologies. The primary objective of AxC is to reduce energy consumption for executing error-resilient applications, accepting controlled and inherently acceptable output quality degradation. However, harnessing AxC poses several challenges, including identifying segments within a design amenable to approximation and selecting suitable AxC techniques to fulfill accuracy and performance criteria. This survey provides a comprehensive review of recent methodologies proposed for performing Design Space Exploration (DSE) to find the most suitable AxC techniques, focusing on both hardware and software implementations. DSE is a crucial design process where system designs are modeled, evaluated, and optimized for various extra-functional system behaviors such as performance, power consumption, energy efficiency, and accuracy. A systematic literature review was conducted to identify papers that ascribe their DSE algorithms, excluding those relying on exhaustive search methods. This survey aims to detail the state-of-the-art DSE methodologies that efficiently select AxC techniques, offering insights into their applicability across different hardware platforms and use-case domains. For this purpose, papers were categorized based on the type of search algorithm used, with Machine Learning (ML) and Evolutionary Algorithms (EAs) being the predominant approaches. Further categorization is based on the target hardware, including Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), general-purpose Central Processing Units (CPUs), and Graphics Processing Units (GPUs). A notable observation was that most studies targeted image processing applications due to their tolerance for accuracy loss. By providing an overview of techniques and methods outlined in existing literature pertaining to the DSE of AxC designs, this survey elucidates the current trends and challenges in optimizing approximate designs.

Charge-coupled device readout by digital-correlated double sampling

Charge-coupled devices (CCDs) play crucial roles in astronomy owing to their widespread use in the optical band, offering high sensibility, low noise, high dynamic range, and high spatial resolution. Recent advancements in CCDs have focused on improving the sub-electron noise levels for particle detection and enhancing readout speeds through simulation studies. The main objective of this study is to replace the analog processing of CCD signals using the digital-correlated double sampling (DCDS) technique. DCDS allows post-acquisition noise correction through intermittent sampling of an internal reference voltage to provide compact and flexible performance. In this study, DCDS was evaluated using two digital processing systems, namely, a 2.5 mega-samples per second (MSPS) 24-bit analog-to-digital converter (ADC) board and a 250 MSPS 16-bit ADC field-programmable-gate-array( FPGA)-based buffer memory board. The readout noise value at 74 kpix/s (7.1 e) was a significant improvement over that obtained with analog processing (9.7 e). The DCDS implementation demonstrates optimal signal-to-noise ratio for a wide range of readout speeds. Parameters such as the sample positions per pixel, number of samples, and number of pixels were identified to be essential in achieving an accurate gain value. Finally, hardware implementation of the DCDS IP core algorithm on a Xilinx Zynq-7000 AP system-on-a-chip (SoC) showed a significant improvement in power dissipation (7.1 W) compared to the analog Monsoon correlated double sample (CDS) circuit (13.6 W). The DCDS IP core implementation also showed a background noise reduction of up to 34% compared to DCDS offline readout processing using a Python algorithm.

Advanced, Real-Time Programmable FPGA-Based Digital Filtering Unit for IR Detection Modules

This paper presents a programmable digital filtering unit dedicated to operating with signals from infrared (IR) detection modules. The designed device is quite useful for increasing the signal-to-noise ratio due to the reduction in noise and interference from detector–amplifier circuits or external radiation sources. Moreover, the developed device is flexible due to the possibility of programming the desired filter types and their responses. In the circuit, an advanced field-programmable gate array FPGA chip was used to ensure an adequate number of resources that are necessary to implement an effective filtration process. The proposed circuity was assisted by a 32-bit microcontroller to perform controlling functions and could operate at frequency sampling of up to 40 MSa/s with 16-bit resolution. In addition, in our application, the sampling frequency decimation enabled obtaining relatively narrow passband characteristics also in the low frequency range. The filtered signal was available in real time at the digital-to-analog converter output. In the paper, we showed results of simulations and real measurements of filters implementation in the FPGA device. Moreover, we also presented a practical application of the proposed circuit in cooperation with an InAsSb mid-IR detector module, where its self-noise was effectively reduced. The presented device can be regarded as an attractive alternative to the lock-in technique, artificial intelligence algorithms, or wavelet transform in applications where their use is impossible or problematic. Comparing the presented device with the previous proposal, a higher signal-to-noise ratio improvement and wider bandwidth of operation were obtained.

STEP-NC compliant 3-axis CNC machine controller based on Field-Programmable Gate Arrays

ABSTRACT Manufacturing processes have gone through several transformations in history. Previously, G&M codes served as a common programming language for CNC machines. Codes of CNC machines contain the information related to the tools and trajectories. G&M codes are machine-specific and vendors must customize them for the tools installed on a particular machine. STEP-NC, described by ISO-14649, provides an alternative to G&M codes aiming at generic interoperability of CNC machine codes. STEP-NC includes information on both the trajectories and the tool’s specifications making it generic and machine-independent. STEP-NC is an emerging area and a gateway to intelligent machining targeting ‘design anywhere and develop anywhere’. Therefore, several researchers have developed software-based decoders and interpreters. They are difficult to implement on a serial pipelined processor limiting their use for real-time applications. This paper presents a Field Programmable Gate Array (FPGA)-based STEP-NC controller implemented and validated on a SPARTAN-3E kit. To the best of the author’s knowledge, this is the first FPGA-based implementation of STEP-NC. The main contribution of this work is a generic state-machine representation of the STEP-NC entities suitable for implementation on different FPGA platforms. The developed decoder was successfully tested and evaluated on a three-axis CNC machine for an example given in ISO-14649-11 for compliance.

High‐speed end‐to‐edge data caching and forwarding architecture based on field programmable gate array

AbstractThe application of the Internet of Things generates massive end‐device data. Traditional end‐to‐edge data caching methods lack parallelism, consume numerous resources, and lack data backup mechanisms. We propose a lightweight high‐speed data caching and forwarding architecture based on a field‐programmable gate array. In the basic scheme, a double‐data‐rate memory read/write mixed control method is proposed to efficiently cache massive amounts of data. To improve reliability, we propose address‐space virtualization to forward data to backup devices. To satisfy the demand for higher performance scenarios, we propose a real‐time data shunting mechanism to realize an optimized scheme that supports higher data rates. These two schemes support single‐link high‐speed data caching and forwarding at 10 and 40 Gbps. Compared with the existing method, the basic and optimized schemes improve the performance by 25% and four times and save 66% and 40% of the resources, respectively. Thus, we provide a lightweight and reliable high‐performance end‐to‐edge data caching solution for resource‐constrained edge devices.

EXPRESS: A Framework for Execution Time Prediction of Concurrent CNNs on Xilinx DPU Accelerator

Deep learning Processor Unit (DPU) is a highly configurable CNN accelerator that supports a variety of CNNs and can be implemented with multiple instances on the same FPGA. Many applications deploy concurrent execution of different CNNs and in such a setting, an execution time predictor can help “optimize” the DPU configurations to meet the performance requirements of different tasks. We characterize CNN execution on DPUs and reduce the variability in execution time due to interference from the operating system. Subsequently, we propose a machine learning-based framework (EXPRESS) to predict the execution time of any given CNN on a DPU configuration, considering CNN, DPU, and bus characteristics. We improvise EXPRESS to support heterogeneous CNNs in EXPRESS-2.0 by making features independent of the number of CNNs. Our entire experimentation is based on data from a real FPGA board for 16 standard CNNs. Our frameworks, EXPRESS and EXPRESS-2.0, significantly outperform state-of-the-art by achieving an average execution time prediction error of 2.2% and 0.7%, respectively. We illustrate the effectiveness of this low prediction error for design space exploration, which is very useful for embedded system application developers.

Optimizing embedded AI systems for autonomous driving: Challenges and solutions using bayesian networks

Abstract. Embedded Artificial Intelligence (AI) systems are important components of autonomous vehicles. However, incorporating AI into autonomous vehicles is technically complex, due to the constraints of computation, real-time processing of data, uncertainty handling, and hardware limitations. Bayesian Networks (BNs) are a promising method that allows probabilistic modelling in adaptive learning and environment perception. Here we report on an overview of the application of BNs on autonomous driving, with an emphasis on how BNs can be optimized for embedded system resource constraints, including both computational and energy. Various optimization techniques are discussed, such as model pruning, approximation, acceleration using hardware accelerators, such as Field-Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuit (ASICs), and advanced cooling and power management to ensure AI reliability under high computational load. By reviewing these approaches, we aim to contribute to the development of more robust and green AI systems for autonomous driving.

Seesaw: A 4096-bit vector processor for accelerating Kyber based on RISC-V ISA extensions

The ML-KEM standard based on Kyber algorithm is one of the post-quantum cryptography (PQC) standards released by the National Institute of Standards and Technology (NIST) to withstand quantum attacks. To increase throughput and reduce the execution time that is limited by the high computational complexity of the Kyber algorithm, an RISC-V-based processor Seesaw is designed to accelerate the Kyber algorithm. The 32 specialized extension instructions are mainly designed to enhance the parallel computing ability of the processor and accelerate all the processes of the Kyber algorithm by thoroughly analyzing its characteristics. Subsequently, by carefully designing hardware such as poly vector registers and algorithm execution units on the RISC-V processor, the support of microarchitecture for extension instructions was achieved. Seesaw supports 4096-bit vector calculations through its poly vector registers and execution unit to meet high-throughput requirements and is implemented on the field-programmable gate array (FPGA). In addition, we modify the compiler simultaneously to adapt to the instruction extension and execution of Seesaw. Experimental results indicate that the processor achieves a speed-up of 432× and 18864× for hash and NTT, respectively, compared with that without extension instructions and a speed-up of 5.6× for the execution of the Kyber algorithm compared with the advanced hardware design.

Construction and analysis of symmetric Sprott B multi-attractors with electric implementation

Abstract In chaos theory, a number of systems and models which apparently contain simple ordinary differential equations (ODEs) turn out to show a dynamic characterized by complicated behaviors and complex trajectories. One of such systems is the Sprott B model. We construct some set of multi-attractors based on the Sprott B model where additional parameters and operators are considered. After summarizing important preliminaries relevant to simple chaotic differential systems, the model is firstly solved analytically and numerically, then graphical simulations are provided. The later show coexistence and evolution of two chaotic attractors in a symmetrical representation. Lastly, similar results and expected outcomes are recovered via an electrical circuit implementation, realized using the Field Programmable Gate Array (FPGA) board, the Digital-to-Analog Converter (DAC) and the Rigol Oscilloscope. They also show progressing sets of coexisting multi-attractors.

Design and FPGA Implementation of a Hyper-Chaotic System for Real-time Secure Image Transmission

Recently, chaos theory has been widely used in multimedia and digital communications due to its unique properties that can enhance security, data compression, and signal processing. It plays a significant role in securing digital images and protecting sensitive visual information from unauthorized access, tampering, and interception. In this regard, chaotic signals are used in image encryption to empower the security; that's because chaotic systems are characterized by their sensitivity to initial conditions, and their unpredictable and seemingly random behavior. In particular, hyper-chaotic systems involve multiple chaotic systems interacting with each other. These systems can introduce more randomness and complexity, leading to stronger encryption techniques. In this paper, Hyper-chaotic Lorenz system is considered to design robust image encryption/ decryption system based on master-slave synchronization. Firstly, the rich dynamic characteristics of this system is studied using analytical and numerical nonlinear analysis tools. Next, the image secure system has been implemented through Field-Programmable Gate Arrays (FPGAs) Zedboard Zynq xc7z020-1clg484 to verify the image encryption/decryption directly on programmable hardware Kit. Numerical simulations, hardware implementation, and cryptanalysis tools are conducted to validate the effectiveness and robustness of the proposed system.