Field Limiting Ring Structure Research Articles

Influence of Surface Roughness on Breakdown Voltage of 4H-SiC SBD with FLR Structure

The Ti/4H-SiC Schottky barrier diodes with a field limiting ring (FLR) structure are fabricated. Two types of SBDs are prepared; one (SBD-A) is covered and another (SBD-B) isn’t covered with a carbon cap during high temperature annealing after ion implantation. The breakdown voltage at room temperature for SBD-A and SBD-B are 1400 V and 1000 V, respectively. The breakdown for both SBDs occurs due to an avalanche breakdown. The light emission images are obtained at the breakdown voltage by photo emission microscope (PEM). The light emission is observed along an FLR of the SBD-A as designed. On the other hand, the spot of light emission is observed on a FLR structure of the SBD-B. This light emission spot indicates that leakage current is concentrated because an electrical field concentration is generated at this one for the SBD-B. The root-mean-square roughness of the Al-implanted region on the FLR structure calculated from the atomic force microscopy (AFM) images for the SBD-A and the SBD-B are 0.697 nm and 5.58 nm, respectively. Therefore it is considered that large surface roughness on the FLR decreases breakdown voltage of SBD because an electrical field concentration is generated at a spot.

Improvement of SBD Electronic Characteristics Using Sacrificial Oxidation Removing the Degraded Layer from SiC Surface after High Temperature Annealing

Ion implantation and a subsequent annealing at high temperature are required for fabricating a high voltage Schottky Barrier Diode (SBD) with a field limiting ring (FLR) or a junction termination extension (JTE), but high temperature annealing degrades surface condition of a SiC substrate and induces a degradation of electronic characteristics of a fabricated SBD. To avoid a degradation of SBD electronic characteristics after high temperature annealing, the method of removing a degraded layer from a SiC surface by sacrificial oxidation after high temperature annealing is studied. In this study, we studied the relationship between the improvement of SBD electronic characteristics and the thickness of sacrificial oxide grown after high temperature annealing. 9~12 SBD without edge termination were fabricated on a SiC substrate of 4mm×4mm. The ratio of good chips to all chips (9~12 SBD) increases with increasing total thickness of sacrificial oxide grown after high temperature annealing at 1800oC for 30 s, where an SBD with a leakage current less than 1μA/cm2 at reverse voltage of –100V was defined as a good chip. We applied this process growing sacrificial oxide of 150nm after high temperature annealing to fabricate the SBD with an FLR structure designed with 600V blocking voltage on a Si-face SiC substrate. The SBD with an FLR structure through this process of 150 nm sacrificial oxide is low leakage current of less than 1μA/cm2 at reverse voltage of –100V and achieves 600V blocking voltage, however, the SBD with an FLR structure without the process of sacrificial oxide after high temperature annealing is high leakage current at reverse voltage of –100V. It is shown that this process growing sacrificial oxide after high temperature annealing is useful to fabricate an SBD with an FLR structure.

A New Junction Termination Method Employing Shallow Trenches Filled With Oxide

A new junction termination method employing shallow trenches filled with oxide, which successfully decreased the junction termination area, is proposed and fabricated without any complicated process such as Si-deep etching. Shallow trenches between the floating field limiting rings successfully redistributed the single electric field peak into two peaks so that the breakdown voltage could be increased with the same junction termination area. The experimental results show that the proposed method decreased the junction termination area by more than 25% compared to a conventional field limiting ring structure when breakdown voltages are equal.

Analytical model of three-dimensional effect on voltage and edge peak field distributions and optimal space for planar junction with a single field limiting ring

An analytical model of the three-dimensional (3-D) effect due to the lateral radius of the main junction and width of the ring junction on voltage and edge peak field profiles for the planar junction with a single floating electrical field limiting ring structure have been proposed for the first time. From this model analysis, the influence on the voltage and edge peak field of the reverse voltage, 3-D factors such as lateral curvature of the main junction and width of the ring junction, space distance between the main junction and ring junction and junction depth are analyzed, and then the expressions for predicting the optimal space and maximum breakdown voltage are also obtained. The analytical results are in agreement with the previous numerical analysis.

An Analytic Model of Planar Junctions with Multiple Floating Field Limiting Rings

A potential function satisfying the two-dimensional Poisson equation for planar junctions with a single field limiting ring(FLR) is presented for the first time which allows an approximate but quick determination of the breakdown voltage and optimized ring spacing. The problem of the multiple rings is then reduced to that of a single ring by means of the equivalent ring junction applied in sequence from the outmost ring. The results are in fair agreement with two-dimensional device simulations using MEDICI. Comparisons with experimental data reported for the optimum ring spacings and the relative improvement on the breakdown voltage of the FLR structure show the validity of the model. The present model is very useful for the FLR structure with multiple rings, providing a starting point for the numerical simulations.

Junction breakdown analysis of a floating field-limiting ring structure using a pisces-2B device simulator

The method used to optimize the spacing between the main junction and the floating field limiting ring structure to improve breakdown voltage is presented. TMA PISCES-2B Version 9033, a 2-D device simulation program extended to a quasi-3-D simulator using cylindrical coordinates, is used to analyze this structure and evaluate design alternatives. The junction-to-ring structure spacing is varied from 0.5 to 5.5 μm in steps of 1.0 μm and each structure is evaluated for its associated junction breakdown characteristics. Both rectangular and cylindrical coordinates are used for comparison purposes. The field-limiting structure ranges from a one-guard-ring to a two-guard-ring structure. Breakdown characteristics are determined by plotting the I- V curves, electric field lines, impact ionization generation rate, potential contours, and current flowlines.

Comments on "Computer study of a high-voltage p-π-n--n+diodes and comparison with a field-limiting ring structure

Comments on "Computer study of a high-voltage p-π-n^--n⁺diodes and comparison with a field-limiting ring structure

Computer study of a high-voltage a p-π-n--n+diode and comparison with a field-limiting ring structure

The paper presents a two-dimensional numerical analysis of a high-voltage p-π-n--n+structure. The effect of the device parameters, such as the implanted dose of the π-region, the main junction depth, and the charges at the interface, is studied. A comparison between the p-π-n--n+and field-limiting ring structures is given.