Field-induced Charged Device Model Research Articles

Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors

The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.

Full-Component Modeling and Simulation of Charged Device Model ESD

This paper presents a methodology to construct an equivalent circuit model of a packaged integrated circuit mounted on a field-induced charged device model electrostatic discharge tester. Circuit simulation is used to obtain the full-component current and voltage distributions. This paper focuses on predicting overvoltage stress at power domain crossing circuits.

Comparison of FICDM and Wafer-Level CDM Test Methods

The on-chip stresses induced by various charged device model (CDM) test methods are compared at both the package and wafer levels. Test methods studied include field-induced CDM (FICDM), wafer-level CDM (WCDM2), capacitively coupled transmission-line pulsing (CC-TLP), and very fast TLP (VF-TLP). The generated stresses are compared on the basis of voltage monitor readings and integrated circuit (IC) functional failures. In general, core circuit failures induced by FICDM are replicated on the wafer level. Package-related parasitics can alter the externally measured FICDM current pulse relative to that delivered internal to the IC, causing miscorrelation with wafer-level testers.

Comparison of Wafer-Level With Package-Level CDM Stress Facilitated by Real-Time Probing

Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.

Analysis of the Effect of ESD on the Operation of MEMS

The effect of charge injection due to electrostatic discharge on the operation of capacitive microelectromechanical-systems (MEMS) structures is studied. A summary of charge transfer for the human-body model, the charged-device model (CDM), and the field-induced CDM is presented. The reliability of MEMS due to the trapped charge is assessed using a figure of merit based on the forces due to the voltage and charge states of operation. An electric-field model for the air gap and dielectric layer is employed to determine surface-charge densities to yield the breakdown of the air gap or dielectric layer and the onset of stiction.

Review of Charge and Potential Control of Electrostatic Discharge (ESD) in Microdevices

Various models have evolved to test the sensitivity of electronic devices to electrostatic discharge (ESD), which include the human body model, machine model, and field-induced charged device model. The objective of this paper is to review both the static and dynamic aspects of these models and to analyze the charge and potential control of ESD events. Charge and geometry sensitivity factors are defined for a general two-body problem. The results should provide a better understanding of models that are used to simulate the direct effect of ESD and to provide methods to evaluate the effectiveness of ESD control processes. In particular, the electrostatic implications of small-gap geometries with application to microelectromechanical systems are reviewed.

The impact of ground plane size upon the performance of Field-induced Charged Device Model ESD testing systems

Experimental measurements of peak stressing current in a laboratory prototype Field-induced Charged Device Model (FCDM) ESD testing system have revealed a nonlinear dependence upon ground plane area and test module capacitance. This dependence is explained by an expanded equivalent circuit model for the testing system that takes explicit account of the parasitic capacitance between the ground plane on the test head and the underlying field plate. The results of this work underscore the importance of ensuring that the ground plane is sufficiently large to cover the device under test.

Electrostatic field limits and charge threshold for field-induced damage to voltage susceptible devices

We have studied electrostatic field and charge threshold limits for damage to MOSFET devices in order to understand the ESD damage risks during handling in electronics production and assembly processes. The study covers both field-induced charged device model (CDM) and charged board model (CBM) cases. The charging electrostatic field for failure can be even two orders of magnitude lower for a device on a board than at component level. The charge level for failure remains approximately constant. Our results show that charge threshold for failure would serve as a good guide for ESD risks of voltage susceptible MOSFETs as discrete components and when assembled to PWBs.

A comparison of electrostatic discharge models and failure signatures for CMOS integrated circuit devices

Six different CMOS device codes were evaluated, according to available test standards, for electrostatic discharge (ESD) sensitivity using three ESD models: human body model (HBM). machine model (MM), and field-induced charged device model (FCDM). Four commercially available simulators were used: two to perform the HBM ESD evaluations and two to perform the MM ESD evaluations. FCDM stressing was performed using an AT&T designed simulator. The failure threshold voltage and failure signature associated with each ESD model and simulator were determined for each test sample. Threshold correlation and regression analyses were also performed. Though the three ESD models and simulators created multiple failure signatures, they do not exhibit a high degree of overlap. Our results will show a high correlation between the ESD thresholds, failing pins, failing circuitry, and failing structures for HBM and MM stressing of the device codes evaluated.

Analysis of the charge transfer of models for electrostatic discharge (ESD) and semiconductor devices

Various models are used to simulate the electrostatic discharge (ESD) event associated with semiconductor devices; these include the human body model (HBM), the charged device model (CDM), and the field induced charged device model (FCDM). Maxwell's method is used to analyze these models to determine device potentials and the transfer of charge during typical discharges; existing test methods are also examined. A charge injection test method is introduced which provides control of the charge transferred to the device under test; it is proposed as a means to study charge related phenomena due to ESD.

A correlation study between different types of CDM testers and "real" manufacturing in-line leakage failures

Charged device model (CDM) tests generated ESD failures that correlated closely to assembly/test manufacturing in-line leakage failures. Both the "field induced noncontact" and "socketed" CDM testers correctly identified the weakest pins in a 0.8-/spl mu/m CMOS technology device. A correlation of the initial fail voltage was found between the different field-induced CDM testers and the eight weakest pins. Similar CDM-tests found a weak pin to pin correlation between the two different socketed CDM testers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>